RU2037190C1 - Multichannel system for recording physical quantities - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: system is designed for measuring, recording, and analyzing current values of physical quantities and forms of physical processes. System has analog measurement channels 1, group 3 of main memory units, OR gate 5, off-line control unit 8, and interface 9. In addition, system is provided with digital measurement channels 2, group 4 of main memory units, groups 6,7 of NOT gates, magnetic-tape storage 11, computing unit 12, and stop button 14. EFFECT: improved accuracy of system due to introduction of structural and informative redundancy and test methods of error correction, enlarged functional capabilities of system. 8 cl, 12 dwg

Description

 The invention relates to computer technology and can be used for its intended purpose for measuring, recording and analyzing the current values of physical quantities of material, energy and information groups, as well as for analyzing the form of physical processes.

 Known multi-channel systems for recording physical quantities [1] containing amplifiers, analog-to-digital converters, memory blocks, a channel switch, a control unit and a recorder.

 The principle of operation of known systems consists in adaptive or non-adaptive sampling of the processes under study, sampling the discrete values of the signals, converting them into a digital code and storing codes in memory blocks to subsequently restore the shape of the studied signals or process the received data.

 The well-known multichannel systems are characterized by insufficient accuracy and limited functionality, since they do not provide for the use of structural-algorithmic error correction methods, and the process itself is limited to registering the shape of the sensor output signals. In addition, the known systems are designed to study the physical quantities of only one group, for example, energy.

 Known multi-channel system for recording physical quantities [2] In the known system, it is possible to quickly set the desired sampling frequencies on the specified sections of the registration period. This allows you to significantly reduce the amount of memory blocks when registering transients and pulses of complex shape. In addition, it is possible to play sequentially a series of complete recording periods with a given sampling rate in each recording period. This allows, for example, to automatically change the test program of various sources of analog signals in a given frequency range. However, the well-known multi-channel system is characterized by limited functionality and insufficient registration accuracy.

 Known multi-channel system does not provide measurement and registration of discrete quantities. The presence of information redundancy is not used to improve the accuracy of measurements and registration. No methods for correcting errors of measuring channels have been implemented, there is no diagnostics of the operability of the main functional blocks of the system. The noted drawbacks limit the widespread use of the known system for recording physical quantities and processes.

 The aim of the invention is to increase accuracy by introducing structural and information redundancy and using test methods for error correction, as well as expanding the scope of the system in terms of measuring and recording analog and discrete values, using autonomous control and data storage, etc.

 Figure 1 shows the structural diagram of a multi-channel system for recording physical quantities; figure 2 structural diagram of the analogue measurement channels; figure 3 is a structural diagram of discrete measurement channels; figure 4 is a structural diagram of the i-th block of random access memory (BOP); figure 5 is a structural diagram of an autonomous control unit; Fig.6 is a structural diagram of a control panel included in the autonomous control unit; 7 is a structural diagram of one of the buffer storage devices included in the autonomous control unit; on Fig structural diagram of the interface; Fig.9 stress diagrams characterizing the operation of the system in time; figure 10 and 11 structural diagram of the algorithm of the system; on Fig diagrams of stresses characterizing the process of recording signals.

 In Fig. 1, the following notation is adopted: 1 analog measurement channels, 2 discrete measurement channels, 3 and 4 blocks of RAM of the first and second groups, 5 OR element, 6 and 7, the first and second groups of NOT elements, 8 autonomous unit control, 9 interface, 10 common bus, 11 tape drive, 12 computing unit (PC), 13 processor, 14 stop button.

 In Fig. 2, the following notation is adopted: 15 reference voltage source, 16 element "2I-OR-NOT", 17 element "NOT", 18 pulse counter, 19 element "OR-NOT", 20 one-shot, 21 light indication unit, 22 analog signal switch, 23 shaper; 24 analog-to-digital converter, 25.1-25.m m sensors, 26.1-26.m m adders, 27 first analogue storage device, 28.1-28. m m even analogue storage devices, 29.1-29.m m odd analogue storage devices.

Figure 3 adopted the following notation: 30 switch digital signals, 31.1-31. R _s R _s pulse counters, 32 (R _s +1) th pulse counter, 33 R _s +2 pulse counter, 34 OR element, 35.1-35.R _p R _p registers, 36 (R _p +1) register, 37.1-37. R _s first R _s formers, 38.1-38.R _p second R _p formers, 39 (K _f +1) th (where R _f R _s + R _p ) former, 40.1-40.R _k R _k comparators, 41 single vibrator.

 In figure 4, the following notation is adopted: 42 decoder, 43,44,45 first, second and third pulse counters, 46 and 47 first and second elements "2I-OR-NOT", 48,49 and 50 first, second and third elements AND-NOT, 51 and 52, the first and second elements, OR-NOT, 53 and 54, the first and second one-shot, 55,56,57,58,59,60,61 and 62 the first, second, third, fourth, the fifth, sixth, seventh and eighth elements of “AND”, 63.64.65 and 66 the first, second, third and fourth elements of “NOT”, 67 and 68 the first and second triggers, 69-75 seven elements of “3I-OR-NOT ", 76-99 twenty-four memory blocks, 100 and 101 first and second four-digit real formers.

 In Fig. 5, the following designations are adopted: 102 crystal oscillator, 103 pulse counter, 104 element 3-OR-NOT, 105 element "I", 106 and 107 first and second elements "OR", 108 block of elements "2-OR ", 109 controlled frequency divider, 110, 111, 112, 113, 114 and 115 first, second, third, fourth, fifth and sixth registers, 116 and 117 first and second decoders, 118 trigger, 119.1-119.NN odd buffer memory devices, 120.1-120.NN of even buffer memory devices, 121 (2N + 1) -th buffer memory device, 122.1-122. N N main reverse counters, pulses, 123.1-123. N N additional reverse pulse counters, 124 (N + 1) -th additional reverse pulse counter, 125.1-125.N first N elements "NAND", 126.1-126. N second N NAND elements, 127 reset pulse shaper, 128 control panel.

 In FIG. 6 the following designations are accepted: 129 136, 137, 138, 139-142, 142-145, 146, 147, 148, 149 and 150 the first-eighth, ninth, tenth, eleventh-fourteenth, fourteenth-seventeenth, eighteenth, nineteenth, twentieth , twenty first and twenty second buttons, 151 158, 159, 160, 161 164, 164 167, 168, 169, 170, 171, 172 first to eighth, ninth, tenth, eleventh to fourteenth, fourteenth to seventeenth, eighteenth, nineteenth, twentieth, twenty-first, twenty-second and twenty-third pulse shapers, 173 pulse counters, 174, 175, 176 and 177 first, second, third and fourth the second trigger, 178 OR element, 179 register, 180 decoder, 181 light indication unit.

 In Fig. 7, the following notation is adopted: 182 "OR" element, 183 and 184 first and second single vibrators, 185 "NAND" element, 187 pulse counter, 188 memory block.

 In FIG. 8 marked: 189 transceivers, 190 and 191 first and second decoders, 192 data output register, 193 command register, 194 input register, 195 state register, 196 transmitter, 197 receiver.

 The conclusions of 8.1-8.N analog and discrete channels 1 and 2 measurements are connected to the information inputs 1-12 of blocks 3 and 4 of RAM, respectively.

 Control inputs (inputs 1-6 and output 7) of channels 2 and 3 are connected to inputs / outputs (to outputs 11.1-11. N, 12.1-12.N, 13,1,2,4 and inputs 24.1-24.N respectively) block 8 of the autonomous system control. The findings of the button “stop.” 14 are connected to a constant voltage source “U” and a control input 24 of the autonomous control unit 8. The outputs of the autonomous control unit 8 (outputs 7.1-7.N, 8.1-8.N, 9.1-9.N, 10.1-10.N, 3,5,6 and 13) are connected to the combined control inputs (35,13-19 , 20-24,32,28,27,34 and 25, respectively) of the corresponding blocks 3 and 4 of the RAM of both groups. Information inputs of discrete channels of 2 measurements are system inputs. The information outputs of the same name 1-8 blocks 3 and 4 of the RAM of both groups are interconnected and connected to the information inputs (inputs 4-11) of the interface 9. The outputs (1-23) of the interface 9 are connected to the information inputs (inputs of the same name 1-23) unit 8 autonomous control. The first control outputs (outputs 9) of blocks 3 and 4 of the RAM of both groups are connected to the inputs of the OR element 5. The output of the OR element 5 is connected to the first control input of the interface 9. The second and third control outputs (outputs 10 and 11) of the blocks 3 and 4 of the RAM of both groups are connected to the inputs of the corresponding elements "NOT" 6 and 7, respectively, of the first and second groups. The outputs of the elements "NOT 6 and 7 are connected, respectively, to the second (2N) and third (3N) control inputs of the interface 9.

 The inputs / outputs of the interface 9 are connected to the inputs / outputs of the computer 12, the processor 13 and the tape drive 11 through a common bus 10.

 In each of the N analog channels 1 of the system measurement, the first inputs m of the adders 26.1.26.m are connected to the reference signal source 15. The second inputs of the adders 26.1.26.m are connected to the signal (first inputs of the analog memory devices 28.1.28.m and connected to the outputs of the sensors 25.1.25.m respectively. The outputs of the m adders 26.1. 26. m are connected to the signal (first) odd inputs analogue storage devices 29.1-29.m. The signal (first) input of the first analogue storage device 27 is connected to the source of the reference signal 15.

 The outputs of the analog storage devices 27-29.m are connected to the inputs of the switch 22 of the analog signals, the control inputs of which are connected to the outputs of the pulse counter 18. The output of the highest level of the pulse counter 18 is additionally connected to the first input of the element "2I-OR-NOT" 16 and through a one-shot 20 with the first input of the OR-NOT element 19. The output of the OR-NOT element 19 is connected to the zero-setting input of the pulse counter 18.

 The second input of the OR-NOT element 19, the second, third and fourth inputs of the 2I-OR-NOT element 16 and the input of the element NOT 17 are the second, third, fourth, fifth and sixth control inputs of analog and discrete channels 1, respectively and 2 measurements.

 The output of the element “2 AND-OR-NOT" 16 is connected to the combined (second) synchronizing inputs of analogue storage devices 27.29.m.

In each of the discrete channels 2 of the system, the inputs of the switch 30 of the digital signals are connected, respectively, to the outputs R _{p of the} registers 35.1-35.R _p , (R _p +1) of the register 36, R _{s of the} pulse counters 31.1-31.R _s and a pair of outputs of the (R _s +1) th pulse counter 32. The control inputs of the digital signal switch 30 are connected to the inputs of the same OR element 34 and connected to the outputs of the (R _s +2) th pulse counter 33. Counting input of the pulse counter 33 connected through the (R _s +1) th driver 39 with the sixth control input of the discrete channel. The counting inputs (R _s +1) of the pulse counters 31.1.31.R _{s are} connected to the outputs of the corresponding R _s formers 37.1.37.R _s . The outputs R _p of the shapers 38.1. 38.R _p respectively connected to the control inputs R _p registers 35.1. 35. R _p . The inputs of the (R _p +1) th register 36 are connected to the outputs R _{k of the} comparators 40.1.40.R _k . Inputs for setting the zeros of the R _s and (R _p +2) th pulse counters 31.1. 31. R _s and 33 are interconnected and connected to the second control input of a discrete channel. The first, third, fourth and fifth control inputs of the discrete channel are free. The outputs of the switch 30 of the digital signals and the single-shot 31 are the information outputs of the discrete channel, the inputs of which are connected to the inputs R _{k of the} comparators 40.1-40. R _k , R _f formers 37.-37.R _s , 38.1-38.R _p and with inputs of registers 35.1-35. R _p .

 In blocks 3 and 4 of random access memory, the first and third inputs of the 3I-OR-NOT 69.75 elements are connected respectively to the first and second seven of the outputs of the parallel code of the first pulse counter 43 of the same name. The second inputs of the 3I-OR-NOT 69.75 elements are connected between themselves, with the first input of the first element "OR NOT" 51 and connected to the twenty-ninth input of the RAM block. The fourth inputs of the elements "3I-OR-NOT" 69.75 are interconnected and connected to the thirtieth input of the RAM block. The fifth inputs of the elements 3I-OR-NOT 69.75 are interconnected and connected to the output of the second one-shot 54. The sixth inputs of each element 3I-OR-NOT 69. 75 are connected to the corresponding outputs of the second pulse counter 44, starting from the least significant bit The outputs of the elements "3 AND-OR-NOT" 69.75 connected to interconnected by the same name address inputs of memory blocks 76.99.

 Three groups of inputs "D1" of memory blocks 76.99 are connected respectively to the inputs, for example, 1.12, 13.19, 20.24-th block of random access memory (BOP). The inputs "CAS" 1.8, 9.16 and 17.24 of the memory blocks 76.99 are interconnected, connected to the first inputs of the fourth, fifth and sixth elements "And" 58,59,60 and connected to the outputs of the first, second and third elements "And" 55 56.57, respectively. The RAS inputs of all memory blocks 76.99 are combined and connected to the output of the first OR-NOT element 51. The WE inputs of each eight memory blocks 76.99 (76.83, 84.91, 92.99) are interconnected and connected respectively to the outputs of the fourth, fifth, and of the sixth “And” elements 58.59 and 60. The second inputs of the fourth, fifth and sixth “And” elements 58.59 and 60 are interconnected, connected to the fourth input of the “2I-OR-NOT” element 47 and connected to the output of the third element "AND NOT" 50. The inputs of the same name on the 1.8th, 9.16th and 17.24th memory blocks 76.83, 84.91 and 91.99 are interconnected and connected (by Etara) to the inputs of the first and second four-digit bus drivers 108 and 109. The control inputs "HC" bus drivers 100 and 101 are interconnected and connected to the "U" supply terminal.

 The synchronizing inputs "VK" of the bus drivers 100 and 101 are connected to the inputs of the fourth element "NOT" 66, with the counting input of the third counter 45 pulses and are connected to the output of the first element "AND NOT" 48. The outputs 1.4 and 5.8 of the first and second bus drivers 100 and 101 are connected to outputs 1.4, 5.8 of the BOP. The ninth output of the BOP is connected to the output of the fourth element "NOT" 66. The twenty-fifth input of the BOP is connected to the input of the second element "NOT" 64 and to the zero-setting inputs of the first pulse counter 43. The twenty-sixth input is connected to the third input of the first 2N-OR-NOT element 46. The twenty-seventh input through the first one-shot 53 is connected to the first input of the second AND-NOT element 49. The twenty-eighth input is connected to the input of the second one-shot 54 and through the third the element "NOT" 65 with the counting input of the second pulse counter 44. The thirty-first input of the BOP is connected to the second input of the first element "OR-NOT" 51. The thirty-second and thirty-fourth inputs of the BOP are connected respectively to the installation inputs of the unit of the first and second triggers 67 and 68 Thirty tons The inputs and the thirty-fifth inputs are connected respectively to the first inputs of the seventh and eighth AND elements 61 and 62. The output of the eighth AND element 62 is connected to the second input of the third AND-NOT element 50. The second input of the eighth AND element 62 is connected with the tenth output of the BOP, with the second input of the eighth AND-NOT element 49, with the first input of the third AND-NOT element 50 and connected to the direct output of the second trigger 68. The zero setting input of the second trigger 68 is connected to the output of the second OR element -NOT "52, whose first input is connected to the output of the second element" NOT "64. The second input torogo element "NOR" 52 is connected to first and second inputs of the first element "2I-NOR" 46 and connected to the next digit of the first counter 43 pulses. The inverse output of the second trigger 68 is connected to the third input of the seventh AND element 61. The output of the seventh AND 61 element is connected to the third input of the second ANDI-OR-NOT element 47 and the second input of the first AND-NOT element 48. Second the input of the seventh AND element 61 is connected to the eleventh output of the BOP, with the first input of the first AND-NOT element 48 and connected to the direct output of the first trigger 67. The inverse output of the trigger 67 is connected to the third input of the eighth AND element 62. Installation input zero of the first trigger 67 is connected to the output of the first element "2 AND-OR-NOT" 46, fourth the first input of which is connected through the first element "NOT" 63 to the counting input of the first counter 43 pulses and is connected to the output of the element "2-OR-NOT" 47. The first and second inputs of the element "2-OR-NOT" 47 are connected to the input zero the third counter 45 pulses and connected to the fourth output of the decoder 42. The inputs of the decoder 42 are connected to the outputs of the third counter 45 pulses. The first, second and third outputs of the decoder 42 are connected to the second inputs of the first, second and third elements "And" 55.56, and 57, respectively. The first inputs of the AND elements 55.56 and 57 are interconnected and connected to the input of the second AND-NOT element 49.

 In block 8 of the autonomous control, the zero setting inputs 2N + 1 of the buffer storage devices 119.1.121 are combined, connected to the zero setting inputs of the pulse counter 103, with the zero setting inputs of the main and additional reverse pulse counters 122.1.124, with the first additional output of the autonomous control unit 8 and connected to the inverse output of the reset pulse generator 127, connected by its input to the power terminal "U". The control inputs of the buffer storage devices 119.1.121 are connected to the corresponding outputs of the first decoder 116. The same information inputs of the buffer storage devices 119.1.121 are combined and connected to the corresponding outputs of the block of AND-OR elements 108. Inputs of address recalculation for each i-th pair of the first 2N buffer memory devices 119.1.120.N are interconnected and connected to the overflow output "P" _ and to the overwrite input of the i-th additional counter 123.J pulses, with the exception of the (N + 1) -th additional counter 124 pulses. The outputs of the odd and even buffer memory 119.1.121 are connected to the same information inputs of the main and additional reverse counters 122.1.124 pulses, respectively. The counting inputs of the reversible counters 122.1.102.N pulses are interconnected and connected to the output of the controlled frequency divider 109. The output of each i-th main reversing counter 122.J (where i 1,2,3, N) of the pulses is connected to the counting input of the corresponding N-th additional reverse counter 123.J (where i 1,2,3, N) pulses. The output of the Nth additional reverse counter 123.N pulses is connected to the counting input of the (N + 1) th additional counter 124 pulses. The code rewrite input of the (N + 1) -th additional pulse counter 124 is connected to the address translation input of the (2N + 1) -th buffer memory 121 and connected to the third output of the control panel 128. Overflow output "P" _ (N-1) -th additional reverse pulse counter 124 is connected to the fifth input of the element "3-OR-NOT" 104. Overflow output "P" _ of each i-th main reverse counter 122.J of pulses is connected to the input of resetting (rewriting) the code of the same pulse counter and with the second input of the i-th (125.J, where i 1,2, N) and the first N elements "I-N "125.1.125.N. The output of the parallel code of each i-th (i ≠ N + 1) additional reverse counter 123.J pulses, together with the outputs of the parallel code of the (N + 1) -th additional reverse counter 124 pulses, are N information outputs of the autonomous control unit 8. The first N control the outputs of the autonomous control unit 8 are connected to the outputs of the first N elements AND-NOT 125.1.125.N. The first inputs of the AND-NOT elements 125.1.125.N are connected to the corresponding control inputs 24.1.24.N of the autonomous control unit 8. The third inputs are connected to the outputs of the bits of the fourth register 113. The fourth inputs of the first N elements of the AND-NOT 125.1. 125.N are interconnected, connected to the sixth output of the autonomous control unit 8 and connected to the eighth output of the second decoder 117. The first, second, third, fourth and seventh outputs of the second decoder 117 are connected respectively to the first, second, third, fourth and fifth synchronizing outputs b Loka 8 autonomous control. The first and second N control outputs 10.1.10.N of the autonomous control unit 8 are connected respectively to the outputs of the first and second N elements "AND NOT" 126.1.126.N. The first inputs of the second N elements AND-NOT 126.1-126.N connected to the outputs of the same name of the fifth register 114. The third inputs of the elements AND-NOT 126.1. 126. N are combined and through the first input of the OR element 107 are connected to the sixth output of the control panel 128. The third 2N control (paraphase) outputs 11.1.11.N and 12.1.12.N of the autonomous control unit 8 are connected to the corresponding paraphase outputs of the sixth register 115. The information inputs of the same name in six registers 110, 111, 112, 113, 114 and 115 are interconnected and connected to the corresponding outputs of the block of AND-OR elements 108.

 The control inputs of each of the six registers 110.115 through the elements AND-OR of the block of elements AND-OR 108 are connected to the corresponding outputs of the decoder 180 of the control panel 128.

 The outputs of the first and second registers 110 and 111 are connected to the installation inputs of a controlled frequency divider 109, the counting input of which is connected to the output of the quartz oscillator 102, to which the counting input of the pulse counter 103 is connected. By its outputs, the pulse counter 103 is connected to the inputs of the second decoder 117.

 The zero-setting input of the controlled frequency divider 109 is connected to the first input of the control panel 128 and connected to the output of the trigger 118. The input of the unit setting of the trigger 118 is connected to the first output of the control panel 128. The zero-setting input of the trigger 118 is connected to the second input of the And element 105 and connected to the output of the element "3I-OR-NOT" 104, the first and second inputs of which are connected to the direct output of the shaper 127 of the reset pulses. The third and fourth inputs of the element "3-OR-NE" 104 is connected to the output of the first element "OR" 106. The sixth input of the element "3-OR-NOT" 104 is connected to the second output of the control panel 128. The fourth and fifth outputs of the control panel 128 are connected respectively, with the first and second control inputs of the block of AND-OR elements 108. An additional output of the block of AND-OR elements 108 is connected to the first input of the first OR element 106. The second input of the first OR element 106 is connected to the additional input 24 unit 8 autonomous control. The input bus 1.21, 22, 23 of the autonomous control unit 8 is connected to the first inputs of the OR elements of the AND-OR unit 108 and to the second inputs of the control panel 128 and the second OR element 107. The second inputs of the AND- unit 108 OR "connected to the output bus of the control panel 128. In this case, the output of the element" AND "105 is an additional output" Set 0 "of the unit 8 of the autonomous control.

 In the remote control 128, the inputs of twenty-two buttons 129.150 are interconnected and connected to the power terminal. The outputs of the buttons 129.150 are connected to the inputs of the formers 151.172, respectively. The outputs of the first eight pulse shapers 151.158 are connected to the first to eighth bit inputs of the register 179.

 The control input of the register 179 is connected to the twenty-sixth input of the light indication unit 181 and is connected to the output of the ninth pulse shaper 159. The first to eighth outputs of the register 179 are connected to the same outputs of the remote control 128.

 The ninth to fourteenth inputs of the light indication unit 181 are connected to the outputs 9.14 of the control panel 128 of the same name, which are an address bus, and are connected respectively to the first to sixth outputs of the decoder 180. The inputs of the decoder 180 are connected to the outputs of the tenth pulse generator 160 through the pulse counter 173.

 The fifteenth to twentieth inputs of the light indication unit 181 are connected to the outputs 15.20 of the control panel 128 of the same name, which together with its twenty-first output constitute a control bus, and are connected respectively to the outputs of the eleventh to sixteenth pulse shapers 161-164. The twenty-first input of the light indication unit 181 is connected to the output of the control panel 128 of the same name and is connected to the direct output of the first trigger 174. The counting input of the first trigger 174 is connected to the output of the seventeenth pulse shaper 167.

 The twenty-second input of the light indication unit 181 is connected to the output of the eighteenth pulse shaper 168 and is connected to the first additional output of the control panel 128. The second additional output of the control panel 128 is connected to the twenty-third input of the light indication unit 181 and is connected to the direct output of the second trigger 175. The counting input of the trigger 175 is connected to the output of the nineteenth pulse shaper 169.

 The third additional output of the control panel is connected to the twenty-fourth input of the light indication unit 181 and is connected to the direct output of the third trigger 176. The counting input of the trigger 176 is connected to the output of the twentieth pulse generator 170.

 The fourth additional output of the control panel 128 is connected to the twenty-fifth input of the light indication unit 181 and is connected to the direct output of the fourth trigger 177. The unit setup input of the trigger 177 is connected to the output of the twenty-first driver 171. The zero-setting input of the trigger 177 is connected to the output of the OR element 178 the first input of which is connected to the output of the twenty-second pulse shaper 172. The inverse output of the fourth trigger 177 is connected to the fifth additional output of the remote control 128.

 The sixth additional output of the remote control 128 is connected to the input of the fourteenth pulse shaper 164. The twenty-seventh input of the light indication unit 181 is the first input of the control panel 128, the second input of which is connected to the second input of the OR element 178.

 In the buffer memory 119-121, the outputs of the first and second single vibrators 183 and 184 are connected to the control inputs V of “read” and W “write” of the memory unit 188, the outputs of which are the outputs of the buffer memory.

 The input of the first one-shot 183 is connected to the second input of the OR element 182 and is the control input "read" of the buffer memory. The third input of the element "OR" 182 is connected to the first input of the element "AND" 186 and is the control input "record" of the buffer storage device. The address inputs of the memory unit 188 are connected to the outputs of the pulse counter 187.

 The zero setting input of the pulse counter 187 is the zero setting input of the buffer memory. The counting input of the pulse counter 187 is connected to the output of the AND-NOT element 185. The first input of the AND-NOT element 185 is connected to the second input of the AND element 186 and is the first control input of the buffer memory. The second input of the AND-NOT element 185 is connected to the output of the OR element 182. The third input of the AND-NOT element 185 is the second control input of the buffer storage device, which together with the control inputs “read”, “write” and the data bus block 188 memory constitutes a control bus and data buffer memory device.

 In the interface 9, the inputs of the first decoder 190 and the transceivers 189 are connected to the common bus, to which the inputs and outputs of the output and input registers 192 and 194 are connected with the transmitters 196 and receivers 197 respectively, the inputs of the command register 193 with the second decoder 191 and 195 status register outputs. The first, second, third and fourth outputs of the first decoder 190 are connected to the address inputs of the data output register 192, command register 193, input register 194 and status register 195, respectively.

 The outputs of the data transmitter 196 of the output register 192 and the outputs of the second decoder 191 are connected to the output bus of the interface 9. The input bus of the interface 9 is connected to the inputs of the receiver 197 of the input register 194 and the inputs of the status register 195. The outputs of the output register 192 are used as the data bus of the autonomous control unit 8 and are connected via transmitters 196 to the first eight outputs 1.8 of the interface 9. The next six outputs (9.14) of the interface 9 are connected to the six outputs (1.6) of the second decoder 191 and are used as the bus addresses of the registers 110.115 of the unit 8 of the autonomous control. The remaining seven outputs 7.13 of the second decoder 191 and the output 22 of the strobe pulse of the data output register 192 are connected to the last eight outputs 14.22 of the interface 9 and are used as the control bus of the autonomous control unit 8. Moreover, the output 22 of the interface 9 is connected to the output of the register 192 through one of the transmitters 196.

 The first input of the interface 9 through one of the receivers is connected to the input of the strobe pulse of the input register 194. The second and third inputs of the interface 9 are connected respectively to the first and second inputs of the status register 195 and are used for their intended purpose, like the other inputs of the input register 194 connected to the inputs 4.11 of the interface 9 through the receiver 197.

 The operation of the system is illustrated by the stress diagrams shown in Fig.12, and is as follows.

 As already noted, the inventive system contains analogue channels for measuring physical quantities of the material and energy groups (for example, substance volume, flow rate, viscosity, concentration, dielectric constant, power consumption of an object, current, voltage, radiation energy, etc.) as well as discrete channels, which are channels for transmitting information about the physical quantities of an information group (amplitude-frequency spectrum, correlation function, sum or difference of signals, integral value tions signal, etc.). In the latter case, the outputs of digital spectrum analyzers, correlometers, integrators, and other devices of the information group are connected to discrete channels. If necessary, discrete channels can be used to connect exemplary measuring instruments (with digital output).

Each channel of the system allows you to connect from one to m sensors (Fig. 2), from one to R _p digital devices, from one to R _k analog devices and up to R _s + 1 converters or devices with a frequency output (Fig. 3).

 Suppose that the sensors 25.1-25.m of the physical quantities of analog channels 1 are connected to the object under study, and the outputs of additional devices used in the study of the object are connected to the corresponding inputs of discrete channels 2.

 The system provides two operating modes: autonomous mode (AR) for recording physical processes and quantities and automatic control (AU) for registration and measurement processes.

 In the autonomous (manual) control mode, instead of a computer 12, a magnetic tape drive 11 can be connected, for example, of the type EC.004.09, or any other cassette recorder interfaced with a common bus 10.

 In autonomous control mode, the system operates as follows.

 After the supply voltage is turned on, a voltage appears on the terminal “U” of the autonomous control unit 8 (BAU), which triggers the reset pulse generator 127. The output pulse from the inverse output of the driver 127 is fed to the zero-setting inputs of the pulse counters 187 of buffer memory devices (BZU) 119.1.119.N, 120.1.120.N, 121, and of the reverse pulse counters (RSI) 122.1.122.N, 123.1.123 .N and 124, as well as to the input of the zero setting of the pulse counter 103 of the block 8 of the autonomous control.

 At the same time, the reset pulse from the inverted output of the driver 127 is supplied to the first input of the And element 105. The reset pulse from the output of the And element 105 through the thirteenth output of the autonomous control unit 8 is fed to the second inputs of the analog and discrete channels 1 and 2 (Fig. 2, 3) and twenty-fifth inputs of blocks 3 and 4 of RAM (figure 4), setting their counters and triggers to the initial zero state.

 At the same time, after turning on the power from the direct output of the driver 127, the reset pulse through the 3I-OR-NOT 104 element is supplied to the second input of the And element 105 and to the zero-setting input of trigger 118. The latter provides control over the operation of the frequency divider 109. Upon receipt of a control pulse at the input of the zero setting of the trigger 118, the controlled frequency divider is reset. There will be no clock pulses at its output. When a pulse is applied to the input of the installation of the trigger unit 118, a signal is generated allowing the operation of the controlled frequency divider 109.

 It should be noted that the installation of the trigger unit 118 is carried out from the control panel 128. When you press the "Start" button 146 at the output of the shaper 168 there will be a pulse that is transmitted through the first output of the control panel 128 to the input of the installation of the trigger unit 118. Using the control panel 128 in trigger trigger 118 is not set. But, by pressing the “CD” button 147 [cyclic (time-finite) or long-term (almost infinite) system operation mode], a pulse arrives at the output of the former 169, which arrives at the counting input of the second trigger 175, setting it to zero or one. The output signal of the trigger 175 is supplied through the second output of the control panel 128 to the sixth input of the “3I-OR-NOT” element 104, thereby allowing or prohibiting the passage of the pulse from the output “P" _ of the reverse pulse counter 124 through the element "3I-OR-NOT" 104 to the trigger zero input 118.

 After setting the controlled frequency divider 109 to zero, there will be no signal at its output.

 The absence of an output signal at the output of a controlled frequency divider (UDF) 109 will result in the absence of a sampling process of the output signals of the sensors 25.1.25.m.

After turning on the power of the system, the quartz generator 102 of the autonomous control unit 8 starts working (Fig. 5), generating pulses with a frequency f ₀₁ 1 MHz.

 The counter 103 with a conversion factor equal to ten, immediately after resetting it to zero, recalculates the output pulses of the generator 102. Using the decoder 117 connected to the outputs of the counter 103, the states of the latter are decoded and synchronization pulses are generated. The latter synchronize the operation of analog storage devices (AZU) 27, 28.1.28.m, 29.1.29.m and analog-to-digital converters 24 analog channels 1; regeneration of memory blocks (BP) 76.99, synchronization of the process of recording information in blocks 3 and 4 of the system’s RAM and the end of the measurement process (recording information in the BOP).

 After setting the functional blocks of the system to its initial state, the operator presses the button 149 mode selection "RU / AU" (manual or automatic control) of the control panel 128 (Fig.6). The signal generated by block 171 puts the trigger 177 in the state "1" and "0" at its direct and inverse outputs, and, consequently, at the fourth and fifth outputs of the control panel 128 (Fig. 5). These signals are input to the AND inputs of the AND-OR block 108. The logical zero signal from the fifth control panel 128 prohibits the passage of signals to the output of the AND-OR block 108 with the input 1-21 of the autonomous control unit 8 (or first inputs of block 108). The signal of the logical unit from the fourth output of the control panel 128 allows only signals from the outputs 1-21 of the control panel 128 to pass to the outputs of the block of AND-OR elements 108. It should be noted that any command given by the buttons 129-150 of the control panel 128 displayed using the light indication unit 181.

 After setting the manual control (RU) mode by repeatedly (up to 6 times) pressing the register address setting button 138 (“AP”) 138 (FIG. 6), the pulse counter 173 is brought into a state in which the light indication unit 181 indicates, for example, the address of the first register 110 ("RF1"). Using the buttons 129-136, the 8th bit code of the least significant bits of the controlled frequency divider 109 (FIG. 5) is dialed, which is first entered into the register 179 of the control panel 128. The status of the bits of the register 179 is monitored using the light indication unit 181. By pressing the data input button 137 (“VD”), the data is transferred to the register 110 from the register 179. The subsequent single press of the “AP” button 138 provides a signal at the second output of the address decoder 180, which allows data to be written to the second register 111 of the autonomous control unit 8. Using the buttons 129-136, an 8-bit high-order code of the high-order bits of the controlled frequency divider 109 is selected. By pressing the 137 "VD" button, the data of register 179 is entered into register 111.

 Thus, the installation of a 16-bit value of the conversion factor of the controlled frequency divider 109. Permission to recalculate pulses using UDC 109 is issued after writing data to the other four registers 112, 113, 114, 115 of the autonomous control unit 8 (Fig. 5) by pressing 146 start buttons. As a result, the output signal of the driver 168, connected to the button 146, produces a logic zero signal. The latter through the first output of the control panel 128 will go to the installation input of the trigger unit 118 of the unit 8 of the autonomous control. This signal will translate the trigger 118 into one and thereby allow the passage of the counting pulses from the output of the generator 102 through the controlled frequency divider 109. It prints the appearance of the signal at the second output of the address decoder 180, which allows data to be written to the second register 111 of the autonomous control unit 8. Using the buttons 129-136, an 8-bit high-order code of the controlled bits of the frequency divider 109 is set. By pressing the 137 "VD" button, the data of register 179 is entered into the register 111. Thus, the 16-bit value of the conversion factor of the controlled frequency divider 109 is set. Permission to recount pulses using UDC 109 is issued after writing data to the other four registers 112, 113, 114, 115 of the autonomous control unit 8 (Fig. 5) by pressing the "Start" button 146. As a result, the output signal of the driver 168, connected to the button 146, produces a logic zero signal. The latter through the first output of the control panel 128 will go to the installation input of the trigger unit 118 of the unit 8 of the autonomous control. This signal will translate the trigger 118 into one and thereby allow the passage of the counting pulses from the output of the generator 102 through a controlled frequency divider 109.

Then the operator sets the set values of the sampling or retrieval frequencies for each channel. The sampling frequency is selected in accordance with the experimental conditions and the frequency range of the investigated physical processes. It should be noted that at the information outputs of each channel, data appears with a repetition rate f ₀₂ 100 kHz equal to the synchronization frequency. In order to exclude information redundancy and memory overflow of the BOP system, it is determined in advance how many values of the amplitudes of the samples and on which channels should be recorded in the BOP. Moreover, for the registration of transient processes, a larger amount of data is needed than when registering steady-state processes in the studied object.

To ensure the progress of the experiment with different sampling and retrieval frequencies, 2N + 1 BZU 119.1-119 was introduced into the autonomous control unit 8. N, 120.1-120. N, 121, which contains data on the value of sampling frequencies f _gi , on the number N _{bi of} samples with a given frequency and on the number of cycles N _c with a given research program (i.e., with given f _gi and N _bi ). The choice of this or that BZU is carried out by the above method by writing to the register 112 the address of the BZU. Using the first decoder 116, the input code is decrypted and data on the experiment are recorded in the corresponding BZU. Moreover, in the first N BZU 119.1-119.N the values of sampling frequencies for each channel are entered, in the second N BZU 120.1-120.N data on the number of samples or data taken on the same channel are entered, and in the BZU 121 data on the number of registration cycles are entered or measurements according to a given program. It should be noted that the capacity of each CCD is selected equal to 128 bits. Those. sixteen 8-bit data on the values of the frequencies, the number of samples and the number of cycles can be recorded in the memory of the CCD. Almost in the memory of the first N CCD, 8-bit data codes are recorded, and in the second CCD 7-bit data codes, since 8-bit main and 7-bit codes (except for the 5-bit reversible counter 124) are used, respectively reversible pulse counters 122.1.122.N and 123.1.123.N, connected by their preset inputs to the outputs of the corresponding BZU (figure 5).

Indeed, for the statistical processing of data on the nature of random processes, it suffices to have 128 sample values and 32 cycles (series) of experiments of the same type. Although the values of the frequencies f ₀₂ and f _gi can vary over a very wide range from 2 to 2 ¹⁶ for f ₀₂ and from 2 ¹ to 2 ⁸ for f _gi .

After writing data to all the CCD, press the "Start" button 146. As a result, pulses with a repetition rate f ₀₂ f ₀₁ / K _UDC , where K _UDC 2 ¹ .2 ^16, will begin to flow from the output of UDC 109 to the subtractive inputs of the main RSI.

At the “P” _ outputs of the RSI overflow, a periodic sequence of pulses with frequencies f _gi f _oi / K _{gi is} automatically generated _, where K _{gi are the} set values of the RSI conversion factors.

 The overflow signal from the output "P" _ of the main RSI 122.1.122.N is fed to the input of rewriting the RSI preset code. In additional N RSI 123.1.123.N, an overflow signal from the output "P" _ is supplied to the inputs of the address code conversion of the memory block 188 of the BZU.

 The overflow signal from the output "P" _ N + of the 1st additional reverse pulse counter 124 is supplied to the fifth input of the 3I-OR-NOT 104 element. If there is an enable signal at the sixth input of the 3I-OR-NOT element 104 trigger 118 translates into a state of zero at its direct output. The status of the trigger 118 is indicated by the light indication unit 181.

 The enable signal is generated, as already noted, by pressing the “CD” button 147 and setting the trigger 175 to the desired state. Moreover, the cyclic mode corresponds to the installation of the trigger 175 in the state unit at its output. The end of the measurement process in the second mode is determined by the decision of the operator or the moment in time by the receipt of a command from the object to end the experiment, for example, by turning on the button 14 "Stop."

The presence of the enable signal at the output of the trigger 175, and, consequently, at the second output of the control panel 128 provides the passage of the overflow signal from the output "P" _ RCI 124 to the input of the zero setting of the trigger 118. As a result, the state of the trigger 118 will change to the opposite, prohibiting operation UDCH 109. The registration process and measurement, consisting of n _u cycles to be completed. This process is repeated by pressing the “Start” button 146 again.

During operation cycles N _n system output data channels 1 and 2 with 8.1-8.N outputs applied to the inputs 12.1 of the respective blocks 3 and 4 of random access memory (DRAM) (Figure 1).

 To record the received data in the BOP using the control panel 128, the corresponding register 113 is selected, in which the address code of the required BOP is entered. The outputs of the register 113 are connected to the corresponding third inputs of the AND-NOT elements 125.1-125.N. Depending on the status of the bits of the register 113, the outputs of the AND-NOT 125.1-125.N elements will receive signals allowing the data from the channel outputs to be written to the corresponding BOP. These signals are formed by the coincidence of four different signals: signals of readiness for information from the digital outputs of the channels (fed to the inputs 24.1-24.N of block 8), the output signals of the main RSI of block 8, the clock signal from the eighth output of the decoder 117 and enable signals from the outputs of the register bits 113 unit 8 autonomous control (figure 5).

 Reading information from the BOP is carried out by the command generated in block 8 of the autonomous control. To do this, in the bits of the register 114 of the BOP address in a known manner, the signal corresponding to the selected BOP number is entered.

 From the outputs of the bits of the register 114, the signal is supplied to the first inputs of the second N elements "And" 126.1-126.N, allowing or prohibiting the passage of pulses through them from the outputs of the second element "OR" 107 and the second decoder 117. The inputs of the element "OR" 107 receive pulses from the computer 12 or from the control panel 128. In the latter case, they are formed using the shaper 164 by pressing the button "142" reading "RAM". The latter is connected to the input of the shaper 164. Like the rest, this command is also displayed using the light indication unit 182 of the control panel 128.

 The manual system control algorithm in general can be represented in the form of a block diagram shown in Fig. 8 and reflecting the totality and sequence of commands executed manually by the operator.

 Let us consider in detail the operation of one of the BOP in the modes of writing and reading information (data).

 A distinctive feature of the BOP is the synchronization of its pulses of the quartz oscillator 102, distributed in time and space using the counter 103 and the decoder 117 (figure 5). To control the operation of the BOP, pulses of the third, seventh and eighth outputs of the decoder 117 are used, the distribution diagram of the output pulses of which is shown in Fig.9.

 In BOP, memory blocks 76.99 are used, which are operational dynamic storage devices made, for example, on the K565RUZ IC. The memory block address code 76.99 is generated using a fourteen-digit pulse counter 43.

 Contactless (seven bits in one cycle), the address codes are transmitted to the inputs of the same name in memory blocks 76.99 through the “3И-OR-NOT” 69.75 elements and are accompanied by clock pulses arriving at the second and fourth inputs of the “3И-OR-NOT" 69.75. The signals from the seventh and eighth outputs of the decoder 117 are used as synchronization pulses. These signals are transmitted respectively through the fifth and sixth outputs of the autonomous control unit, the twenty-ninth and thirtieth inputs of the BOP, to the first input of the OR-NOT element 51 and to the second and fourth inputs of the seven elements "3 AND-OR-NOT" 69.75. The first inputs of each of the seven elements of the “3-OR-NOT” 69.75 are connected to the corresponding first seven outputs of the bits of the counter 43 of the address of the memory blocks 76. 99. The third inputs of each of the seven elements of the “3-OR-NOT” 69.75 are connected respectively to the second seven outputs counter 43 of the address code of the memory blocks 76.99. In addition, the sixth inputs of the seven elements of “3I-OR-NOT” 69.75 are supplied with the address code of the line of memory blocks 76.99 from the bits of the second (seven-bit) counter 44 pulses.

The fifth (combined) inputs of the 3I-OR-NOT elements 69.75 from the third output of the decoder 117 through the third output of the autonomous control unit 8, the twenty-eighth input of the BOP and the second one-shot 54 receive pulses with a frequency f _p 100 kHz, specifying the cycle time regeneration. The seven-shot line address code signals generated using the “3I-OR-NOT” 69.75 elements are fed to the addresses of the memory blocks 76.99 combined with the same name. In the second measure, the column address code is entered from the same outputs of the elements "3-OR-NOT" 69.75. For the complete regeneration of the information stored in the BOP, 128 cycles are necessary (accesses to all 128 addresses of rows of memory blocks 76.99). At the selected regeneration frequency f _p 100 kHz, the total regeneration time of memory blocks 76.99 will be t _p 2 ⁷ / f _p 2 ⁷ ˙1˙10 ^-6 2 ⁷ ˙10 ^-3 s.

 In the mode of recording information in memory blocks 76.99, the data is received in the form of 24-bit layers at 1-24 inputs of the BOP. The first 12 bits of this word are data from the outputs of the analog-to-digital converter 24 analog channels 1 or from the outputs of the switch 30 digital signals of discrete channels 2. These data come from 8.1-8.N channel outputs to 1-12 BOP inputs. The second 12 bits comprise: 7 bits the number of samples at a given sampling frequency, 5 bits the number of corresponding cycles. For each i-th BOP, these word bits are formed in the autonomous control unit 12 and are the outputs of the additional i-th reverse pulse counters 123.J and N + of the 1st reverse pulse counter 124, connected through the 8.J and 9.J outputs of the block 8 to 13-19 and 20-24 inputs of the BOP, respectively (see figure 4).

 The inputs 1.24 of the RAM block are connected to the inputs "D1" of the memory blocks 76.99, respectively.

и

(

вход выбора адреса строки,

вход выбора адреса столбца).The choice of any of the 16384 cells of memory blocks 76.99 is provided by a 14-bit address code arriving in two clock cycles, accompanied by gate signals to the inputs

and

(

line address selection input,

column address selection input).

блоков памяти 76.99 поступает сигнал с выхода элемента "ИЛИ-НЕ" 51, первый и второй входы которого через двадцать девятый и тридцать первый входы БОП, пятый и шестой выходы блока 8 автономного управления соединены с седьмым и третьим выходом дешифратора 117 (фиг.5).To the entrances

of memory blocks 76.99, a signal is received from the output of the OR-NOT element 51, the first and second inputs of which through the twenty-ninth and thirty-first inputs of the BOP, the fifth and sixth outputs of the autonomous control unit 8 are connected to the seventh and third output of the decoder 117 (Fig. 5) .

блоков памяти 76.99 поступают в режиме записи сигналы выбора адреса столбца с выходов элементов "И" 58, 59 и 60. Вторые входы элементов "И" 58, 59 и 60 объединены и подключены соответственно к выходу элемента "И-НЕ" 50. Последний обеспечивает разрешение управления режимом записи данных в блоке памяти 76.99 по сигналам с выходов второго триггера 68 и пятого элемента "И" 62. Выходы блоков 68 и 62 соединены соответственно с первым и вторым входами элемента "И" 50 (фиг.4). Необходимо отметить, что режим записи информации в блоки памяти 76.99 (фиг.4) устанавливается путем подачи логического нуля на вход установки единицы триггера 68 и перевода последнего в единицу на его прямом выходе. При этом сигналом логического нуля с инверсного выхода триггера 68, поступающего на третий вход элемента "И" 61, запрещается выполнение операции считывания данных с БОП. Это позволяет исключить одновременное выполнение операции "запись" и "чтение" информации в БОП.For every eight entries

of memory blocks 76.99, in the recording mode, signals for selecting the column address from the outputs of the "And" elements 58, 59 and 60 are received. The second inputs of the "And" elements 58, 59 and 60 are combined and connected respectively to the output of the "AND-NOT" element 50. The latter provides permission to control the data recording mode in the memory block 76.99 by the signals from the outputs of the second trigger 68 and the fifth element "And" 62. The outputs of the blocks 68 and 62 are connected respectively to the first and second inputs of the element "And" 50 (figure 4). It should be noted that the mode of recording information in memory blocks 76.99 (Fig. 4) is established by applying a logical zero to the input of the installation of the trigger unit 68 and translating the latter into a unit at its direct output. In this case, the signal of logical zero from the inverse output of the trigger 68, arriving at the third input of the element "And" 61, it is prohibited to perform the operation of reading data from the BOP. This allows us to exclude the simultaneous execution of the operation "write" and "read" information in the BOP.

,

и

указанных блоков памяти с выходов элементов "ИЛИ-НЕ" 51, "И" 58, 59, 60 и элементов "И" 55, 56 и 57 соответственно (фиг.4).Management of the recording of information in memory blocks 76.99 is carried out by signals for selecting row addresses, writing / reading, and column addresses arriving at the inputs respectively

,

and

these memory blocks from the outputs of the elements "OR NOT" 51, "AND" 58, 59, 60 and the elements "AND" 55, 56 and 57, respectively (figure 4).

 In the read mode, trigger 67 is transferred to the state of the logical unit. As a result, the operation of writing data to the BOP is prohibited. This is achieved by applying a logical zero signal from the inverse output of the trigger 67 and the third input of the element "And" 62.

этих блоков с выходов элементов "И-НЕ" 55, 56 и 57.Signals for selecting the address of the rows of memory blocks 76.83, 84.91, 92.99 are fed to the inputs

of these blocks from the outputs of the AND-NOT elements 55, 56 and 57.

 In this case, from the outputs of the elements “3I-OR-NOT” 69.75, the address code of the line is sent to the address inputs of the memory blocks 69.75. The column address code is entered into the memory block 69.75 on the second of two clock cycles.

 The process of reading a 24-bit word occurs byte-by-bit.

 Of the total four measures, three are used to read a 24-bit word and one (fourth) measure to recalculate the address of the memory blocks 69.75.

 These clocks are formed by applying a signal from the sixth output of the autonomous control unit 8 through the thirty-third input of the BOP and the elements "AND" 61 and "NAND" 48 to the counting input of the pulse counter 45, the inputs of the crystal selection "VK" bus shapers 100 and 101 and input of the element "NOT" 66.

 Using the pulse counter 45 and the decoder 42 is the formation of clock pulses. From the first three outputs of the decoder 42, clock pulses are supplied to the second inputs of the elements "And" 55, 56 and 57, respectively. At the first inputs of the AND elements 55, 56, and 57, the output signal of the AND-NOT element 49 is received. It should be noted that the AND elements 55, 56, and 57 perform the function of OR when logical zeros arrive at their inputs.

 The signal from the fourth output of the decoder 42 sets the pulse counter 45 to zero and recounts, in the reading mode, the addresses of the memory blocks 76. 99 by applying a pulse through the first and second inputs of the 2I-OR-NOT element 47 to the counting input of the pulse counter 43.

последних (фиг.4).The outputs of the elements "And" 55, 56 and 57 are formed of signals for recording information in the memory block 76.83, 84.91 and 92.99, respectively, which are received at the inputs

the latter (figure 4).

,

и

блоков памяти 76.83, 84.91, 92.99 с выходов элементов "ИЛИ-НЕ" 51, "И" 55, 56 и 57 и элементов "И" 58, 59 и 60 соответственно (фиг. 4). По первому такту на входы

,

и

блоков памяти 76.83 поступают в той же последовательности сигналы логического нуля. Наличие сигналов, соответствующих логической единицы на входах

блоков памяти 84.91 и 92. 99, обеспечивает установку их в третье состояние, соответствующее отключение выходных этих блоков памяти от выходной шины.Management of three clock cycles of information transfer is performed by signals for selecting row addresses, column addresses and a write-read signal received at the inputs

,

and

memory blocks 76.83, 84.91, 92.99 from the outputs of the elements "OR NOT" 51, "AND" 55, 56 and 57 and the elements "AND" 58, 59 and 60, respectively (Fig. 4). On the first measure of the inputs

,

and

memory blocks 76.83 received in the same sequence of logic zero signals. The presence of signals corresponding to a logical unit at the inputs

memory blocks 84.91 and 92. 99, provides for their installation in the third state, correspondingly disconnecting the output of these memory blocks from the output bus.

 According to the second and third clocks, the reading of information from the outputs of the memory blocks 84.91, 92.99, respectively, is carried out in a similar way. At the same time, the address code of the memory blocks 76.99 installed in the counter 43 pulses is not recounted. Recalculation of the address code is carried out by the signal from the fourth output of the decoder 42 (reading clock setter). Byte-wise output of information from the outputs of the bus drivers 100 and 101 is carried out by applying to their inputs "VK" the output signal of the element "NAND" 48 and is accompanied by a stob pulse from the output of the element "NOT" 66. This information is through the outputs 1-8 of the bus drivers 100 and 101 goes to inputs 4-11 of interface 9.

 From the outputs of the interface 9, the information goes to the drive 11 on a magnetic tape connected instead of a computer 12 in the mode of autonomous (manual) control of the system.

 Data signals from 1-8 outputs of blocks 3 and 4 of RAM are supplied to 4-11 inputs of interface 9. At its first input, a strobe pulse from the output of the first element "OR" 5 (Fig. 1). The inputs of this element are connected to the ninth outputs of all BOP, the signals of which are combined by "OR" and provide synchronization of information input through receivers 197, register 194, transceivers 189 and a common bus 10 to drive 11 on magnetic tape, in the case of a system without a computer 12, i.e. offline data logging.

 Consider the automatic control (AU) registration and measurement processes using a computer 12.

 The "AU" mode is set manually by pressing the button 159 on the control panel 128 or the corresponding button on the control panel of the computer 12. In the latter case, the control signal via the common bus 10, transceivers 189 of the interface 9, through one of the bits of the register 192 and the transmitter 196 ( Fig. 8) is supplied to the twenty-second output of the interface 9, and therefore to the second input of the control panel 128 connected to the second input of the OR element 178. The indicated signal puts the trigger 177 in a state of logical zero at its direct output. At the first input of the AND elements of the block of AND-OR 108 elements, an inhibitory signal will be received, and at the second input of the And elements, an enable signal from the fourth and fifth outputs of the control panel 128, respectively. As a result, the system will be controlled only by a command from a computer 12 in the given sequence.

 As can be seen from FIG. 8, the first inputs of the “OR” elements of the block of AND-OR elements 108 receive data from 1-8 outputs of the interface 9, addresses of the registers 110. 115 from 9-14 outputs of the interface 9 and the commands “read BZU”, “write BZU” , "reading RAM", "writing RAM", "STOP", "reading once / multiple." and a strobe-pulse of data tracking from 15-22 outputs of interface 9, respectively.

 In the automatic control mode of the registration processes, the system operates according to the same algorithm as with manual control (Fig. 10, 11). However, measuring and processing data in automatic control mode are significantly different from offline mode.

 The main feature of the automatic mode is the possibility of statistical processing of research results and selection of optimal modes of measurement and registration of physical processes and quantities from them. This allows you to effectively use the hardware and software of the system and increase the information content, reliability and reliability of research results.

du(t)/dt в заданных интервалах времени Δ ti Ti, где i 0,1,2,N; б) частоты f_ог основной гармоники или спектрального состава сигнала U(t); в) времени затухания Т_з переходных процессов; г) характеристических моментов времени t_o, t₁, t₂, t_i.For this, the transient U (t) is recorded (Fig. 12), measuring and processing at least three of its parameters: a) the speed of the process under study
v

du (t) / dt at predetermined time intervals Δ ti Ti, where i 0,1,2, N; b) frequency f _{og of the} fundamental harmonic or spectral composition of the signal U (t); C) the decay time T _s transients; g) characteristic times t _o , t ₁ , t ₂ , t _i .

 Then, depending on the frequency of the fundamental harmonic, the average sampling frequency of the process under study, the required number of samples, and the number of measurement cycles are set.

The sampling frequency is specified depending on the speed of the studied processes. The number of samples is set based on the amount of BOP memory. The time of the experiment is defined as
T _e KT _c , where T _{c is the} time of one cycle, which is 3-10 time intervals between the characteristics of the moment in time, K is the number of cycles at which the amplitude of the process decreases to a predetermined value of A _m.min .

After specifying the values of the sampling frequency, the number of samples and the number of measurement cycles, the transient is recorded again and its parameters are processed. Such an iterative procedure is repeated several times until the processing results of the same type are obtained, and consequently, the nominal values of the sampling frequencies, the number of samples and the number of cycles necessary for a reliable study of the object of study are obtained. It should be noted that structural redundancy and new connections between functional blocks have been introduced into the analog channels of measuring physical quantities, providing: correction of the additive and multiplicative components of the measurement error of each of the mentioned channels and their testing. In addition, two modes of sampling and measuring the amplitudes of the samples from the output signals of the sensors 25.1.25.m were implemented: a) simultaneous recording (with a frequency f ₀₃ f ₀₂ / m) of the instantaneous values of the amplitudes of the samples from the output signals of the sensors in the RAM 28.1.28. m, followed by sequentially reading and converting the recorded information into a code, and b) recording at the same time (with a frequency f ₀₂ 100 kHz) instantaneous values of the amplitudes of the samples from the output signals of the sensors in the RAM and synchronously converting them into code using the ADC 24.

Testing of analog channels is carried out as follows. When the switch position 22 of the analog signals corresponds to the arrival of the first (after reset to zero) pulse to the counting input of the counter 18, the output code N _xo ADC 24 of each of the analog channels is recorded in the BOP. This code is proportional to the amplitude of the sample from the output signal of the reference voltage source 15.

The value of N _o voltage V _o source 15 is known a priori with high accuracy. The voltage V _{o itself} is selected to be very small in value, i.e. V _o ΔV. The measurement result N _{xo of} this voltage is recorded in the computer memory 12 as the value N _xo K _oi SV _o , where K _{oi is} the transfer coefficient of the i-th channel, S is the ADC conversion slope. The values of N _xo and N _{o are} compared with each other. Based on the comparison result, existing corrections are made to the measurement results.

, (1) где N_1i, N_2i и N_3i результаты преобразования в код амплитуд выборок, записанных в АЗУ, из выходных сигналов источников 25 опорного напряжения, датчика 25.J и сумматора 26.J (где 1 ≅ J ≅ m) соответственно.To eliminate the systematic error of the channel, the processing of the values of the amplitudes of the samples is carried out using the second processor 13 according to the algorithm
N _xi = N _o

, (1) where N _1i , N _2i and N _{3i are the} results of conversion into the code of the amplitudes of the samples recorded in the RAM from the output signals of the voltage reference sources 25, the sensor 25.J and the adder 26.J (where 1 ≅ J ≅ m), respectively .

 Data processing by algorithm (1) is as follows. The trailing edge of the pulse coming from the output of the fourteenth category of the counter 43 of the memory address in read mode (i.e., when overwriting information from the outputs of blocks 3 and 4 of random access memory (Fig. 4) into the random access memory 12 or a magnetic tape drive 13) through the first element "2 AND-OR-NOT" 46 trigger 67 reading, is set to zero.

 From the direct output of the trigger 67, the signal enters through 11 the output of the blocks 3 and 4 of the RAM and the elements 6 (Fig. 1) to the inputs 2N of the interface 9 (or to the inputs 1N of the status register 195), Fig. 8. Register 195 generates a code characterizing the end of the corresponding channel. After the appearance of this code, the data of the selected channel is processed using a computer 12 according to an algorithm whose structural diagram is shown in Figs. 10, 11.

 We show that algorithm (1) ensures the exclusion of the additive and multiplicative components of the error with a linear characteristic of the channel transformation, i.e.

N _i K _i S _i V _i (1 + γ _i + Δ N _i ), (2) where Δ N _i is the additive component of the conversion error reduced to the output of the i-th channel;
K _i S _i Ui γ _i the multiplicative error component reduced to the output;
K _i the transfer coefficient of the i-th channel from the sensor to the ADC;
S _{i the} steepness of the conversion of the i-th ADC;
V _{xi is the} output signal of the i-th sensor (amplitude of the i-th sample).

When characterizing the transformation (2), we obtain
N _1i K _i S _i V _oi (1 + γ _i + Δ N _i ), (3)
N _2i K _i S _i V _1i (1 + γ _i + Δ N _i ), (4)
N _3i K _i S _i V _2i (1 + γ _i + Δ N _i ), (5) where V _{oi is the} amplitude of the sample from the output voltage of the source 15;
V _1i V _{xi the} amplitude of the i-th sample,
V _2i V _xi + V _{oi the} amplitude of the sample from the output signal of the i-th adder.

(6)
Из выражения (6) видно, что реализация алгоритма (1) обработки данных обеспечивает исключение систематической погрешности каждого i-го канала. Основные требования по стабильности и точности предъявляются к идентичности характеристик АЗУ 27-29.m. Неидентичность характеристик АЗУ приведет к неравенству их коэффициентов передачи и возникновению небольшой систематической погрешности, зависящей от степени идентичности характеристик. Эффект в этом случае достигается только за счет исключения погрешностей АЦП 34.We substitute the results of measurements (3) - (5) of the amplitudes of the samples into expression (1). Then

(6)
From the expression (6) it can be seen that the implementation of the data processing algorithm (1) ensures the elimination of the systematic error of each i-th channel. The basic requirements for stability and accuracy are presented to the identity of the characteristics of the AZU 27-29.m. The non-identical characteristics of the AZU will lead to an inequality of their transmission coefficients and the emergence of a small systematic error, depending on the degree of identity of the characteristics. The effect in this case is achieved only by eliminating the errors of the ADC 34.

A feature of the work of discrete channels (figure 3) is, as already noted above, the ability to enter measurement information from external additional standard and non-standard digital measuring instruments by connecting their outputs to the input registers 35.1-35.R _p .

By connecting exemplary measuring instruments to the inputs of discrete channels, it is possible to use them to correct the transmission coefficient of analog measuring channels. Using the counters 31.1-1.R _s and the multi-bit counter 32, it is possible to count a different number of heterogeneous events that took place in the object under study, as well as to convert the sequence of these events into parallel code. Discrete channels are also performed using comparators 40.1-40.R _k , the operation of comparing the equations of the output signals of sensors, converters, current or voltage sources located on the studied object and carrying information about the state of individual elements or nodes of the object in real time.

 The presence in the computer system 12 and interfaces 9 allows you to additionally solve the problems of averaging and smoothing research results, digital filtering of recorded signals according to known data processing algorithms.

 In contrast to the prototype, a multi-channel system for recording physical quantities is characterized by wide functionality and increased accuracy of measurements and registration.

 The expansion of functionality is achieved by introducing discrete channels into the system. As a result, it became possible to include additional external standard or non-standard digital measuring instruments, including exemplary ones. The introduction of discrete channels also provides the calculation of a different number of heterogeneous events taking place in the studied object, the conversion of the sequence of events into a parallel code, as well as the operations of comparing the output signal levels of sensors, transducers, current or voltage sources located on the studied object.

 Introduction to the system of blocks of random access memory, connected in a certain way with discrete and analog channels, with an interface and an autonomous control system, provides enhanced functionality by quickly memorizing the given arrays of samples of sensor output signals characterizing the physical processes in the studied object, taking into account different speeds the course of the studied processes, as well as due to the separation in time of the processes of taking and processing the values of the amplitudes of the samples, prog ammiruemogo entire volume distribution information received in memory units and computers.

 The introduction of the second processor 13 provides separation of the functions of controlling the operation of the functional blocks of the system and processing the received information. The introduction of the group of elements "NOT" and their relationships with the interface and with the blocks of RAM provides synchronization of the process of transferring information to computers. This increases the reliability of the information received and the readiness of the computer to its perception and processing.

 The introduction of an autonomous control unit expands the functionality of the system in terms of implementing an autonomous mode of operation without a computer, but with a tape drive, and a mode with automatic control of the experiment. The introduction of an autonomous control unit allows us to refine the program for optimal control of the sampling process, in particular, select the sampling frequency, set the required sample size, and form time intervals between samples in cycles and channels; control the commands given from the control panel; perform a system shutdown operation upon command from an object, from a control panel or from a computer.

 The introduction of significant distinguishing features into the measuring channels ensures the implementation of a test algorithm for correcting channel errors, i.e., it provides an increase in the accuracy of recording and measuring physical processes and quantities. In addition, they ensure the registration of fast-moving processes with different speeds and the introduction of corrections to the measurement result in the case of deviations of the transmission coefficients of the channels from the specified nominal values.

 Distinctive features entered into each buffer storage device allow manual and automatic control of the reading, writing and address translation modes. Distinctive features entered into the interface provide pairing through a common bus, random access memory blocks and an autonomous control unit with a computer, as well as automatic control of the system using a computer.

 Thus, the proposed set of functional blocks and their relationships provides the expansion of functionality and increase the accuracy of registration and measurement of physical processes and quantities using the proposed multichannel system.

Claims (8)

 1. MULTI-CHANNEL SYSTEM FOR REGISTRATION OF PHYSICAL QUANTITIES, containing analog measurement channels, the outputs of which are connected to the information inputs of the corresponding blocks of RAM of the first group, an OR element, an interface whose outputs are connected to the information inputs of the autonomous control unit, the first outputs of which are connected to the control inputs of the corresponding analog measurement channels, characterized in that discrete measurement channels are introduced into it, the second group of RAM blocks, element groups NOT, a computing unit, a magnetic tape memory unit and a stop button, the terminals of which are connected to a constant voltage source and a control input of an autonomous control unit, the second outputs of which are connected to the control inputs of the corresponding memory blocks of both groups, the information inputs of discrete measurement channels are inputs systems controlling the inputs of discrete measurement channels are connected to the corresponding first outputs of the autonomous control unit, outputs of discrete measurement channels they are connected to the information inputs of the corresponding RAM blocks of the second group, the information outputs of all the RAM blocks of both groups are connected to the information inputs of the interface, the first control outputs of all the RAM blocks of both groups are connected to the inputs of the OR element, the output of which is connected to the first control input of the interface, the second and the third control outputs of the blocks of RAM of both groups are connected to the inputs of the corresponding elements NOT, respectively, of the first and second groups, you the moves of which are connected respectively to the second and third control inputs of the interface, the inputs and outputs of which are combined into a common bus with the inputs and outputs of the computing unit and the memory unit on the magnetic tape.  2. The system according to claim 1, characterized in that each of the analog measurement channels contains two groups of m analogue storage devices, an analogue storage device, an analogue signal switch, an analog-to-digital converter, a pulse shaper, a light indication unit, m totalizers, a source reference voltage, inverter, element NOT, element 2 AND OR NOT and element OR NOT, one-shot, pulse counter and m sensors of physical quantities connected to the signal inputs of the same analog memory devices of the first groups, the outputs of which are connected to the corresponding information inputs of the analog signal switch, the output of which is connected to the input of the analog-to-digital converter, the synchronizing input of which is connected through the pulse shaper to the first control input of the analog channel, to the information outputs of which the outputs of the analog-to-digital converter are connected, the gate output the signal of the analog-to-digital converter is connected to the input of the light indication unit and is connected to the seventh channel output, counting the input of the pulse counter is connected to the output of the element NOT, the outputs of the pulse counter are connected to the control inputs of the analog signal switch, the high-order output of the pulse counter is additionally connected to the first input of the element 2 AND OR NOT and through a one-shot with the first input of the element OR NOT, the output of which is connected to the input zero pulse counter, the second input of the element OR NOT, the second, third and fourth inputs of the element 2 AND OR NOT and the input of the element are NOT the second, third, fourth, fifth and sixth control the input inputs of analog channels, the output of the 2and OR element is not connected to the combined clock inputs of all analog storage devices, the output of the reference voltage source is connected to the signal input of a single analog storage device and to the first inputs of the adders, the second inputs of which are connected to the outputs of the sensors of the same physical quantities, outputs adders are connected to the signal inputs of the same analog memory devices of the second group. 3. The system of claim 1, characterized in that each of the digital channel includes a monostable multivibrator, OR element, k _s + 2 pulse counters, k _f + 1 (wherein k _f k _s + k _p) formers, k _{to the} comparators , k _p + 1 registers and switches of digital signals, the inputs of which are connected respectively to the outputs of k _p + 1 registers, k _s pulse counters and a pair of outputs (k _s + 1) -th pulse counter, the control inputs of the digital signal switch are connected to the inputs of the same name and OR gate connected to the outputs (k _s + 2) -th pulse counter whose count input Port nen through (k _f + 1) -th control driver to a sixth discrete channel input, counting inputs k _s + 1 pulse counters are connected to the outputs of respective formers k _s, k _f formers outputs connected respectively to the control inputs of the registers _r k inputs (k _p + 1) of the register are connected to the outputs of k _{to the} comparators, the inputs for setting the zeros of k _s and (k _s + 2) of the pulse counters are interconnected and connected to the second control input of the discrete channel, the first, third, fourth and fifth control whose inputs are free, the outputs the digital signal commutator and the one-shot are respectively the information and synchronizing outputs of the discrete channel, the inputs of which are connected to the inputs k _to comparators, k _f formers, inputs of k _p registers and to the control input of the (k _p + 1) th register. 4. The system according to claim 1, characterized in that each block of RAM includes a decoder, three elements AND NOT, eight elements AND, four elements NOT, two triggers, two one-shot, two elements OR NOT, three pulse counters, two four-charged bus drivers, twenty-four memory blocks, two 2 AND OR NOT elements and seven 3 AND OR NOT elements, the first and third inputs of which are connected respectively to the first and second seven outputs of the bits of the pulse counter parallel code, the second inputs of 3 AND OR elements are not combined oh, with the first input of the first element OR NOT and connected to the twenty-ninth input of the RAM block, the fourth inputs of the 3 AND OR elements are not interconnected and connected to the thirteenth input of the RAM block, the fifth inputs of the 3 AND OR elements are not interconnected and connected to the output the second one-shot, the sixth inputs of each element 3 AND OR NOT connected by the corresponding, starting from the least significant bit, the outputs of the second pulse counter, the outputs of the elements 3 AND OR NOT connected to the interconnected address memory block inputs, three groups of inputs DI of which are connected respectively to inputs 1 12, 13 19, 20 24 blocks of random access memory, inputs

1 8, 9 16 and 17 24 memory blocks are interconnected, connected to the first inputs of the fourth, fifth and sixth elements And and connected to the outputs of the first, second and third elements And, respectively, the inputs

all memory blocks are combined and connected to the output of the first element OR NOT, the inputs

each of the eight memory blocks are interconnected and connected respectively to the outputs of the fourth, fifth and sixth AND elements, the second inputs of which are interconnected, connected to the fourth input of the second element 2 AND OR NOT and connected to the output of the third element AND NOT, outputs of the same name 1 8, 9 16 and 17 24 memory blocks are interconnected and connected in four to the inputs of the first and second bus drivers, the control inputs of which are connected to each other and connected to the power terminal, the synchronizing inputs of the VK are connected to the odes of the fourth element NOT, with the counting input of the third pulse counter and connected to the output of the first element AND NOT, the outputs of the first and second bus drivers are connected to the outputs 1 4, 5 8 of the RAM blocks, the ninth output of which is connected to the output of the fourth element NOT, twenty-fifth the input of the RAM block is connected to the input of the second element NOT and to the zero-setting input of the first pulse counter, the twenty-sixth input is connected to the third input of the first element 2 AND OR NOT, the twenty-seventh input through the first one-shot ator is connected to the first output of the second element And
NOT, the twenty-eighth input is connected to the input of the second one-shot and through the third element NOT to the counting input of the second pulse counter, the thirty-first input of the RAM block is connected to the second input of the first element OR NOT, the thirty-second and thirty-fourth inputs of the RAM block are connected respectively to the inputs unit settings of the first and second triggers, thirty-third and thirty-fifth inputs are connected respectively to the first inputs of the seventh and eighth elements And the output of the eighth element And is connected to the second the input of the third element AND NOT, the second input of the eighth element AND is connected to the tenth output of the RAM block, with the second input of the second element AND NOT, with the first input of the third element AND is NOT connected to the direct output of the second trigger, the zero setting input of which is connected to the output of the second element OR NOT, whose first input is connected to the output of the second element NOT, the second input of the second element OR NOT connected to the first and second inputs of the first element 2 AND OR NOT and connected to the highest bit of the first pulse counter, inverse output the second trigger is connected to the third input of the seventh AND element, the output of which is connected to the third input of the second element 2 AND OR NOT and the second input of the first element AND NOT, the second input of the seventh element And is connected to the eleventh output of the RAM block, with the first input of the second element AND NOT and connected to the direct output of the first trigger, the inverse output of which is connected to the third input of the eighth element AND, the zero setting input of the first trigger is connected to the output of the first element 2 AND OR NOT, the fourth input of which is connected through the first element is NOT with the counting input of the first pulse counter and is connected to the output of the second element 2 AND OR NOT, the first and second inputs of which are connected to the zero setting input of the third pulse counter and are connected to the fourth output of the decoder, the inputs of which are connected to the outputs of the third pulse counter, the first, the second and third outputs of the decoder are connected to the second inputs of the first, second and third elements AND, respectively, the first inputs of which are combined with each other and connected to the output of the second element AND NOT. 5. The system according to claim 1, characterized in that the autonomous control unit comprises a control panel, a quartz generator, a reset pulse shaper, an AND 3 element, an OR element block, two OR elements, an AND element, a controlled frequency divider, a trigger, six registers, two decoders, pulse counter, 2N elements AND NOT, N main and N + 1 additional reversible pulse counters and 2N + 1 buffer memory devices, the zero setting inputs of which are combined, connected to the zero setting input of the pulse counter, with the setting inputs and zeros of the main and additional reversible pulse counters, with the first input of the And element connected to the inverse output of the reset pulse shaper connected to the power terminal by its input, the control inputs of the buffer storage devices are connected to the corresponding outputs of the first decoder, the information inputs of the same name are combined and connected to the corresponding the main outputs of the block of elements AND OR, the inputs of the address translation of each i-th pair of the first 2N buffer storage devices are interconnected and sub are connected to the overflow output "P _- " and to the overwrite input of the i-th additional pulse counter, with the exception of the (N + 1) th, the outputs of the odd and even buffer memory devices are connected to the same information inputs of the main and additional reversible pulse counters, respectively the inputs of the main reverse pulse counters are interconnected and connected to the output of a controlled frequency divider, the output of each i-th main reverse pulse counter is connected to the counting input of the corresponding i- o additional reverse pulse counter, the output of the Nth additional reverse pulse counter is connected to the counting input of the (N + 1) -th additional pulse counter, the code rewrite input of which is connected to the address translation input of the (2N + 1) -th buffer memory and is connected to the third output of the control panel, the overflow output of the "P _- " (N + 1) -th additional reverse pulse counter is connected to the fifth input of element 3 AND OR - NOT, the overflow output "P _- " of each i-th main reverse pulse counter in is connected to the input of the code preset of the same pulse counter and to the second input of the first N elements AND NOT, the outputs of the parallel code of each i-th (i ≠ N + 1) additional reverse pulse counter along with the outputs of the parallel code of the (N + 1) -th additional reverse pulse counter are N information outputs of the autonomous control unit, the first N control outputs of which are connected to the outputs of the first N elements AND NOT, the first inputs of which are connected to the corresponding control inputs of the autonomous control unit The third inputs are connected to the outputs of the fourth register bits, the fourth inputs of the first N elements AND are NOT combined with the second inputs of the second N elements AND NOT, with the sixth output of the autonomous control unit and are connected to the eighth output of the second decoder, the first, second, third, fourth and the seventh outputs of which are connected respectively to the first, second, third, fourth and fifth synchronizing outputs of the autonomous control unit, the first and second N control outputs of which are connected respectively to the outputs of the first and W Of the first N elements AND NOT, the first inputs of the second N elements AND NOT connected to the same outputs of the fifth register bits, the third inputs are combined and through the first input of the second OR connected to the sixth output of the control panel, the third 2N control paraphase outputs of the autonomous control unit are connected to the corresponding paraphase the outputs of the sixth register, the same information inputs of all six registers are interconnected and connected to the corresponding main outputs of the block of elements AND OR, the control inputs of each about of six registers through elements AND OR block of elements AND OR are connected to the corresponding outputs of the decoder of the control panel, the outputs of the first and second registers are connected to the installation inputs of the controlled frequency divider, the counting input of which is connected to the output of the quartz generator, to which the counting input of the pulse counter is connected connected by its outputs to the input of the second decoder, the zero setting input of the controlled frequency divider is connected to the first input of the control panel and connected to the trigger output, in One installation unit of which is connected to the first output of the control panel, the trigger zero input is connected to the second input of the AND element and connected to the output of the 3 AND OR element, the first and second inputs of which are connected to the direct output of the reset pulse generator, the third and fourth inputs of the 3 AND OR element NOT connected to the output of the first OR element, the sixth input is connected to the second output of the control panel, the fourth and fifth outputs of which are connected respectively to the first and second control inputs of the block of elements AND OR, an integral output of which is connected to the first input of the first OR element, the second input of which is connected to an additional input of the autonomous control unit, the input bus of which is connected to the first inputs of the OR elements of the OR block and to the second inputs of the control panel and the second OR element, the second inputs of the element block And OR are connected to the output bus of the control panel, while the output of the AND element is an additional output of "Setting 0" of the autonomous control unit.  6. The system according to claim 5, characterized in that the control panel comprises a light indication unit, twenty-two chains of pulse shapers and buttons connected in series, the first inputs of which are combined and connected to the power terminal, the first, second, third and fourth triggers, an OR element , a pulse counter, a decoder and a register, the eight bit inputs of which are connected respectively to the outputs of the first eight pulse shapers, the control input of the register is connected to the twenty-sixth input of the light indication unit and the connection n to the output of the ninth pulse shaper, the first eighth register outputs are connected to the outputs of the control panel of the same name, the inputs of the light display unit and make up the data bus of the control panel, the ninth fourteenth inputs of the light display unit are connected to the outputs of the control panel of the same name, which is an address bus, and are connected respectively with the first sixth outputs of the decoder, the inputs of which are connected through the pulse counter to the outputs of the tenth pulse generator, the fifteenth twentieth inputs and the light indications are connected to the same outputs of the control panel, which together with the twenty-first output make up the control bus, and are connected respectively to the outputs of the eleventh sixteenth pulse shaper, the twenty-first input of the light indication unit is connected to the same output of the control panel and connected to the direct output of the first trigger, counting the input of which is connected to the output of the seventeenth pulse shaper, the twenty-second input of the light indication unit is connected to the output of the eighteenth the pulse shaper and is connected to the first additional output of the control panel, the second additional output of which is connected to the twenty-third input of the light indication unit and connected to the first output of the second trigger, the counting input of which is connected to the output of the nineteenth pulse shaper, the third additional output of the control panel is connected to the twenty-fourth the input of the light indication unit and is connected to the direct output of the third trigger, the counting input of which is connected to the output of the twentieth shaper pulses, the fourth additional output of the control panel is connected to the twenty-fifth input of the light indication unit and connected to the direct output of the fourth trigger, the unit setting input of which is connected to the output of the twenty-first pulse shaper, the zero setting input is connected to the output of the OR element, the first input of which is connected to the output twenty-second pulse shaper, the inverse output of the fourth trigger is connected to the fifth additional output of the control panel, the sixth additional output of which is connected n to output PFN fourteenth, twenty-seventh block output light indication yaalyaetsya first input of control unit, the second input of which is connected to the second input of the OR gate.  7. The system according to claim 5, characterized in that each buffer storage device contains a memory unit, a first and second one-shot, connected by outputs to the control inputs V "Read" and W "Write" of the memory unit, the outputs of which are outputs of the buffer storage device , a pulse counter, an AND element, an AND NOT element, and an OR element, the first input of which is the address translation address of the buffer memory, the second input of the OR element is connected to the input of the first one-shot and is the control input the "buffer memory", the third input of the OR element is connected to the first input of the AND element and is the control input "Record" of the buffer memory, the address inputs of which are connected to the outputs of the pulse counter, the zero-setting input of which is the zero-setting input of the buffer memory, the counting input the pulse counter is connected to the output of the elements AND NOT, the first input of which is connected to the second input of the element And is the first control input of the buffer storage device second input of AND NOT connected to the output of the OR gate, the third input of AND NOT a second control input of the buffer memory, which together with the control inputs of the "Read", "Write" and the data bus of the storage unit is a control bus and a data buffer memory.  8. The system according to claim 1, characterized in that the interface comprises a first decoder, transceivers, output and input registers with transmitters and receivers respectively switched on, a command register with a second decoder and a status register, the inputs of which, like the inputs of the same names of the other registers, connected via transceivers to a common bus to which the inputs of the first decoder are connected, the first, second, third and fourth outputs of which are connected to the address inputs of the data output register, command register, register and the status register, respectively, the outputs of the data transmitter, the output register, and the outputs of the second decoder are connected to the output bus of the interface, the input bus of which is connected to the input of the receiver of the input register and the inputs of the status register, the outputs of the data of the output register are connected via transmitters to the first eight outputs of the interface, the following six outputs of which are connected to the first six outputs of the second decoder, the remaining seven outputs of the second decoder and the strobe output of the data output register are connected to the last eight interface outputs, the first input of the interface through one of the receivers is connected to the input of the strobe pulse of the input register, the second and third inputs are connected respectively to the first and second inputs of the status register, the remaining inputs of the input register are connected to the inputs of the interface through the receiver.