SU468369A1 - Converter code analog - Google Patents

Description

(54) CODE ANALOG TRANSMITTER

The invention can be used in measurement technology, in data conversion and transmission systems.

Code-to-analog converters are known that contain a matrix of analog elements, a switch, a block of reference parameters, an analog-code converter, an auxiliary weight register, a comparison circuit, a synchronization block and a code master, and the matrix output of analog elements is through a switch whose second input is connected with the output of the reference parameter block is connected to the first input of the analog-code converter, the output of the auxiliary weight register is connected to the first input of the circuit, the comparison, the first output of which is connected to the second the input of the converter analog-code

However, the known devices have low speed and modulation of the output signal in the process of setting its new value.

The aim of the invention is to eliminate the modulation of the output signal, if the increase in speed.

For this purpose, additional switches, a memory register, a key circuit, a block of registers of bit weights, a difference register, a reference code register are entered into the code analog converter, the second output of the comparison circuit through the memory register: and the key circuit is connected to the input of the analog matrices elements, the output of the analog-code converter through the first additional switch directly and through the block of registers of discharge weights and the second additional switch connected to the inputs of the auxiliary weight register, t comparing the second output circuit chei Res register difference and the reference code register, a second input of which is connected to the output setpoint code, connected to the second input of the comparison circuit, which fourth output I connected to an input sinhroschizatsii unit outputs are connected to inputs of soot- Ivetstvuyuschimi all blocks. f in the drawing is illustrated with a block diagram of the proposed converter.

The device contains a matrix of analog elements 1, a key circuit 2, a memory register 3, a block of registers of discharge weights 4, a second additional switch 5, a switch 6, a block of reference parameters 7, an analog converter S code, a first additional switch 9, an auxiliary weight register 10 synchronization unit 11, the comparison circuit 2, the difference register of the reference code 14 and the sensor code 15. The converter operates as follows. First, the correction of the converter 8 is performed. For this, the signal from the synchronization unit 11 through the switch 6 connects the output of the reference parameter block 7 to the input of the converter 8, In the code setter 15 /, the code corresponding to the reference parameter of the block 7 is set. the switch 9 is connected to the register 10. The signal of the block 11 is transferred to the code of the block 15 is transferred to the register 14, and the register 10 is recorded from the output of the converter 8. The difference of the codes from the first output of the comparison circuit 1 is factory Its conversion to E | 4 | t is in .dl correction its characteristics. Then, the matrix 1 is calibrated. For this purpose, the output of matrix 1 is connected via switch 6 to the input of converter 8, the output of which is connected via a first additional switch 9 with a register of discharge weights 4. In block 15, the code N g i is set to be converted. All bits are consecutively calibrated. To do this, first, by the signal of the 11th digit, matrices, except for the first (minor), are set to zero, the first to one, From the output of the converter 8, the N code corresponds to the value of the first digit of the matrix , write to the register of the first bit of block 4. Next, the second bit of the matrix is set to one, all others are zero .: The resulting code Ng of the weight of the second bit from the output of the converter 8 is written to the second bit register of block 4, etc. After the code M has been written, the weight of the last bit in block 4, the converter 8, is output by the signal of block 11 from the conversion mode. The next step is to determine such a set of bits of matrix 1 which gives Y, corresponding to the given Ng code. To do this, by signal N from block 15 of block 11, the code is written to register 14, code N is rewritten via switch 5, to n inputs to register 10. Codes N, and N1 are compared in circuit 12. If. From the fourth output of circuit 12 to the input of block 11, a signal is sent, which is erased in register 1O, I-th with number .-: register bit 3 is set to zero, and code 10 is copied to switch 10 via switch 5; th bit, which is again compared with the Ng code in circuit 12. If Nn NgT is the same as n-1 any other weight Nj) then the signal from the fourth output of circuit 12 by the synchronization unit 11 records the difference code (N d -NYX, X erased codes in registers 1O and 14, the code from register 13 is rewritten into register 14, and P-th bit 3 is set to one. its code ib is rewritten with the code Nf. | (.P.-) of the bit and the comparison process continues. Codes N'-1 HCNg-Nn are already compared). If NVI Ng (as well as any other code N j), the th bit of register 3 is set to, all subsequent (lower than N or Nl are set to zero. After this, the signal of block 11 registers the code 3 through a key circuit 2 is rewritten into the matrix. 1. In the process of determining the state of the register 3, the state of matrix 1 does not change, that is, i.e. after overwriting the code from register 3 to matrix 1, the value of Y changes from the previous one to the next, intermediate stages. Thus, the V transform occurs without parasitic modulation of the output signal Y. Calculate the number of cycles needed to convert N4 N ,, .- a .., YV / - dllqNC taxes. The calibration step requires fff cycles to convert and write to block 4 N, N codes. In the search stage of register 3. In the worst case n cycles of comparisons are needed (according to the number of bits of the matrix 1). As a result, the total number of cycles in the proposed device is 2p in performance in comparison with the known device J21-a

Thus, the proposed device is faster and does not have spurious modulation of the output signal.

Subject invention

A code-analog converter containing a matrix of analog elements, a switch, a reference parameter block, an analog-code converter, an auxiliary weight register, a compared circuit, a synchronization block and a code master, the matrix of analog elements being output through a switch whose second input is connected to the output of the reference block parameters, connected to the first input of the analog-code converter, the output of the auxiliary weight register is connected to the first input of the circuit) Srayeni, the first output of which is connected to the second input Analog converter, characterized in that with

6

The purpose of eliminating modulation of the output signal and speeding up is the additional switches, a memory register, a key circuit, a register unit of discharge weights, a difference regulator, a reference code register, the second output of the comparison circuit through the memory register and a key circuit. connected to the input of the matrix of analog elements, the output is

10 generator analogue code through the first additional switch directly and the register of discharge weights and the second additional switch connected to the inputs of the auxiliary weight register

15, the third output of the comparison circuit through the difference register and the reference code register, the second input of which is connected to the output of the code master, is connected to the second input of the comparison circuit, the fourth output of which is connected to the input of the synchronization unit, the outputs of which are connected to the corresponding inputs of all blocks.