SU1195360A1 - Device for determining extreme points - Google Patents

Description

The invention relates to measuring equipment and can be used in radio devices and devices for static accounting and signal analysis.

The purpose of the invention is to increase the speed of the device.

The drawing shows the block diagram of the device.

The device for determining transitions and extrema contains a n-bit register 1, elements 2 and 3 BAN, elements OR 4-6, elements 7 and 8, elements OR 9 and 10, and trigger 11.

The device works as follows.

The range of change of the controlled value is divided into bits. The signal corresponding to a certain digit of the input quantity (XI, X2, X3 ... Xn) is fed to the corresponding single input of the η-bit storage register 1. At the same time, the trigger corresponding to the given digit and on its unit triggers on the ή-bit register 1 the output signal appears at the information inputs of the elements of the prohibition of 2 and 3 and the input element And 8 of this category, as well as through the elements OR 5 to the inputs of the elements And 7, and prohibiting the inputs of the elements of the PROHIBITION 3 senior bits. The signal from the output of the open element of the prohibition 3 of this category opens the element I 7 through one of the inputs and closes the element of the prohibition 2 of this category. Thus, the signal from the unit output of this category of memory register 1 prepares the opening elements 8 and the input element 7 of this category for one of the inputs: PROHIBITION 3 of the most significant bits of the register are simultaneously closed with the same signal. If, when changing the input value, find its value in any other range, then the corresponding single input of the η-bit storage register I receives a signal that sets

the corresponding trigger in a single state.

Suppose that a trigger of the highest order is set to one state, which corresponds to an increase in the value of the input quantity. Then the signal from its single output does not pass through the element closed by the signal from the low-order trigger.

Yu BAN 3, and enters through the open element BAN 2 of this category and through the elements OR 4 at the second inputs of the elements AND 8 of all the low-order bits. Where the signals match

15 low and high bits, the AND 8 element will open and the signal from its output through the OR element 9 will go to the zero input of trigger 11, simultaneously through the OR 6 element {except for the first digit connected directly to the output of the And 8 element) resetting the low bit of register 1 to zero state.

If, when the input value changes, the trigger of the lower order will be set to one state (which corresponds to a decrease in the input value, then the signal from its output through the elements OR 5 will go

30 to the second inputs of the elements And 7 all senior bits. Where there is a coincidence of signals of the older and younger ones. the signal from the output element And 7 through the element OR 10

* will go to the single input of the trigger 11, simultaneously through the element OR 6 (except for the last digit connected to the output of the element And 7 directly) resetting the high bit of the register I to the zero state.

Thus, when the input value increases, the signals from the outputs of the And 8 elements arrive at the zero input of the trigger 11, keeping it steady, and when it decreases, from the outputs of the And 7 elements to its single input, tilting the trigger 11 to another stable state. Moment tipping trigger 11

, θ corresponds to the extreme value of the input value.

I> 95360

Claims (2)

A DEVICE FOR DETERMINING EXTREMUES, containing a register, AND groups of elements, OR elements, a trigger whose output is a device output, an output of the h-th digit of the register (ΐ = 1, η-ι) is connected to the first input of the ί -th element of the first group, the output of the elements And the first group are connected with the same inputs of the first element OR, the information input of the register is the information input of the device, the output of the first element OR is connected to the installation input to the trigger unit, the installation input to which zero is connected to. the output of the second element OR, characterized in that, in order to improve performance, it introduced the first, second and third groups of OR elements, two groups of BANKS elements, the input of the setting to zero of the 1st register bit is connected to the output (Ϊ-1). th element OR of the first group, the inputs of the installation to zero of the first and d-th bits of the register are connected respectively with the output of the first element of the first group and the output of the η-th element of the second group, the outputs of the elements of the second group are connected to the same inputs of the second element OR, the output of the (ΐ + 1) -th digit of the register is connected respectively to the first inputs of the ί — x elements 'of the first and second groups and with the same inputs of the OR elements, starting with} th, first group (} · ΐ, η-2) "whose outputs are connected to the first inputs of the (ί + 1) -x elements of the second group and the second the inputs ("+1) of the elements BANNER the first group, the second input of the first element BANKS the first group Py combined with the first ... input of the first element of the second group and connected to the output of the first digit of the register, the output of the h-th element of the BANNER of the first group is connected to the second input of the ίth element of the BANNER of the second group, the output of the 8th element of the second group is connected · To the first input of the? Th element OR of the second group, the second input of which is connected to the output of the E th element AND of the first group, output | th element of the BANNER of the second group is connected to the m inputs of the elements OR of the third group, the output (—th element OR of the third group is connected to the second input ΐ —th element AND of the first group; the second input (n-1) —th element AND of the first group is connected to the exit (n-1) —th element of the prohibition of the second group. 5i _and "P95360 one I 195360 2