SU1239611A1 - Device for measuring extreme values of continuous signal - Google Patents

Abstract

This invention relates to digital measurement technology. The purpose of the invention is to expand the functionality of the device. The device contains an analog-to-digital converter 1, a reference element 2 and a memory register 3. Introduction to the register device 4 of memory, elements I 5 and 6, the element IL 7 and connecting them to the elements of the device makes it possible to measure the extreme values of any continuous signal, including alternating signals of continuous form. In this case, when comparing codes, the sign bit must be taken into account in order to avoid malfunctioning when the signal passes through zero. 2 Il. i f g y co co od Figure 1

Description

112

The invention relates to the field of digital measurement technology and can be used to measure the extreme values of non-linear signals.

The purpose of the invention is to expand the functionality of the device by measuring all the extreme values of the signal.

FIG. 1 shows a block diagram of the device; in fig. 2 is a timing chart of the input continuous signal.

The device for measuring the extreme values of non-diverg signals contains the following analog-digital converter 1, the comparison element 2, the first memory register 3, the second memory register 4, the first 5 and the second 6 AND elements, and the OR 7 element.

In the device, the output of the following analog-digital converter 1 is connected to the inputs of the comparison element 2, the first 3 and second 4 registers

Thus, up to the newly recorded value codes in the first register are less than the digital coding at the output of the trace of the digital converter working as before, starting from the moment t ,. to register 3 memory write down

thirty

code NJ, all subsequent or less N. At the same time

memory pitch, control input first

the first memory register 3 is connected to the first output of the comparison element 2 and to the input of the first element 5, and the control input of the second memory register 4 is connected to the second output of the comparison element 2 and the input of the second element AND, the outputs of the memory registers 3 and 4 are connected to the other inputs of the elements And 5 and 6 outputs of which are connected to

the inputs of the element OR 7, the output of which is the 35 code, fixed in go is connected to the second input of the element 2 of the comparison.

The device works as follows.

element 2 compares cash O, which is closed by And 5 and prohibits for the first register 3 memories

the memory is a code that is maximum at a given time in a given period of time.

Minimum search: 1a is signaled to maximum search.

Let at time t, the input continuous signal U be zero, respectively, at the output of the following analog-digital converter 1. - zero code, registers 3 and 4 of memory - to 40

Minimum search: 1a signal is similar to maximum search.

Since the digital code is N,

less to

about

yes N5, then on the second output of the element 2

g; at the outputs of element 2, by comparison, by the time tg, will write the code N.

This means that since the moment t, the value of the input signal grows accordingly, the digital code increases at the output of the following analog-digital converter 1. Thus, the first input of the comparison element 2 will receive the growing value of the digital code, and the second input of the comparison element 2 is the zero code, since registers 3 and 4 of memory are in the O state. At the same time, the ratio at the first output of the comparison element 2 is Wits 1.

the second register 4 of memory and opens the second element AND 6. At the same time, at the outputs of the element 2, a comparison is compared with 0, but since the value of the input

The 50 signal is killed, then after some time its code will be less than the N code recorded in the second register 4 of the memory. At the same time, at the second output of comparing element 2, compares the signal 1 to the signal 1 which instead of the code N (5 stored in memory register 4 since time t, will write the code Ny, etc.

-6

five

and at time t. the current value of the N code from the output of the following analog-digital converter 1 is written to the first memory register 3. The first element 5 also opens simultaneously at the outputs of the comparison element 2 is shown, but since the value of the input signal increases, after some time the digital code will be greater than the N code recorded in the first tee. At the same time, at the first output of the comparison element 2, the signal 1 again appears, which will write the code N in the first register 3 of the memory from the moment t

 2 3 memory N instead of digit0

2, the first AND element 5 stored therein 5 opens, and O, etc. appears at the outputs of the comparison element 2.

Thus, as long as the newly recorded values of the digital codes in the first register 3 of the memory are less than the digital codes appearing at the output of the following analog-digital converter 1, the device operates as before. Starting from the moment t ,. when in the first 3 memory registers digital

NJ, all subsequent codes are equal or less than N. At the same time, the first code is fixed to

The comparison element 2 will signal O, which closes the first element of AND 5 and prohibits the writing of codes to the first register 3 of the memory. Digital

register 3

the memory is the code corresponding to the maximum of a continuous signal at a given time interval.

Search for the minimum: 1a signal is similar to the search for the maximum.

Since the digital code is N,

less koo

yes N5, then on the second output of the element 2

g; The second register 4 memory and opens the second element AND 6. At the same time, at the outputs of the element 2, the comparison is 0, but since the value of the input

the signal is killed, then after some time its code will be less than the N code recorded in the second register 4 of the memory. At the same time, at the second output of comparing element 2, signal 1 again takes place, which instead of code N (5 stored in memory register 4 from the time t, will write down code Ny, etc.

-6 Beginning from the moment t, when in the second register of 4 memory, the digits are written, the subsequent codes from the output, the following analog-digital converter 1 are equal to or greater than NJJ. At the same time, the second output of the comparison element 2 will be O, which closes the second element And 6 and will prohibit writing to the second register 4 of the memory, in which the code of the signal minimum N.

Thus, the device operates in the following mode, i.e. if the code from the output of the next analog-to-digital converter 1 exceeds the code recorded in the first register 3 of the memory by at least the low-order bit, then 1 appears on the first output of the comparison element 2 and the code from the output of the next analog-digital converter 1 is rewritten in the first register 3 of memory, and the first element AND 5 is sprinkled to the second input of element 2 of the comparison of the code values stored in the register 3 of memory. As soon as this condition is violated, the first output of comparing element 2 is O, the first element of AND 5 is closed, and in the second register 3 the memory will be stored with the code of the signal maximum. At the same time, the second element 2 compares Wits signal 1 and begins to search for the minimum of the signal, which is similar to the search for the maximum. If the code from the output of the following analog-digital converter 1 is less than the code recorded in the second memory register 4, even by the low-order bit, 1 appears at the second output of the comparison element 2 and the code from the output of the following analog-digital converter 1 is written to the second register 4 of the memory, the second element 6 is opened to feed the second input of the element 2 to a comparison of the current values of the codes stored in the second register 4 of the memory.

As soon as this condition is violated,; then on the second output of the element 2 of the comparison, according to Wits O, the second element And 6 is closed and in the second register

5 s tO

15 20 25 jq.,. .

396114

re will store the minimum signal code. The removal of the maximum value should take place between the moments of fixing the maximum and minimum,

The removal of the minimum value should take place between the moments of fixing the minimum and maximum.

The proposed device makes it possible to measure the extreme values of any non-original signal, including continuous-shaped alternating signals, in which case, when comparing codes, the sign of the bit must be taken to avoid incorrect operation when the signal passes through zero.

Claims (1)

Invention Formula A device for measuring extreme values of continuous signals, containing the following analog-to-digital converter comparison element, the first memory register, the output of the following analog-digital converter connected to the inputs of the comparison element and the first memory register, the control input of which is connected to the first the output of the comparison element, characterized in that, in order to expand the functionality, the second memory register of the first and second elements of the AND and are entered into it. the OR element, the information input of the second memory register is connected to the output of the following analog-digital converter, the control input of the second memory register connected to the output of the second element AND and the second output of the comparison element, the other input of which is connected to the output of the element OR, the inputs of which are respectively connected to the outputs of the first and second elements AND, the other input of which is connected to the output of the second memory register, the output of the first memory register is connected to one input of the first element AND, the other input cat An op is connected to the first output of the reference element. 35 45 50 } tz J v Rem Removing the Maximum minimum pickup time FIG. 2