SU1280598A1 - Multichannel microprogram counter - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in control computing systems with time distribution functions, as well as in the unified time service tools or in systems for calculating the life of devices. The purpose of the invention is to expand the scope by providing an account in any number system. The device contains a memory block, a counter, an address register, a pulse generator, a microprogram memory block, a waiting multivibrator, two triggers, a buffer register, and a multiplexer. New in the device is the use of a standby multivibrator, two triggers, a buffer register and a multiplexer, which allows to realize an account in any number system. 1 il. SL C

Description

The invention relates to automation and computing, and can be used in control computing systems with time-distributed functions, as well as in a single-time service or device life counting systems.

The purpose of the invention is to expand the scope by providing the account B with any number system.

The drawing shows a functional diagram of the proposed multi-channel firmware counter.

The multi-channel firmware counter contains 1 RAM block, 2 counter, address 3 register, 4 pulse generator, microprogram memory block 5, standby multivibrator 6, triggers 7 and 8, buffer register 9, multiplexer 10, output group 11 of the conversion factor number and group outputs 12 values of the conversion factor.

The RAM block 1 is designed to store the values of all parameters, with each parameter corresponding to a certain cell of block 1. Counter 2 is designed to intermediately store the corresponding parameter, as well as to change the value of this parameter. Register 3 addresses provide addressing of the firmware memory block 5.

A pulse generator 4 is needed to form time stamps determining the accuracy of the resource measurement.

The microprogram memory unit 5 is intended for storing microprograms that provide processing of parameters (conversion factors) in accordance with the counter operation algorithm.

The waiting multivibrator 6 provides for the formation of clocking pulses that determine the rate of operation of the resource counter.

Trigger 7 ensures that the low-order overflow signal is stored (with respect to the processed) bit.

The trigger 8 provides testing of the full operating cycle of the counter.

The buffer register 9 is designed to store the address (number) of the corresponding parameter for the time it is processed.

The multiplexer 10 provides for the bit-wise switching of the corresponding parameter for its bit-by-bit analysis, as well as the analysis of the state of the trigger 7.

The output lines 11 and 12 are for outputting information from the device, with the line 11 indicating the parameter number, and the line 12 being its current value.

The groups of bits A and Aj of microprogram memory block 5 (Fig. 1) are intended for addressing microprogram memory block 5 and operative memory block 1, respectively.

The group of bits of the microprogram A memory block 5 (Fig. 1) provides control of the multiplexer 10 to switch the value of the corresponding parameter by bit-wise when it is analyzed for equality to a given conversion factor. The analysis is carried out programmatically using the appropriate firmware implemented by block 5 of the firmware memory.

The microcommands Y, and Yj provide trigger control 7: respectively, reset to 0 and set it to one state.

The microcommand Yj provides the write / read operating mode of block 1 of one0 memory. At the same time, the information reading mode from block 1 is provided, while at Yj 1, information is recorded in block 1. Micro-command Y provides the increment of the counter 2, and micro-command Yj provides its zeroing. Y. Scrocade serves for

B

recording information into the counter 2. The microcommand Y resets the contents of the trigger 8 to 0.

0 Multichannel firmware counter is designed to determine the duration of the operation of some equipment or its main components. (devices). Counting the output of production by ftitc by counting the time stamps generated by the pulse generator during the time when power is applied to the device.

Before starting the operation, the counter is reset. The initial state is the zero state of all memory elements: cells of block 1, register 3 addresses, buffer register 9, counter 2, triggers

5 7 and B.

Claims (1)

Resetting is performed by applying an external signal. The reset to the R input of the trigger 8, then with the zero value of its Q output, the trigger 8 resets the buffer register 9 and the address register 3. In turn, the zero value of the address register 3 reads a zero microprogram word from the microprogram memory block 5, in which microcommands Y are recorded and the tamping conditions of trigger 7 and counter 2, respectively. Upon completion of zeroing, a signal from the pulse generator 4 sets up into a single state of the trigger 8, with the signal from the Q-output of which a waiting multivibrator 6 is triggered, which ensures the formation of clock pulses that synchronize the operation of the device. The entire operation of the device can be represented as a set of partial cycles Tug, constituting a complete cycle T. Which private cycle corresponds to the processing subroutine of the corresponding parameter. The number of parameters is determined, on the one hand, by the accuracy of the resource counter, and on the other hand, by the value of the maximum conversion factor. Each of the cycles is divided into chaps, and at each step the corresponding micro-operations are performed. All cycles are performed similarly, with the exception of the first and last, which differ only in the input and output operators of the corresponding subroutines. The difference in the representation of subroutines that implement the corresponding parameter is also to bind them to the corresponding cells (addresses) of the 5 firmware memory blocks and to allocate the values of the corresponding parameters in the main memory unit 1. The resource counter parameters are understood as conversion factors used to count the number of units, tens, hundreds and tens of hundreds of milliseconds, units, tens of seconds, units, tens minutes, units, tens, hundreds, thousands of hours, etc. . hours Each parameter is represented by a binary-decimal code in the corresponding cell of the operational memory block 1, starting with zero. Thus, the number of cells in memory block 1, necessary for the implementation of the device, is equal to the number of coefficients recalculation parameters of the resource counter (n): Nn Thus, the counter operation consists of n cycles, and each cycle consists of ha steps ( natural integers). The generalized algorithm of the device operation on the first cycle can be represented as follows. From the memory unit 1, the contents of the corresponding cell are read. This content is a binary four-digit code (since the conversion is carried out in a binary-decimal code), representing the value of the corresponding conversion factor. This code is bitwise (decomposed on multiplexer 10) using the appropriate firmware, implemented in block 5 of the firmware memory, addressed via address 3 register, is analyzed for equality to its conversion factor of the corresponding parameter. If the current and specified values of the conversion factor are equal, the transfer unit is memorized to the highest bit on trigger 7 (trigger 7 in this case is set to state 1). Counter 2, on which the current value of the recalculation coefficient is recorded, is zeroed out, and its zero content is written into memory unit 1 at the address from which the recalculation coefficient was read. If the current and specified recalculation coefficient values are not equal, then the content of counter 2 is increased by one unit and the new value is written to the cell of the operational memory 1 according to the address set on buffer register 9. The listed actions are repeated in other cycles with the only difference that the summation of the unit to the current value of the conversion factor selected from the RAM 1 is performed before analyzing the current value of the conversion factor if in the previous cycle the trigger 7 was set to viz 1, i.e. there was a transfer from the previous bit, otherwise - there was an overflow of the previous conversion factor. Thus, at each step, with the help of bit group A, control is transferred from the previous firmware to the next. When the last firmware word is executed, or if the specified value is not equal. The first of the sequentially analyzed conversion factors results in zeroing of the trigger 8, which zeros the contents of the buffer register 9 and the address register 3 with a signal from the Q-output. The calculation process begins again after the arrival of the next pulse from the pulse generator 4. Invention Multi-channel firmware counter containing a block of RAM, whose outputs are connected to the information inputs of the counter, address register, the outputs of the counter are connected to the information inputs of the RAM, pulse generator, microprogram memory block, group of outputs of the first address in which connected to the first group of information inputs of the address register, the outputs of which are connected to the address inputs of the microprogram memory block, characterized in that, in order to expand ty use by providing accounts in any notation system, it introduced a monostable multivibrator, two trigger buffer register and a multiplexer, n data inputs of which are connected to the n outputs of block 40 iflOB operational memory, where n - disarmament. The input inputs of which are connected to the outputs of the buffer register, the information inputs of which are connected to. the group of outputs of the second address field of the microprogram memory unit, the group of outputs of the field of analysis of conversion factors of which is connected to the control inputs of the multiplexer (n + 1) -th information input of which is connected to the forward output of the first trigger, and the output of the multiplexer is connected to the second information input the address register, the synchronous input of which is connected to the output of the waiting multivibrator, the direct output of the second trigger is connected to the Start input of the waiting multivibrator, and the installation inputs to 1 and O of the second trigger are connected respectively, with the output of the pulse generator and with the device reset input, the first, second, third, fourth, fifth, sixth and seventh outputs of the micro-operations group of the microprogram memory unit group are connected to the installation inputs O and 1 of the first trigger, respectively, the read write input an operative memory unit, with a counting input of an installation into O and an input of a counter record, with an input of an installation into O of a second trigger, the direct output of which is also connected to the inputs of an installation into O of a buffer register and an address register, and information outputs The buffer register and counter are connected to the output group of the number of the coefficient of the device count and the group of recalculation coefficient respectively.