JPH03139741A - History information storing system - Google Patents

Abstract

PURPOSE:To store much hardware history information with small storage capacity by using a synchronous signal for generating a clock having an (n)-fold period. CONSTITUTION:The values of two registers 2 and 3 which are equal for (n) cycles are selected with the synchronous signal which performs control so that a clock is inputted to the registers 2 and 3 once in every (n) cycles, and the data and synchronous signal are stored as history information in a storage part 5. Namely, the storage part 5 is stored with the contents of one of the two registers for cycles which are (n) submultiples of (n) cycles and with the contents of the other for the remaining cycles. Then the polarity of the synchronous signal which is stored simultaneously is used as an identification signal to judge which register contents stored data is. Consequently, the capacity of the storage part for storing the history information is reduced and a low-cost computer can be developed at low cost.

Description

[Detailed Description of the Invention] [Ia Essential] Regarding the storage method of history information in the storage unit of computer hardware, for the purpose of reducing the capacity of the storage unit that stores history information, a basic clock and a A clock control unit (1) that generates a clock N that is n times the basic clock (n≧2) based on a synchronization signal that has a period that is n times as large as that of the basic clock, a register (2) in which data is set by the clock N, and a register (
3) and a register (2) depending on the polarity of the synchronization signal.
and a selection control unit (4) that selects one of the registers (3) and
), and a storage section for storing the contents of the register selected by the selection control section and information regarding the polarity of the corresponding synchronization signal.

[Industrial Application Field] The present invention relates to history information (hereinafter also referred to as history information) that is collected as information for analyzing circuit operation in order to search for the cause of a hardware failure in an electronic computer (hereinafter also referred to as computer). The present invention relates to a method of storing information in a storage unit, particularly a method that allows necessary information to be stored in a small-capacity storage unit.

[Prior Art] Electronic computer circuits are made up of a huge number of gate elements, etc., and when a failure occurs in one of these, it is not easy to search for the cause of the failure.

For this reason, changes in the main parts of the operating hardware are collected and stored as historical information, and when a failure occurs, this information is used as a clue to search for the location that caused the failure.

Conventionally, in such a history information storage circuit, a method has been adopted in which a register output of a hardware control signal necessary for failure analysis is connected one-to-one with the human power of a storage unit (RAM, etc.).

That is, this allocates 1 bit of the storage section to 1 bit of the register. The actual storage unit is, for example, 1
It is configured such as using five 4kRAMs with 6 bits) x 256 cycles.

[Problem to be solved by the invention] As the circuit configuration of computer hardware has become more complex in recent years, the amount of control information required for analysis in the event of a failure has increased. ing. In contrast, the capacity of the storage unit that stores history information (
There is a way to increase the number of RAM and registers, but
Since this would require a significant increase in the amount of hardware compared to the past, there is a desire for a method that can store all the necessary history information without increasing the capacity of the storage unit as much as possible.

In particular, this has been a pressing problem in realizing low-cost, miniaturized computers.

SUMMARY OF THE INVENTION In view of these conventional problems, it is an object of the present invention to provide a means for storing as much hardware history information as possible with a small storage capacity.

[Means for Solving the Problems] According to the present invention, the above objects are achieved by the means described in the claims.

That is, the present invention provides a clock control unit that generates a clock N that is n times the basic clock (n≧2) using a basic clock and a synchronization signal that has a cycle that is n times the basic clock;
A register A and another register B in which data is set by a clock N, a selection control section that selects one of the register A and the register B depending on the polarity of the synchronization signal, and a register selected by the selection control section. This is a history information storage method that includes a storage unit that stores the contents of the synchronization signal and information related to the polarity of the corresponding synchronization signal.

"Working" FIG. 1 is a diagram illustrating the present invention in detail.

4- In the same figure, 1 is a clock control unit, and n of the basic clock is
A clock N with twice the period is generated.

2.3 is a register, and a value is set in synchronization with the clock N of each one cycle.

Reference numeral 4 denotes a selection unit that selects the output of register 2 and the output of register 3 using 5IGI, which is a synchronization signal for increasing the clock cycle by n times.

Reference numeral 5 denotes a history information storage unit which stores the value of the register selected by the selection unit 4 and information regarding the corresponding polarity of SIGI as his/IJ information.

In the present invention, from the outputs of two registers as shown in FIG.
First, one is selected, and the other is selected before the register value changes, and these values are stored in the storage unit as history information every cycle. This allows 2
It is easy to understand how the two registers change over a certain period of time (the number of cycles determined by the capacity of the storage section).

That is, the present invention selects the values of two registers that have the same value for n cycles using a synchronization signal that controls a clock to be input to the register once every n cycles, and synchronizes with the data. By storing the conversion signal in the storage unit as history information, the contents of one of the two registers are stored in the storage unit for several nth cycles between n cycles, and the contents of the other register are stored in the storage unit during the remaining cycles. It controls the storage of data, and uses the polarity (“0” or “1”) of the synchronization signal that is stored and wiped at the same time as an identification signal to determine which register contains the contents. be.

In the present invention, the capacity of the storage unit for storing history information can be reduced by the above method, and it is possible to develop a compact computer at low cost.

[Embodiment] FIG. 2 is a block diagram of an embodiment of the present invention, showing a history information transfer circuit in computer hardware. In the figure, reference numeral 1a denotes an AND circuit for controlling the clock, which makes the clock cycle n times the basic cycle. 2a
3a is a flip-flop (hereinafter also referred to as FF) constituting the register high, and 3a is an FF constituting the register low. Reference numeral 4a denotes a selection signal generation circuit, which determines which of register high 2a and register low 3a to select based on synchronization signal 5ICI.

4b is an AND circuit for register high select, 4C
is an AND circuit for register low select, and 4
d is an OR circuit. These AND circuits 4b, 4c and OR circuit 4d send history information to the history information storage section. Reference numeral 5a denotes a history information storage circuit, which is composed of, for example, a RAM.

5b is a memory circuit pointer control circuit, which
By incrementing (or decrementing) the data, overwriting of the history information is prevented for a certain period of time depending on the storage capacity. Further, numeral 11 indicates a clock with n times the period, and 21, 31, 41, and 51 indicate signal lines, respectively, and these correspond to those described in FIG. 3, which will be described later.

FIG. 3 is a time chart explaining the operation of the embodiment shown in FIG. When the synchronization signal 5IG1 is input manually as shown in the figure, FF2a and FF3a are set.
The double period clock 11 becomes a double period clock as shown by 111 in the figure. Therefore, the FF is set once every two basic cycles. As a result, the output signal of register high 2a (signal of signal line 21) and the output signal of register low 3a (signal of signal line 31) are
This is shown as 21 or 31 in the figure. and,
When synchronization signal 5IGI is “1”, register high 2
If the output of a is selected and register low 3a is selected when it is "0", the history information sending signal is sent to the signal line 41 in FIG.
It becomes like a signal.

Next, the track layer information written in the history information storage circuit 5a when the circuit operates as shown in FIG. 3 will be explained using FIG. 4.

When the first clock is input, the pointer 51 indicates 1'', and the selected address is output with DA, TAL, which is the history information of the synchronization signal 5IGI, and register high and register low. History information DATA2 selected from among them is written.

From the second clock onwards, if the operation is as shown in Figure 4 and the history information is read from the history information storage circuit, what kind of history information it is will be shown in the figure. I can judge.

"Effect 1 of the Invention As explained above, the present invention uses a synchronization signal to generate a clock with an n-times period, so that one of the two registers set by the clock with an n-times period One of the registers is selected, its contents are read out, and the contents of the other register are outputted before the value changes and are stored together with the polarity of a synchronization signal for identifying them. Since it is possible to obtain sufficient history information necessary for failure analysis with half the storage capacity of , it has the advantage of making it possible to downsize the computer.

・・・・・・N times cycle clock, 21.31.41.
51・Old・Signal line

Claims (1)

[Claims] A clock control unit (1) that generates a clock N that is n times the basic clock (n≧1) using a basic clock and a synchronization signal that has a period n times the basic clock; Register where data is set (2
) and a register (3), a selection control section (4) that selects one of the register (2) and the register (3) according to the polarity of the synchronization signal, and the contents of the register selected by the selection control section. 1. A history information storage method, comprising: a storage section that stores information about the polarity of a synchronization signal and information about the polarity of a synchronization signal corresponding thereto.