SU1767500A1 - Microprogram control device - Google Patents

Abstract

The invention relates to computing and can be used to build blocks of microprogram control of a computer. The invention allows to increase the speed and reduce the memory capacity of microinstructions. For this, the device (Fig. 1) contains a block of memory of micro-instructions, a register of 3 micro-instructions, a first block of 2 memory, a first multiplexer 5, a first element I 6, a first block 7 of masking, a second multiplexer 8. a buffer register 9, a second block 10 masking, the second memory block 11, the second element And 12 and the address register 4. 9 il.

Description

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The invention relates to computing and can be used to build blocks of microprogram control of a computer.

The purpose of the invention is to increase the speed and reduce the memory capacity of micro-instructions.

FIG. 1 shows a block diagram of the device; in fig. 2 shows an example of implementation of a masking unit; in fig. 3 is a timing chart of the arrival of clock signals; in fig. 4 ... 9 - graph-schemes of algorithms.

The device (Fig. 1) contains a block of 1 memory of micro-instructions, a first block 2 of memory, a register 3 of micro-instructions, a register 4 of address, a first multiplexer 5, a first element AND 6, a first block 7 of masking, a second multiplexer 8, a buffer register 9, a second masking unit 10, second memory unit 11, second element 12, second clock input 13, reset input 14, logical conditions input 15, first 16 and third 17 clock inputs, first output 18 of the address field, first output 19 of the masking floor , the first output 20 of the type of the address modification type, the second output 21 of the recording attribute type address modification, the second output 22 of the address load address type field, the second output 23 of the address field 23, the second output 24 masking field, the second output 25 of the address type change attribute, the first output 26 of the address address loading address field, and the first output 27 of the sign records of signs of modification of the address of the register of 3 microinstructions,

The masking unit 7 (10) (Fig. 2) contains the elements NOT 28, the elements AND 29, the elements OR 30, the first 31, the second 32 information and control 33 inputs.

The timing diagram of the arrival of the sync signals is shown in FIG. 3. The clock signals C1, C2, NW follow one after another and are separated by time intervals.

In each microcommand, the mode of forming the address of the next microcommand is specified (unconditional or conditional transitions). The unconditional transition is given by the zero values of the mask signals coming from the output 19 of the registry 3 to the input 33 of the masking unit 7. The conditional transition is encoded with non-zero mask values.

In the unconditional transition mode, the address specified directly in the current microcommand, coming from the output 18 of register 3 to the input 32 of the masking unit 7, is output without changes to the output of the masking unit 7. From the output of masking unit 7, this address enters the information input of the register 4 addresses.

In the conditional branch, the directly specified address is modified. The modification consists in replacing the bits of the directly specified address (corresponding to the unit mask values) with the values of the bits of the sources of the modification. There are three sources of modification:

- the signs arriving at the input 15 of the device;

- signs buffered in previous operation cycles in memory block 2;

- signs installed in the memory block 11 during the execution of the microprogram.

The modification source is defined by control signals from the outputs 20 and 25 of register 3 to the control inputs of multiplexer 5 and multiplexer 8, respectively.

When using the first modification source, the signs through the input of the device arrive at the output of multiplexer 5.

When used as a source of modification of memory block 2 or memory block 11, information is fed from the output of register 9 to the output of multiplexer 5.

Firmware device operates as follows.

The device is reset to the initial state by a signal coming through the device input 14 to the reset inputs of register 3, register 4 and register 9. At the same time, registers 3 and 9 are set to state O, and the first executive address of the microprogram is entered into register 4 ( .

The chain of entry of the first executive address is not shown). From the outputs of register 4, this address is fed to the input of memory block 1.

In each cycle of operation of the device, its clock inputs 16, 17,13 are supplied with clock signals C1, C2, NW, respectively.

With the arrival at the input 16 of the clock signal device C1, the microcommand is read from memory block 1 into register 3.

From the output of block 2 memory (output block

I1 memory) reads information from the memory location. The address is set by signals from output 26 (22). The read information is fed to the information inputs of the multiplexer 8.

In accordance with the control signal from the output 25 of the register 3 to the control input of the multipilexor 8, this or that data is output to the output of the multiplexer 8.

The sync signal C2 supplied to the synchronous register 9 is recorded

the register 9 of the string value of block 2 of memory block 11 of memory), coming from the output of multiplexer 8 to the information input of register 9.

At the output of the masking unit 10, bits of a code or an old string value of the memory block 11 (or memory block 2) are issued in accordance with the values of the mask bits.

If it is necessary to buffer the features in a given operation cycle, the corresponding bits are set in the micro-instruction. The buffering of the signs arriving at the input 15 of the device is specified by the control signals coming from the outputs 26 and 27 of the register 3, respectively, to the address input and through the element 6 (building the C3 clock signal) to the read / write input of the memory block 2.

When installing the signs in the memory block 11, the selection of the line number is performed by address signals from the output 22 of the register 3 to the address input of the memory block 11.

The write to the memory block 11 is gated by the synchronization signal СЗ, coming from the input 13 of the device through the element 12 to the read / write input of the memory block 11,

Signals from the output of multiplexer 5, i.e. either signals from input 15, or signals from output of register 9, are supplied to the corresponding input of the masking unit 7.

At the output of the masking unit 7, directly specified address bits are output (from the output 18 of register 3), or information from the output of the multiplexer 5, in accordance with the values of the mask bits.

The clock signal SZ, arriving at the sync input of register 4, records B, register 4, the address of the next microcommand formed in this cycle, coming from the output of masking unit 7 to information input of register 4.

The arrival of the sync signal Sz ends the device operation cycle. Then everything repeats.

FIG. 4 shows two graph-schemes of algorithms with the same sequence of control signals: H1, H2H9.

FIG. 5 shows a generalized graph-flowchart including a sequence of control signals: H1, H2, ..., H9. When the micro-command A1 is executed in the memory block 11, the bit F (0): 0 is set, and when the micro-command 81 is executed in the memory block 11, the bit F (0) is set: 1. During the micro-command H9 the check is performed

conditions F (0) 0, after which actions are performed according to the first (Fig. 4a) or the second (Fig. 46) algorithm. The use of, in this case, memory block 11 allowed

5 to reduce the volume of the first memory block 1 by 9 cells.

FIG. 6 shows the flowchart of the algorithm with the union and branching of the branches. Micro-commands G1, G2, G3 are made

0 preparation of the analysis K L (for example, analysis of the command code).

FIG. 7 shows the same graph diagram itself, but using the setting (F (0): 0 or F (0): 1) and analyzing the feature (F (0)

5 0), which made it possible to exclude microcommands (G1, G2, G3) of preparation of the analysis.

When executing complex firmware, it is necessary to select the desired branch of the firmware, corresponding to

0 to all previous events that occurred during the execution of the firmware (Fig. 8). In this case, the analysis of the signs is carried out sequentially one after the other, with each analysis (L1, L2) preceded by

5 microcommands for preparation of a trait for analysis (L1. L2).

The proposed device implements the installation independently of each other (and sequentially one after the other) of several

0 bits (F (0), F (1) of the line of the memory block 11. This allows you to select the desired branch of the microprogram corresponding to all previous events that occurred during

5 execution of the microprogram (Fig. 9) (with simultaneous elimination of the microcommand L1, L2 for preparation of the analysis).

Claims (1)

Invention microprogrammed control device containing the first memory block, micro-command register, micro-memory memory block, address register, first multiplexer, first AND element, first masking unit, first, second and third informational inputs and output of which are connected respectively to the output of the first multipilexor, the first outputs of the micro-command address field and the micro-register register masking field and the information 0 by the input of the address register, the output of which is connected to the address input of the microinstructions memory block, the output of which is connected to the information input of the register of microinstructions, the first output of the sign of the address modification type of which is connected to the control input of the first multiplexer, the first information input of which is connected to the information input of the first the memory block and is the input of the logical conditions of the device, the first output of the sign of the recording of the signs of the modification of the register address of the micro-instructions is connected to the first input of the first element a And, the output of which is connected to the read input of the first memory block, the first clock input of the device is connected to the sync input of micro-commands, the reset input of which is connected to the reset inputs of the device and the address register whose synchronous input is single with the second input of the first element And i The second clock input of the device, the first output of the address field of the load of signs of the modification of the register of microcommands is connected to the address input of the first memory block, the output of the field of microoperations of the register of microcommands is the output The device, characterized in that, in order to improve speed and reduce the memory capacity of micro-instructions, it contains a second memory block, a second multiplexer, a buffer register, a second masking block and a second And element, the first and second inputs and output of which are connected respectively to the second clock input of the device, the second output of the sign of recording signs R 7 ( modifying the address of the microinstruction register and to the write / read input of the second memory block, the address, information inputs and output of which are connected respectively to the second output of the address field of the signs loading of the microinstruction register modification, the output of the second masking block and the first information input of the second multiplexer, the second the information and control inputs of which are connected respectively to the output of the first memory block and the second output of the type of the modification of the microcommand register address type, the second outputs the address field and the concealment field of which are connected respectively to the first information and control inputs of the second masking unit, the second information input of which is connected to the second information input of the first multiplexer and the output of the buffer register, the information input, the sync input and the reset input of which are connected respectively to the output of the second multiplexer, the third clock and installation inputs of the device. I -: -. and CI 3) -M-G-1 Iv) .. „m .. j: .-.- v.c - D i2) 0 r Kb .. J-IJ 73. B2 El K2 about o yu (Oh  © -I 0 | but but al YU SJ about o in -. h F4 .-. R („.-, -. .- -. ВЗ | Г Г5 | jenJ ten one 00