SU561964A1 - Firmware Control - Google Patents

Description

commands, address modification node, the control input of which is connected to the control input of the device, the outputs of the main and auxiliary firmware memory blocks are connected respectively to the inputs of the main microcommand register and the additional microcommand register, the outputs of three groups of elements AND through the first group of elements OR and the first address register is connected to the input of the microprogram memory main unit, the first inputs of the first group of elements are AND connected to the output of the operation code register first commands, the second inputs - with the first clock of the register of additional dummy microcommands, the first inputs of the second group of PI elements are connected to the output of the operation code register of the second command, the second inputs to the second register output of the additional microcommands, the first inputs of the third And group of elements And are connected to the first register output the main microcommands, and the second and third inputs through the first and second groups of elements are NOT connected respectively to the first and second outputs of the additional microcommand register, the outputs of the fourth and fifth groups n PI elements through the serially connected second group of elements OR and the second address register are connected to the input of the additional microprogram unit, the first inputs of the fourth group of elements I are connected to the second output of the main microcommand register, the second inputs to the third output of the additional microcommand register, the first inputs of of that group of elements I are connected via the address modification node to the fourth output of the register of the additional microcommand, the second inputs are NOT connected to the third through the third group of elements tim yield additional microinstruction register. The drawing shows a block diagram of the proposed device. The device contains block 1 of the main firmware memory, register 2 of the main microcommand; block 3 additional firmware memory, register 4 additional microcommands, registers 5, 6 addresses, constants field 7 in the field of the base address 8 of the main microcommand, tact field 9 and field of the base address 10 of the additional microcommand, node 11 modification of the address, inputs 12 of the device, group elements 13, 14, 15, groups of elements NOT 16, 17, 18, groups of elements PI 19, 20, groups of elements OR 21, 22, register 23 of the operation code of the first command and register 24 of the operation code of the second command. The device provides processing of a command system of the type received by the IB computer system by the EC computer. The description of the operation of the device is conveniently performed on the example of executing commands of the RX format of the type of addition with a fixed comma, as the most widely used. All other commands on the processing steps may be reduced to commands of this type (n) by the elongation of the corresponding ethanes by including additional masking cycles or the elimination of some stages. Consider all the processing steps that this command takes in the processor. Performing it takes six CPU cycles. These cycles are called command processing cycles and are denoted by the letter T with the corresponding number: T1 is the command unpacking cycle, i.e., fetching commands from the command buffer and reading address modifiers from the local memory; 12 - address modification clock; TZ-cycle request for operand in operative (buffer) memory; T4 is the tact of sampling operands from local or on-operative memory; T5 - clock cycle for performing operations on operands; T6 is a measure of recording the result in the local memory. Thus, to control the execution of a single command from the microprogram memory block, you need to select a sequence (microprogram) from the microcommand slot. To execute another command, a different microprogram is required from micromanders, etc. Usually, the first microcommand is selected from the microprogram by using the opcode as part of the address of the cell where the first microcommand is stored. To eliminate duplication of the same micro-commands used in different microprograms, the device switches to common micro-commands from different points of the micro-programs that ensure the execution of system commands. Returning to the execution cycles of the operations, transitions to common points in the common firmware for all operations are performed as follows. The microcommand of the first cycle T1 is common to all commands. The number of micro-instructions of the second clock T2 is equal to the number of commands in the system. Thus, the transition from the T1 microcommand to the T2 microcommand occurs according to the operation code. The actions performed in the third cycle are the same for several commands. These commands are combined into a group that has its own code, which is indicated (in the T2 microcommand of this command. Iri transitions from T2 microcommands to TK microcommands, this group code is used as part of the microcommand address. The number of TOR microinstructions is equal to the number of grits. the command system can be divided into 20-25 groups. From several TK micro-commands at the address located in the micro-command base field, a transition is made to one T4 micro-command, since T4 micro-commands are less than TK.

For the selected command system, 15 T4 micro-commands can be distinguished. The action in the fifth cycle depends on the operation code of the system command and therefore, when switching from T4 microcommand to T5, the opcode is used as part of the microcommand address. The number of micro-commands T5 is equal to the number of commands in the system. In commands that require more than one execution cycle, the first T5 micro-command is the beginning of a sequence of several T5 micro-commands. T6 microinstruction is common to all commands.

When three commands are executed in 5-6 processor cycles (with the combined execution of three commands) the short-circuit command will be at the first level of combining, command K2 at the second, and command K1 "at the third level of combining.

To control the execution of these commands, it is necessary to select three sequences of microinstructions or one sequence that controls all three commands that are at different stages of processing.

Difficulties in organizing one sequence arise from the complexity of the organization of transitions in the microprogram, i.e., the difficulty of forming the address of the next microcommand. In the proposed device, these difficulties are eliminated by dividing the control functions between the two memory blocks of the microprograms as follows.

Actions common to all commands that are associated with the execution cycle number are controlled by microcommands of block 3 of the additional firmware memory, and actions dependent on the operation code are controlled by microcommands of block 1 of the main memory of programs, i.e. the sequence The microinstructions for controlling the execution of commands are split into two sequences selected from two synchronously operating blocks 1, 3.

The control functions, depending on the processing steps of the command, are executed by the microcommands of block 3. To control two or three commands, one microcommand is selected that has the features of the cycles of these commands. Control functions dependent on the onerration code are performed by microcommands of block 1.

Microcommands (type M) control the modification of the address of the operand. Microcommands (such as OP) control the operation.

Start-up microcommands (PCs), i.e., those that do not perform any actions other than transitions are used at the entrances and exits of the combined command execution mode to preserve continuity in the work of the microprogram memory.

Proceeding from the above-mentioned isol, to control the execution of three commands, you need to select two sequences of microcommands from blocks 1 and 3.

The separation of control between two sequences of micro-instructions allows simplifying the design of microprogram transitions.

The transition to the next microinstruction in block 3 depends on the number of the command processing cycle. Every two cycles, a new sequence begins, i.e., a sample of micro-instructions that operate on the combined HHbiMi cycles begins. Transitions in block 1 of the main memory of microyrograms on microcommands of type M are made according to the operation code of the command located on the first level of alignment, and on microcommands of the type OP, according to the operation code of the command located on the third level of combination. Transitions in long sequences of microcommands of the OP type occur at the base address, which is located in the field of the executed microcommand. In the structure of the processor sui1stvuyut

additional circuit conditions that define one of the four transition directions.

In order to shorten the processor's cycle time, and therefore increase the speed,

the transition circuit conditions are not taken into account when generating the address. The branch into four directions is performed by splitting the block 1 of the main memory program into four independent modules, which are processed simultaneously at the same base address. The sampling time from the modules is used to analyze the circuit conditions and form the reception signal from the corresponding memory module to the main microcommand register 2.

The organization of transitions in the firmware of the main and additional memory can be traced when selecting two sequences of instructions to control the processing of three commands.

On the first T1 micro-command, the processor exits after completing operations to load system commands into the command buffer.

The PS of block 1 is selected as an "empty command, because the processor has not yet entered the combining mode. The transition from T1 to T2 occurs at the base address, which is from floor 10 through node I, the group of elements P 20 and 1-1LP 22

is applied to register 6. The transition to a microcommand of the type M for the command K1 occurs by filing the operation code of the command K1 located on the first level of combining. The operation code stored on register 23 through the groups of elements AND 13 and SLI 21 is fed to the address register 5. Elementites And 13 are controlled by the T1 iH3 signal of the clock cycle 9 of register 4.

Transition from microcommand M for K1 to

Claims (2)

the PC micro-command occurs at the base address, which from floor 8 of register 2 through the groups of elements AND 15 and OR 21 enters the register 5 of the address. Both the second and third inputs are supplied with the control signals T1 and T4. The transition from microcollections T2 to the combined micro-command T13 occurs on the group code coming from the 7th floor of the register 2 through the groups of elements I 19 and P1LI 22 to the register 6 of the address. The second input of the elements And 19 is given the signal of the sign of the tact T2. The transition from T13 to the combined micro-command T24 occurs at the base address, which through the groups of elements AND 20 and OR 22 enters register 6, as described above, and the transition from PC to M for command K2 occurs using the operation code of command K2, which is now is at the first level of combining, and its code is on register 23. Command K1 is already at the second level of combining, and its opcode is stored in register 24. Forming the address of a microcommand according to the code of the system command located at the first level of combining was described above. The formation of transitions in subsequent microcommands is organized in a similar way to the vysheopodsna. Both blocks 1, 3 of the microprogram memory operate synchronously, generating signals to control the execution of system commands at all stages of processing. Control (1 signals from block 3 of additional g / microprogram memory affect the organization of microprogram transitions and main memory, and the code of a group of commands that are in the microcommand of block I of the main memory microprogram is used for transitions in the microprograms of block 3 additional memory Thus, the device allows the processor to simultaneously process three commands, i.e., it allows for three levels of combining, which significantly increases system performance and increases the efficiency If you use hardware in general, you can reduce the total amount of microprogram memory by 15–20%, i.e., reduce the processor hardware. Formula of the microprogram control device containing groups of elements AND, OR, microprogram memory and additional firmware memory, characterized in that, in order to reduce equipment and command processing time, it contains the first and second address registers, the operation code registers of the first command and the second command, the main registers microcommand and additional microcommand, address modification node, the control input of which is connected to the control input of the device, the outputs of the main and auxiliary microprogram memory blocks are connected respectively to the inputs of the main microcommand register and the additional microcommand register, the outputs of three groups of elements And through the first connected the group of elements Р1ЛИ and the first register of the address are connected to the input of the main firmware memory block, the first inputs of the first group of elements AND are connected with the output of the operation code register of the first command, the second approaches - with the first output of the additional micro-register register, the first inputs of the second group of the I elements are connected to the output of the operation code register of the second command, the second inputs are with the second output of the additional micro-register register, the first inputs of the third group of And elements are connected with the first register output of the main microinstruction, and the second and third inputs through the nerve and second groups of elements are NOT connected to the first and second outputs of the additional microcircuit respectively the mandates, the outputs of the fourth and fifth groups of elements AND are connected in series to the second group of elements OR and the second register |) ad) of the circuit connected to the input of the additional microprogram memory block, the first | inputs of the fourth group of elements AND are connected to the second output of the main register microcommands, the second inputs - with the third output of the register of the additional microcommands, the first inputs of the fifth group of electrical elements And are connected through the address modification node to the fourth output of the register of the additional microcommands, the second inputs through three This group of elements is NOT connected to the third output of the register of the additional microcommand. Sources of information taken into account during the examination: 1- S. Hasson, Firmware Management, vol. 1, 2 M., “Peace, 1973 2. US patent LL 3800293, cl. 340-172.5, 03/26/74.