SU1332328A1 - Processor - Google Patents

Abstract

The invention relates to computing and can be used in the development of high-speed computing systems. The purpose of the invention is to increase the speed of the processor by combining in time the performance of independent operations on half words. The processor contains a block of 4 microinstructions memory, a register of 5 microinstructions, a computational unit 1, a block 11 of memory constants, a block of 20 elements AND, a switch 21 of initial setup, an element OR 22, a multiplexer 19 conditions, a register 13 of the address of microcommand, a block 14 of address memory transitions, two-port 15 transition addresses, a register of 16 external transitions, a mask register 17 and a masking block 18. 1 hp f-ly, 3 ill., 2 tab. With S (L j "

Description

The invention relates to computing and can be used in the development of high-speed computing systems.

The purpose of the invention is to increase the speed of the processor.

Figure 1 shows the block diagram of the processor; figure 2 - structural diagram of the computing unit; on fig.Z - timing processing diagrams in the processor microcommand.

The processor contains a computational unit 1 consisting of two identical operating units 2 and 3, a microinstructions memory unit 4, a microinstructions register 5 containing two identical operating unit control fields 6 and 7, an internal control field 8. The processor also contains an initial setting.

The correspondence between the input pulse and the output bins for the first block of elements is presented in Table. one.

Operational node 2 (H) with (FIG. 2) processor element Riffeire 5b, commutator data, first and second engines 58 and 59, transfer multiplexer, element group

Group of elements And 61 SOD 15 First 40 and Second 41 inputs 62, second 63, third 64, 65, fifth fifth 66 outputs.

The correspondence between the input siggs of the group

mi blocks, field 9 control external-20. 61 is presented in Table 2, with the devices and the address field 10 of the next microcommand, block 11 of the memory of constants, block 12 of the address generation of the microcommand, which includes the register 13 of the microcommand address, which can be executed on the basis of any synchronous O-type triggers and The lower bit of which must have an independent, 14 memory of addresses of the transitions, register 15 of the addresses of the transition, register} 6 external transitions, the register 17 of the microprocessor works the next time.

Execution by any microcom. produced for the same n 25 time, called microcycle Processing microinstructions in a conveyor mode, i.e. following procedures are performed in one microcycle; the implementation of the 30th microinstruction N, which is located in the register of 5 microinstructions, in the unit 1 under the 6th and 7th registers of the microcoma, the address is

 ki, masking unit 18, multi-execution of any microcommand. produced in the same period of time 25, called the microcycle. The processing of microinstructions is performed in a conveyor mode, i.e. The following procedures are performed during one microcycle; implementation of the current microcommand N located on the register of 5 microinstructions in the execution unit 1 under the control of fields 6 and 7 of the register of microcommands; generating the address of the next micro25 command N and sampling the micro-command M from the block 4 of the memory of the micro-commands to the address set at its address — the water of the micro-command address 12, controlled by

plexCop 19 conditions, the first block of elements AND 20, the switchboard 21 of the initial installation, the element OR 22, informational input-output 23, internal data bus 24, outputs 25 for controlling external microcommand register devices, input 26 for the operation code process 40 field 8 for register 5 microinstructions. litter, exit 27 control floor first. Formation of the address of microcommands by the operational node of the register of microinstructions, output 28 of the control field by the second operational node of the register of microcommands, output 29 of the first operational node, output 30 of the second operational node, input 31

45

M may be performed in four different ways.

1. If the microinstruction M is unconditional, then its address arrives without change from the field 10 of the address of the next microcommand of the register 5 microcommands to the register 13 of the address of the microcommand. From there at the right time he

and the transfer output 32 of the first operating unit, the input 33 and the transfer output 34 of the second operating unit.

The first block of elements And contains the first 35, second 36, third 37, fourth 38, fifth 5, 40, seventh 41 inputs and first 42, second 43, third 44, fourth 45, fifth 46, sixth 47, seventh 48, eighth 49, ninth 50, tenth 51, eleventh 52 and twelfth 53 outs.

The processor also contains the input 54 of the initial installation.

The correspondence between the input clock pulses and the output signals for the first block of elements And 20 is presented in Table. one.

Operational node 2 (H) contains (FIG. 2) processor element 55, buffer register 5b, source data switch 57, first and second shifters 58 and 59, transfer signal multiplexer 60, and group 61.

The group of elements And 61 contains the first 40 and second 41 inputs and the first 62, second 63, third 64, fourth 65, fifth fifth 66 outputs.

Correspondence between input and output signgs of a group of elements

. 61 presented in table 2,

The processor works as follows.

The execution of any microcommand is performed in the same period of time, called a microcycle. The processing of microinstructions is performed in a conveyor mode, i.e. The following procedures are performed during one microcycle; implementation of the current microcommand N located on the register 5 micro-commands in the execution unit 1 under the control of fields 6 and 7 of the register of micro-commands; forming the address of the next microcommand N and sampling the microcommand M from block 4 of the memory of microcommands at the address set at its address — the water of the microcommand address 12, under the control of

A floor 8 register 5 microinstructions. . Formation of the microinstruction address

A floor 8 register 5 microinstructions. . Formation of the microinstruction address

M may be performed in four different ways.

1. If the microinstruction M is unconditional, then its address arrives without change from the field 10 of the address of the next microcommand of the register 5 microcommands to the register 13 of the address of the microcommand. From there at the right time he

it is assigned to the address inputs of microcommand memory 4 and held there for the time required to read the microcommand.

2.If the address of the microcommand M is determined by the condition developed

node 2 (W), then this condition enters the chains 29 or 30 through the multiplexer 19 conditions per unit input of the lower bit of the register 13 address

 one

microinstructions to which the address code from field 10 of the microinstructions register is previously sent is the same as in item I. In this case, the address code in field 10 of the microinstructions register contains a low-order bit. If the condition has developed, then the low-order bit of the address in register 13 is set to 1, if not, then it remains in O. Further actions are similar to claim 1.

3.If the address of the microcommand M is determined from the results of calculations of the microcommand L, preceded by N,

at nodes 2 (3), the computed code enters at the end of the preceding microcycle via chains 23 and 24 to the transition address register 15, and from the output of this register in this micro cycle goes to the address inputs of the transition address memory block 14 and is held there for the time required to read the address of the microcommand M, which comes from the outputs of block 14 of the memory of addresses of jumps to the address inputs of the block 4 of memory of microcommands.

4. If the address of the microcommand M is set by other processors of the system, for example, the high level command code must enable the execution of a specific microprogram in this processor, the corresponding code enters through the circuit 26 to the register of 16 external transitions, is masked in block 18 with the current register code 17 masks and, if there is no lock for this code, goes to the address inputs of the block 14 of the addresses of the transition addresses. The further procedure is similar to p.

During the microcycle of execution of the current microcommand, the field 9 controlling external devices of register 5 microcommands across circuit 25 all the signals needed when the processor interacts with other devices of the system, for example, request signals for accessing the shared memory of the system, etc.

Computing unit 1, consisting of two identical nodes 2 and 3, each of which processes a half-word of information, works as follows. Each node contains a processor element 55, which can perform a series of arithmetic and logical operations on the half-word information. Sources to be processed

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information can serve as an internal memory of microprocessor elements

55, a buffer register 56, a constant memory unit 11 connected to the processing element via the internal data bus 24 via the source data switch 57, as well as system devices external to this

To the processor, connected to the processor element 55 via the external data bus 23 via the source data switch 57, the internal memory of the processor element 55, the buffer register can serve as information receivers.

56, the register 15 addresses go through the shifter 58 on the external data bus 23 or through the shifter 59 on the internal data bus 24, and

20 devices of the system external to this processor through the shifter 58 via the external data bus 23. At the same time, Shift 58 and 59 provide fast transfer of any 25 combinations of bytes on the internal and external data buses. The fields 6 and 7 of the control of the operational nodes of the register of 5 microcommands contain all the codes necessary for

30 control the operation of the operating nodes, namely: the code of the elementary operation of the set of processor elements 55; the input transfer code Po and the control code of the multiplexer 60 of the transfer signal; address codes of two sources of information; address code receiver information; shear control code 58 and 59; control code switch 57 source data; code

40 control a group of elements And 61.

Executive unit 1 can process information in two modes: with a full-length word and with half-words. When processing a full size

The 45 words of the field 6 and 7 of the control of the operational blocks of the register of 5 microcommands contain the same information, under the control of which the elementary operation is performed on all sections of the information word. If during the execution of the firmware, processing of independent words is required, the size of which does not exceed half a word, then nodes 2 and 3 perform non-dependent dependent operations on the half words controlled by fields 6 and 7, respectively, containing in this case different information. The performance of the executive unit 1

actually doubles due to maximum utilization of its equipment.

Let us consider the work of the proposed processor on the example of performing two independent operations on half-words of information under the control of one microcommand.

The processor is started up via the inputs 54 of the initial installation as follows. The address inputs of the micro-command memory block 4 receives the address of the micro-command through the first data inputs of the initial installation switch 21. Read the micro-command from the micro-memory memory block 4 through the OR 22 element and is set to 1 bit of the register 16 corresponding to the address code of the first micro-command of the called microprogram . At the same time, sync pulses start to enter the inputs 35-4-J. The signals from the inputs of the initial setup are removed when the start microcommand is rewritten to the register of 5 microcommands. Here, the initial switch 21 switches to receive information on the second data inputs. The start microinstruction polls the register of 16 external transitions and, through block 18 and block 14 of the memory of the addresses of the transitions (sync inputs 48 and 49 respectively), forms the address of the first microcommand N of the called microprocessorgram, which is fed to the address inputs of the block 4 of the memory of microcommands. Then, the microinstructions N are read from the microcommand memory block 4 and are extinguished into the register of 5 microcommands (synchronization inputs 51 and 42, respectively).

In this example, the microinstruction M is unconditional, i.e. the address of the next micro-command) M is set in the field 10 of the register of 5 micro-commands, from where it is transmitted to the register of the micro-command address 13 under the control of the synchronous input 43. Then, under the control of the synchronous input 50, it enters the address of the micro-command through the second data inputs of the initial installation switch 21, the micro-reading of the micro-command is allowed through the element OR 22 and under the control of the sync-input 51 reads the following micro-command M from block 4. All these procedures

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performed under control of a register 8 microcommand field 8.

In parallel, the following actions are performed in the computing unit 1 under the control of fields 6 and 7 of register 5 of micro-instructions. In operational node 2, processing the lower half-word of information 5 under control

10 half 6 register 5 micro-commands

(circuits 27) two operands are read from the internal memory of the microprocessor elements 55 and arithmetic addition is performed in the ALU (blocks 55 and

15 60, synchronous input 63). The result appears on the D-outputs of the processor elements 55 and through the shifter 58 under the control of the synchronous input 65 enters the outputs 23, from where it can

20 to be recorded in external information receivers under control of the corresponding signals at the outputs of the field 9 of the register 5 micro-commands (outputs 25). In operational node 3, processing the half word, under the control of field 7 of microcommand register 5 (circuit 28), the first operand from buffer register 56 is read through circuit 24 through switch 57

30 source data to the D-inputs of the processor elements 55 (sync-input 62); at the same time, the second operand is read from the internal memory of the processor element 55; in the ALU is performed

35 logical multiplication operation; the result of the operation is recorded in the internal memory of the processor elements (blocks 55 and 60, synchronous input 63).

five

0

five

Claims (2)

1. A processor containing a micro-command memory block, a micro-command address generation unit, a micro-command register, a computing unit, the output of the micro-command memory block connected to the micro-command register information input, the output of the external control field of the processor connected to the external control output of the processor, which differs from in order to increase the processor speed, it contains a memory block, constants, AND block, initial setup switch, and OR element, and microinstruction address of conditions comprises a multiplexer, 7 microcommand address register, jump address memory block, jump address register, outer jump register, mask register, masking block, and the computing block contains the first and second operational nodes, with the outputs of the first and second fields of microoperations connected respectively to the operation code inputs of the first and second operating nodes, the first information inputs and outputs of which are combined and connected to the first information input of the register of the address of the pereod and with the information input / output of the processor ,, senior bit the information input of the external transition register, the first information input and the control input of the initial setup switch and the first input of the OR element are combined and connected to the initial installation input of the processor, the processor command code input is connected to the other bits of the external conversion register information input, the output of which is connected with the first information input of the masking unit, the second information input of which is connected to the output of the mask register, the information inputs of the mask register, the address inputs and the input control of reading the memory block of constants, control input of the condition multiplexer, control input of the memory block of the jump addresses, control input of the third state of the jump address register and the first to the twelfth inputs of the AND block of the elements are combined and connected to the outputs of the control field of the internal microcommand register , the output field of the address of the next microcommand, which is connected to the information input of the microcommand address register, the output of which is connected to the output of the branch address memory and with the second input The setting input of the initial setup switch, the output of which is connected to the address of the microcommand memory block address, the read control input of which is connected to the output of the OR element, the output of the masking unit is connected to the output of the transition address register and the address input of the transition address memory block, the outputs of the first and second operational nodes are combined and connected to the output of the memory block of constants and one ten 15 25 20 332328о the second information input of the register of addresses of the transitions, the outputs of the logical conditions of the first and second operating nodes are connected respectively to the first and second information inputs of the conditions multiplexer, the output of which is connected to the input of the installation of the micro-command address in the low-order I register, the first synchronous input of the processor and the second operating nodes and the thirteenth input of the block And; the second synchronization input of the processor is connected to the second synchronization input of the first and second operations with the fourteenth input of the AND block, the third synchronous input of the processor is connected to the fifteenth and sixteenth inputs of the AND block, the fourth synchronized input of the processor is connected from the seventeenth to the eleventh inputs, and the fifth synchronous input of the processor is connected from the twentieth to the twenty second inputs of the AND input block , the sixth and seventh sync-inputs of the processor are connected respectively to the twenty-third and twenty-fourth inputs of the block of elements And, the first to the twelfth outputs of which are connected respectively to the syncro Iedes of the register of microinstructions, the register of the address of the microcommand, the register of the external transition, the register of the mask, the multiplexer of conditions, with the control inputs of the third state of the register of the addresses of the transitions, the masking unit, the memory of the addresses of the transitions, the register of the address of the microcommand, the memory of the microcommands With the synchronization address registration register of the address of transitions, the output of the transfer attribute of the second operational node is connected to the input of the transfer attribute of the second operational node, the output of the transfer attribute of which is connected to the output transfer characteristic of the MSB word processor, the transfer characteristic in the input significant bit of a word processor connected to the input of the first feature operational unit of transfer. 2. The processor according to claim 1, which is composed of 55 processor elements, a group of elements AND, a buffer register, a transfer signal multiplexer, an initial data switch, first and second shifters, the first information thirty 35 40 45 50 the input-output of the node is connected to the output of the first shifter and the first information input of the source data switch; the second information input-output of the node is connected to the outputs of the second shift and buffer register and to the second information input of the input data switch; the element is connected to the same output of the node, the input of the micro-operation code and the input of the register number of the processor element, the control inputs of the first and second shifters and the source data switch, the control input and the first The information multiplexer input of the transfer signal and the first to the fifth inputs of the elements AND groups are combined and connected to the input of the operation opcode of the node, the output switch of the source data is connected to the information inputs of the buffer register and the processor element, the information output of which is connected to the information inputs of the first and the second shifters, the transfer input of the node is connected to the second information input of the multiplexer transfer signal, the output of which is connected to the transfer input of the processor element, the output peren the wasp of which is connected to the transfer output of the node, the first synchronized input of which is connected to the sixth inputs of elements AND of the group, from the seventh to tenth inputs of which are connected to the second synchronous input of the node, the outputs from the first to fifth elements of the group And are connected respectively but with the control input of the third state of the buffer register, with the synchronous input of the processor element and the synchronous input of the second and first shifters and the synchronous input of the buffer register.