SU1168937A1 - Microprogram device for controlling and debugging processor microprograms - Google Patents

Abstract

FIRMWARE CONTROL AND DECELATION MICROPROGRAMM OF THE PROCESSOR, containing the microprogram address register, microinstructions memory block, decoder, clock generator, initial address register, first and second address switches, two elements And, and the register output of the microprogram address is connected to the output address register, the first and second address switches, two elements to the input of the microinstructions memory block, the first and second outputs of which are connected respectively to the input of the decoder and to the first information inputs of the commutators; a, the second information inputs of which are connected to the third output of the microinstructions memory block, the fourth output of which is connected to the third information inputs of the address switches, the fourth information inputs of which are connected to the external demand bus, and the outputs are connected respectively to the first information inputs of the firmware address register and the initial register addresses whose synchronization inputs are connected respectively to the outputs of the first and second elements AND, the first inputs of which are connected to the output of clock pulse generator, the control inputs of the address switches are connected to the external bus, characterized in that, in order to reduce hardware costs for debugging microprograms, a trigger, a micro-command counter, two branch registers, two comparison circuits, a switch switch, four elements are entered into it OR, the third element is AND, the first and second outputs of the decoder are connected respectively to the first inputs of the third and fourth elements OR, the outputs of which are connected to the second inputs of the first and, respectively, And, the third output of the decoder is connected to a single trigger input, the inverse output of which is connected to the second input of the fourth OR element, controlling the Y input of the firmware address register and the first input of the third And element, the second input and output of which are connected respectively to you ( L the clock pulse and the counting input of the microinstructor counter, the information input and output of which are connected respectively to the fourth output of the decoder and the control input of the feature switch, the first The information input is connected to the output of the first OR element, the first input of which is connected to the output of the first comparison circuit, the first input of which is connected to the output of the first branch register, the information input of which is connected to the external request bus, the installation input of the microcommand counter and information inputs the first and second branch registers, the control input of the first branch register is connected to the fifth output of the decoder, the sixth output of which is connected to the control input of the second register branch, the output of which is connected to the first input of the second comparison circuit, the second input of which is connected to the second input of the first comparison circuit and the output of the microprogram address register register, the output of the second comparison circuit is connected to the second input of the first OR element, the second information input and output of the switch

Description

yen respectively with the fifth output of the microinstructions memory block and the first input of the second OR element, the second input of which is connected to the initial setup input of the device and the reset input register of the starting address, the output of the second OR input is connected to the zero input of the trigger, the forward output of which is connected to the second the input of the third OR element and the control care of the register of the start address, the sixth output of the microcommand memory block, is the control output of the device.

one

The invention relates to computing and can be used to create specialized and universal microprogrammable processors.

Logic and functional modeling systems are known for debugging algorithms and the logic of microprogram function 1.

The disadvantage of these modeling systems is the use of large computational masses with high machine costs and, as a rule, batch processing, which increases the cost of debugging and increases its time. In addition, the debug confidence level is low.

The closest to the invention is a microprocessor processor containing a microprogram address register, a microinstruction storage unit, a decoder, a pulse generator, a starting address register, two address switches, two AND elements, the output of the microprogram address register being combined with the output of the initial address register and connected to the input microinstructions storage unit, the first and second outputs of which are connected respectively to the input of the decoder and to the first inputs of the address switches, the second inputs of which are connected the third output of the microinstructor storage unit, the fourth output of which is connected to the third inputs of the address switches, the fourth inputs of which are connected to the external bus, and the outputs are connected respectively to the first input of the microprogram address register and the first input of the initial address register, the second inputs of which are connected respectively to the outputs the second and first elements And, the first inputs of which are connected to the output of the pulse generator, the fifth inputs of the address switches are connected to the external condition bus 2.

A disadvantage of the known device is the use, in addition to special software, of additional equipment, which is not actually used.

when running processor working firmware.

The aim of the invention is to reduce hardware costs for debugging firmware.

The goal is achieved by the fact that the processor firmware control and debugging software contains a firmware address register, a microinstructor memory, a decoder, a clock generator, a start address register, the first and second address switches, two elements, and the output of the microprogram address register combined with the output of the register of the initial address and connected to the input of the microinstructions memory block, the first and second outputs of which are connected respectively to the input of the descrambler and from the first mi information inputs of the address switches, the second information inputs of which are connected to the third input of the microinstructions memory block, the fourth output of which is connected to the third information inputs of the address switches, the fourth information inputs of which are connected to the external request bus, and OUT; С1ы are connected respectively to the first information inputs firmware address register and

0 of the initial address register, the synchronization inputs of which are connected respectively to the outputs of the first and second elements AND, the first inputs of which are connected to the output of the clock generator, the control inputs of the address switches are connected to

5 by the bus of external conditions, a trigger, a micro-command counter, two branch registers, two comparison circuits, a feature switch, four OR elements, a third AND element, with the first and second outputs

0 decoder connected respectively with the first inputs of the third and fourth elements OR, the outputs of which are connected to the second inputs of the first and second elements, respectively, the third output of the decoder - with a single trigger input, the first output of which is connected to the second

the input of the fourth element OR, the control input of the microprogram address register and the first input of the third element AND, the second input and output of which are connected respectively to the output of the clock generator and the counting input of the micro-command counter, the information input and output of which are connected respectively to the fourth output of the decoder and the control the input of the feature switch, the first information input of which is connected to the output of the first OR element, the first input of which is connected to the output of the first comparison circuit, the first input of which is connected to the output of the first branch register, the information input of which is connected to the external query bus, the installation input of the microinstructor counter and the information input of the second branch register, the control input of the first branch register connected to the fifth output of the decoder, the sixth output of which is connected to the control the input of the second branch register, the output of which is connected to the first input of the second comparison circuit, the second input of which is connected to the second input of the first comparison circuit and the output of registration The microprogram address path, the output of the second comparison circuit — with the second input of the first OR element, the second information input and the switch output of the switch — respectively, with the fifth output of the microinstruction memory block and the first input of the second OR element, the second input of which is connected to the input of the initial installation of the device and the reset input of the initial address register, the output of the second OR element - with a zero trigger input, the direct output of which is connected to the second input of the third OR element and the control input of the initial address register, The simple output of the macro storage unit is the control output of the device.

FIG. 1 shows a block diagram of the device; in fig. 2 - time diagrams of the device; in fig. 3 is a block diagram of the device operation in the configuration mode.

The device contains a register of 1 firmware address, a block of 2 microinstructions memory, a decipher 3, a generator of 4 clocks, a register 5 of the initial address, the first 6 and second 7 switches of the address, the first 9 and second 8 elements And, the trigger 10, the counter of 11 micro instructions, the first 12 and second 13 branch registers, first 14 and second 15 comparison schemes, first 16 second 17, third 18 and fourth 19 elements OR, third element AND 20, switch 21 signs, bus 22 external requests, initial installation input 23, bus 24 external conditions

The device operates in two modes, the setup mode and the operating firmware execution mode. In the initial state, the initial setup signal from input 23 arrives at the third input of register 5 of the starting address and through the first input of the second element OR 17 to the zero input of trigger 10, the latter is set to the zero state, and in register 5 of the initial address is set nullP

 The second address is the starting address of the receive firmware and the implementation of the setup function. A single enable signal from the direct output of the trigger 10 is supplied through the third element OR 18 to the second input of the first element AND 8, ensuring the arrival of clock pulses from the output of the generator 4 pulses through the first element 8 to the second input, which is synchronizing, register 5 of the initial address. In addition, a single signal from the direct output

0 trigger 10 enters the fourth input of register 5, transferring its output from the third state (high impedance) to the open state, i.e. connecting the output of register 5 to the input of block 2. Due to this, the device is switched to the setting mode. In this mode, register 5 addresses block 2 of the microinstructions memory, ensuring that microinstructions of the adjustment firmware are read from it. The decipheror 3 of the corresponding micro-command fields generates control signals that ensure the execution of micro-operations in the setup mode. The decoder 3 decodes the fields of the microcommands that control the device blocks in the second mode as well.

To form the address of the next microcommand, the address code from the second output of the microcommand memory block 2 is fed through the first input of the second switch 7 address to the first input of register 5 of the initial address and is written to it when a sync pulse arrives at the second input of register 5 (diagrams A, B, B , G, Fig. 3). Consider the operation of the device in the setup mode using the example of setting up the device to perform the function of executing the work program from the starting address by N steps. The first parameter received from the external request bus 22 and the address of the microprogram implementing the required tuning function is loaded via control code 10 received from the fourth output of the microcommand memory block 2 via the second address switch 7 into the initial address register 5. This selects the desired firmware, which will be

 interpret subsequent parameters coming from the external bus 22. In this case, the second parameter, which is the number of steps N, comes from the bus 22 external requests to the third input of the microcommand counter 11, which is written to by the control signal received from the fourth the output of the decoder 3 to the second input of the counter 11 microinstructions. The third parameter, coming from the external demand bus 22 to the third inputs of the first and second switches 6 and 7, is transmitted via the first address switch 6 to the first input of register 1 of the firmware address. In this case, from the second output of the decoder 3, a microprogrammed control signal is output, which arrives at the first input of the element OR 19.

When applying this signal, one clock pulse passes through the element AND 9 to the second input of register 1, ensuring the loading of the specified address into it. After that, the address of the initialization firmware should be loaded into register 5, which provides loading of the newly arriving parameter as the code of the tuning function, which may be required when executing the next tuning function during the program debugging process. At the end of each setup firmware, the program enters the execution mode of the working microcommand. This is ensured by the fact that at the end of the microprogramme of adjustment from the third output of the decoder 3, the control signal arrives at the first input of the trigger 10 and converts it to a single state (diagrams B and D, Fig. 3).

Allowing a single signal from the first output of the trigger 10, coming through elemegg OR 19 to the second input of the element And 9, ensures the arrival of a sequence of N clock pulses from generator 4 to the control input of the register 1 of the firmware address. Thereby, the device is switched to the execution mode of the N chips of the working microprogram (diagrams E and G) of FIG. 3).

Depending on the previously selected setting function, the working firmware can be executed in the following mode: running the working firmware from the desired address, starting the firmware from the desired or current address to the breakpoints, running the firmware in a certain number of steps from the specified or from current address. The operating program execution mode is provided by applying a resolution signal from the second output of the trigger 10 to the third input of register 1 of the firmware address, connecting its output to the input of the microcommand storage unit 2. At the same time, applying a prohibitory (zero) signal from the inverse output of trigger 10 to the fourth input of register 5 disables the output of register 5 of the starting address from block 2 of the memory of microcommands. The addressing of the microinstructions memory block 2 is performed from the output of register 1 of the firmware address.

The decoder 3 generates control signals for performing microoperations, the codes of which are written in the corresponding fields of each microcommand read from the first output of block 2 of microcommand memory. Address generation is performed by applying the address code from the second output of the block

2 through the first input of the first switch 6 to the first input of the register I of the firmware address. The firmware is executed without stopping or to the corresponding breakpoint. The execution of the firmware for a certain number of steps is ensured by the presence in the device of the counter 11 micro-commands, which, when each micro-command is executed, subtracts one from the parameter defined in the configuration mode.

0 In the mode of execution of the working firmware, the first input of the micro-command counter 11 receives a clock pulse from the output of the I 20 element. The latter ensures the transmission of the clock pulses from the generator 4 output, since its first input receives the enabling signal from the inverted output of the trigger 10. When the counter value of the 11 micro-commands becomes equal to zero, a control signal is generated at its output, which is fed to the first input

Q switch 21 features. In accordance with the feature code coming from a separate field of a microcommand from the fifth output of block 2 to the third input of the switch 21, the control signal from the output of the switch 21 (chart 3, Fig. 3) goes to the first input of the OR element 17 and then to zero trigger input 10, stop the execution of the working firmware and transfer the device to the configuration mode. The micro-command counter 11, in addition, can be used to implement step-by-step execution of the working firmware.

Similarly, when executing work programs to the stopping points stored in

The 5 registers 12 and 13 of the branching, the comparison circuits 14 and 15, ensure that the breakpoints match the current firmware address configured in register 1 of the micro-command address. In the case of coincidence, the control signal from the output of any of the comparison circuits 14 and 15 through the OR element 16, the switch 21 features, the OR element 17 goes to the zero input of the trigger 10, converting it to the zero state, and the device to the configuration mode. After entering the configuration mode, the state of the memory elements of the processor controlled by the proposed device can be displayed for indication and change using the appropriate firmware settings.

Using the proposed device, the method of performing a set of functions for displaying the internal state of the processor elements, starting and running the working firmware for the required number of steps to breakpoints is simplified. Such a set of functions corresponds to a dynamic debugging firmware package, whereby a reduction in the firmware debugging time is achieved. When using the proposed device, there is no need for additional complex hardware costs in the form of debugging systems, auxiliary consoles, logic analyzers, the excessive complexity of which is due to the focus on debugging not only software, but also hardware.

FIG. 7

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Claims (1)

FIRMWARE CONTROL AND DEBUGGING PROCESSOR FIRMWARE microprogram containing microprogram address register, micro memory instruction block, decoder, clock pulse generator, start address register, first and second address switches, two AND elements, the output of the firmware address register and combined with the output of the start address register the input of the memory block of microcommands, the first and second outputs of which are connected respectively to the input of the decoder and to the first information inputs of the address switches, second its information inputs are connected to the third output of the micro-command memory block, the fourth output of which is connected to the third information inputs of the address switches, the fourth information inputs of which are connected to the external request bus, and the outputs are connected respectively to the first information inputs of the microprogram address register and the start address register, inputs synchronization which are connected respectively with the outputs of the first and second elements-AND, the first inputs of which are connected to the output of the clock generator output pulses, the control inputs of the address switches are connected to the external environment bus, characterized in that, in order to reduce hardware costs for debugging microprograms, a trigger, a micro-counter, two branch registers, two comparison circuits, a feature switch, four elements are introduced into it OR, the third element AND, and the first and second outputs of the decoder are connected respectively to the first inputs of the third and fourth elements OR, the outputs of which are connected to the second inputs of the first and second elements I. tr This decoder output is connected to a single trigger input, the inverse output of which is connected to the second input of the fourth OR element, which controls the input of the firmware address register and the first input of the third AND element, the second input and output of which are connected respectively to the output of the clock pulse generator and the counting input of the micro instruction counter, the information input and output of which are connected respectively to the fourth output of the decoder and the control input of the feature switch, the first information input of which is connected to the output of the first OR element, the first input of which is connected to the output of the first comparison circuit, the first input of which is connected to the output of the first branch register, the information input of which is connected to the external request bus, the setup input of the micro-counter and the information inputs of the first and second branch registers, controlling the input of the first branch register is connected to the fifth output of the decoder, the sixth output of which is connected to the control input of the second branch register, the output of which is connected to the first input ohm of the second comparison circuit, the second input of which is connected to the second input of the first comparison circuit and the output of the firmware address register, the output of the second comparison circuit is connected to the second input of the first OR element, the second information input and the output of the switch of the sign of connection (Yen, respectively, with the fifth output of the memory unit microcommands and the first input of the second OR element, the second input of which is connected to the input of the initial installation of the device and the input of resetting the register of the starting address, the output of the second OR element is connected to zero the trigger input, the direct output of which is connected to the second input of the third OR element and the control input of the start address register, the sixth output of the micro-command memory block is the control output of the device.