SU1254495A1 - Interface for linking central processor unit with group of arithmetic processor units - Google Patents

Abstract

The invention relates to computing and can be used in the construction of high-performance computing systems as a means to interface the central processor with arithmetic processors. The aim of the invention is to increase the speed of a computing system by providing switching of computing operations from software to hardware and vice versa. The device contains a control unit, a return register in the program, an operation code register, a diagnostic transition register, an address register, a number register, a memory block, a comparison node, a decoder, two triggers, two OR elements, two I. Elements. -ly, 12 ill., Table. § (L

Description

The invention relates to computing technology and can be used in the construction of high-performance computing systems (VS) as a means for interfacing the central processing unit (CPU) with arithmetic processors (AP).

The purpose of the invention is to increase the speed of the aircraft operation by ensuring the overflow of computational operations from software to hardware and vice versa.

FIG. 1 is a block diagram of the device; in fig. 2 is a block diagram of a CPU; in fig. 3 is a block diagram of the AP; in fig. 4 is a diagram of a memory block (W1); FIG. 5 is a block diagram of an address register; in fig. 6 is a block diagram of the operation code register; in fig. 7 is a block diagram of the register of return to the program} in FIG. 8 is a block diagram of a diagnostic transition register; in fig. 9 is a block diagram of a comparison node; in fig. 10 is a block diagram of the number register; FIG. 11 is a block diagram of an interprogrammed control unit; . 12 is a timing diagram of the transition to the main program ... The device contains (fnig.1) CPU 1, AP 2, register 3 return to the program memory block 4, register 5 of the operation code, register 6 of the diagnostic transition, comparison node 7, register 8 addresses, number register 9, decoder 10 first AND 11 element, first trigger 12, second trigger 13, first OR element 14, second OR element 15 second AND 16 element, firmware control block 17, address bus 18, data bus 19, output Read CPU (Thu. CPU) 20, output Confirmation of capture of the CPU (PZh CPU) 21, and code Record CPU (Zpv CPU) 22, input Sat oc CPU (Sat CPU) 23, input request input capture CPU CPU Willingness

KZhCP) 24,

(GC. TsP) 25, output Malfunction AP (NS.AP) 26, input Sampling crystal AP (VC AL) 27, input Read AP (Pt.PA) 28, exit End of the operation of the AP (KVO AI) 29, input Record AP (Zp / AP) 30, input Command / data AP (K / D AP) 31, input Launch AP 32, input Permit selection of external program memory (RVV PC) 33 input Read external program memory (Thu runway) 34 , entry Record of external program memory (Zp, WFP) 35.

CPU 1 (Fig. 1) contains buffer 36 a, tres, buffer 37 data, block 38 re

about

the gistras, the internal highway 39, the arithmetic logic unit 40, the control unit 41, the exchange control unit 42, the synchronization unit 43. The device used CPU series K580 IC80, KO.348.393.TU.

AP 2 (FIG. 3) contains an operation unit 44, an adder 45, a control unit 46, a first combinational circuit 47, a fault trigger 48, an error counter 49, a second combinational circuit 50.

The memory unit 4 (FIG. 4) contains the first switch 51, the second switch 52, the operational memory. the device (RAM) 53, the bus driver 54, the element NOT 55, the group of elements AND 56, the element OR 57, the associative storage device 0 (ABC) 58, consisting of the decoder 59, the registers 60, the elements 61 of the comparison, the encoder 62.

The address register 8 (FIG. S) contains the first delay element 63, the element 5 AND 64, the second delay element 65, the third delay element 66, the first counter 67, the second counter 68, the third counter 69, the fourth counter 70, the first buffer circuit 71, the second buffer circuit 72, the fourth delay element 73, the fifth delay element 74, the AND-OR 75 element.

Operation code register 5 (FIG. 6) contains a NOT element 76, a delay element 77, an AND element 78, a multi-mode buffer register (MBR) 79, for example, type K589IR12, consisting of AND element 80, AND-OR element 81, OR element 82, trigger groups 83, element groups AND 84.

The address register 3 (Fig. 7) contains the first element AND 85, the first element OR 86, the second element AND 87, the second element OR 88, the element NOT 89, the trigger 90, the MBR 91, the third element And 92, the MBR 91 is made similar to the MBR 79 (Fig. 6).

The diagnostic transition register 6 (FIG. 8) contains a delay element 93, the first element is NOT 94, the element is AND 95, the second element is NOT 96, the third element is NOT 97, the first MBR 98, the second MBR 99, the third MBR 100. The MBR 98- 100 are made similar to the MBR 79 (Fig. 6).

55 Comparison node 7 (FIG. 9) contains a group of elements AND 101, an element OR 102, a trigger 103, a delay element 104.

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Register 9 numbers (Fig. 10) contains the element 105 delay, the element And 106, register 107.

The CU 17 (Fig. 11) contains a memory of 108 micro-instructions, a register of 109 micro-instructions, a counter of 110 micro-commands, an AND-OR element 111, a delay element 112, the first element AND 113, a counter 114, a decoder 115, a fourth and fifth elements And 116, a trigger 117, the generator 118 pulses, the seventh and eighth elements And 119, the second trigger 120, the second, third, the test elements And 121 - 123, the element SH. 124, element NOT 125.

The construction of the device is based on two principles: the principle of modular representation of BS software and hardware and the principle of interchangeability of software and hardware modules. A module (software or hardware) is an object that has functional completeness, which implements a finite number of functions, respectively, in a software or hardware way.

In the device, an AL is used as a hardware module, which, in the case of the implementation of several computational operations, acts as a set

Functional hardware module. In this case, in general, to process information, the UA must receive the input data of an operation and the operation code (command) in accordance with the requirements of the algorithm for solving the problem. At the end of the calculation process, the UA outputs the processed data as results.

Modular programming, in addition to reducing the time spent on software development, makes it more concise and comprehensible, allowing you to encode and test them independently of other software modules. In this case, all program modules are designed in the form of subroutines representing a single mechanism to which program control is transferred and from which control is returned to the program. In addition, the use of subroutines significantly reduces the volume of program memory due to the possibility of repeated access to the once written and debugged subprogramme: there is no need to perform multiple duplications in the main program. As for the UA, the subroutine should get a non- (

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which input data and issue results.

The question of where to place the data and how to transfer it to the subroutine is very important for the organization of the computational process. Therefore, consider the various data transfer methods developed for the microprocessor system (MPS) between the main program and the subroutine. To do this, we divide all existing methods for transferring data into two groups, depending on their location with respect to the CPU ratio; inside and outside of the CPU. The first group includes methods for transmitting data using internal CPU registers or a special stack embedded inside the CPU. The second group consists of ways to exchange data via the external memory of the runway program. It should be noted that, in general, loading data into internal registers or a special CPU stack precedes their storage in the runway. The second group of data transfer methods is often used to organize subroutines. Therefore, it can be considered that the most common data transmission methods are transmission methods via runways. This device uses only data transfer methods, in which data can be accessed by all system processing modules (this device is used in the MMS, in which there is only the second group of data transfer methods to subroutines).

The subprogram execution is initiated by specifying its name in a subprogram call command. subroutines (a label in the assembler string field) is associated with the address of the memory cell in which the first byte of the subprogram command is located and to which control is transferred from the dial peer. Then the commands of the subroutine are executed in the usual way, and upon its completion. control is transferred to the call point. When the subroutine call command is executed, the current contents of the program counter of the CPU are loaded onto the stack, and the transition address is loaded into the program counter. The contents of the program counter are transferred via the address bus to the memory, and the read signal selects the first byte.

instructions (code of the first operation of the subroutine), which takes control of the process, after which the first instruction of the subroutine starts, then the second, and so on. The final command of each subroutine is a one-byte return command that retrieves the return address from the stack and passes it to the program counter. Next, the command is executed, which is found in the calling program immediately after the call command of the subprogram.

The appearance of the AP in the IPU is caused by a tendency to increase the productivity of the aircraft. Since universal microprocessors (including the K580 series) are not very effective for performing complex mathematical operations (such as

It is built in the form of a memory catalog based on an associative memory device (CAM) and operates in two modes: settings and working.

J In setup mode, block 4 generates a so-called switching matrix from a descriptor of hardware-implemented functions and informational control words AP 2.

10 At the same time, the registers 60 of the ABC 58 write the labels of the subroutines having the equivalent hardware implementation of the AP 2, and the cells of the RAM 53 contain the information needed by the AL 2 for processing

5 operations and swap operations

. (Fig. 18): the initial addresses of the input data, the initial addresses of the encoding data, the opcode, the number of the AP, the length of the word being processed (for example.

multiply, divide, erect (20 bytes) operations, the length of the result. Writing to the power of finding the logarithm is done under the control of CPU 1,

computations of trigonometric functions, etc.), which they perform programmatically and spend iiHoro time, then an increase in the productivity and computational power of universal microprocessors is achieved by including them in conjunction with them. The AP focuses on performing complex mathematical operations. Typically, the UAs are connected to the CPU as additional peripheral devices, the operation of which is initiated and controlled by the CPU.

This device, as part of the MPS, intercepts and transmits to the AP 2 those arithmetic operations that the AP 2 is aimed at effectively performing and which are implemented in a uniprocessor system by software, with the subsequent transfer of the input data to the AP 2 and the results to the desired area of the program memory. . In the event of a malfunction of the AP 2 performing the function, the device transfers the operations of the failed AP 2 to software. Moreover, in the future, access to this AP 2 is not made until its malfunction is eliminated.

In order to clarify the principle of operation of the device, it is necessary to first consider the organization of its constituent units. Central unit. The device is a memory block 4 (FIG. 4) for determining the configuration of the IPU. Block 4 is built in the form of a memory directory based on an associative memory device (CAM) and operates in two modes: settings and working.

J In the setup mode, block 4 generates the so-called switching matrix from the descriptor of hardware-implemented functions and the information control words AP 2.

10 At the same time, the registers 60 of the ABC 58 write the labels of subroutines having the equivalent implementation in hardware version of AP 2, and the cells of RAM 53 contain the information needed by AL 2 for processing operations and exchanging in the runway

. (Fig. 18): the initial addresses of the input data, the initial addresses of the decoded data, the opcode, the number of the AP, the length of the processed word (for example.

and in such a way that there is a one-to-one correspondence between the descriptor (label) of the subprogram placed in the k-th register 60 of the CAM 58, and the content of the k-th cell of the RAM 53. In a certain way, the width of the fields of the RAM 53 changes, as well as the volume AZS 58, you can get as the required number of hardware-implemented functions and AP 2 included in the IPU, and the required length of the processed word.

The entry in the k-th register 60 and the k-th cell of the RAM 53 is made as follows.

On the address bus 18, the CPU 1 sets the addresses corresponding to the th register 60 and the th cell of the RAM 53. The data bus 19 transfers the labels of the kth subroutine and the initial address of the input data, the starting address of the output data, the code of the kth operation , AP number, the length of the input word and the length of the output word. The output signal of the GPU 22 switches the first switch 51, the second switch 52 and the bus driver 54 to the setting mode. The address bus 18 commutes with the decoder 59 and the address inputs of the RAM 53, the data bus 19 commutes with the registers 60 and the information inputs / outputs of the RAM 53. With the same signal from the output of the GPU 22, the kth subroutine is written to the th register 60 (depgafrator 59 opens the inputs of k-th register 60) and the corresponding information in k-th

cell RAM 53 (the signal from the output Zp. CPU 22 is fed to the inputs Record and Sampling resolution of RAM 53). By continuing to overwrite the switching matrix, it is possible to reorient the device to process the required number of application programs.

The customization process is greatly simplified due to the requirements for the design specifications for each subprogram. These specifications indicate where the data is (the input data addresses) processed by the subroutine; where will

the results (addresses of output fs 2 MHz), sufficient for detecting obdannyh), obtained when executing subroutines.

In addition, many assemblers have special tools that facilitate the work of the programmer with subprograms. The assembler makes it possible to broadcast the subroutine separately. It then collects information about all references to the subroutine in the main program and transfers it to a special loader program that replaces these references with addresses.

In the operating mode, the second switch 52 connects the address bus 18 to the information inputs of the registers 60 and the first inputs (inputs A) of the comparison elements 61. Encoder Outputs 6. in operation open. Since the second inputs (inputs B) of the comparison elements 61 are connected to the outputs of registers 60, when the first inputs of the comparison elements 61 receive a code address equal to the contents of the k-th register 60, the output of the -th comparison element 61 appears the signal that arrives at the direct input of one of the elements And 56. If at the inverse input of this same k-th element And 56 there is no signal He. AP 26, then a signal from a to-that comparison circuit 61 switches an element of a ШШ 57 to a single state (a start signal). The signal from the k-th comparison element 61 also goes to one of the inputs of the encoder 62, at the output of which a code appears that corresponds to the address of the k-ram of the RAM 53. The Start signal switches the first switch 51 and the bus driver 54 so that .so that they connect, respectively, the outputs of the encoder 62 with the address inputs of the RAM 53 and the information

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the RAM 53 inputs with outputs of registrars 5, 8 and 9. The same Start signal is fed to the Read and Allow sampling of RAM 53, which results in the selection of K-cell RAM 53, in register 5 - code to -th operation, in register 8 - addresses of input and output data and lengths of words, in register 9 - numbers of AP.

Calculations show that the time during which the address of the runway cell is present on the address 18 bus (for K580, for 1 to 3 clocks equal to 1.5 of the ISS at the clock frequency

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rascheni to the hardware-realized function, giving of a signal on ZZkh input. CPU 24 and sampling the contents of the k-th cell of RAM 53 and registers 5, 8 and 9. Thus, after tuning, block 4 contains a descriptor of hardware-realizable functions and information-control words of AP 2, which, in general, fixes the MPS configuration .

 The remaining units of the device carry the following functional load. The Start signal from the output of the aperture 57 (Fig. 4) opens the inputs of register 5 (Fig. 6) and register 9 (Fig. 10), so that the contents of the flip-flops 83 and the register 107 are reset. Delay elements 77 and 105 have a delay at the time of reset (zeroing) of the triggers 83 and register 107, respectively. Then, the Start signal is fed to the inputs C of the AND-OR element 81 and register 107, respectively, which permits the recording of data on information inputs into the triggers 83 and the register 107. The signal from the CU 17 to the input element NE 76 opens the outputs of register 5, with the result that the content of the latter is fed to the data bus 19. The contents of register 107 (AP number) is fed to the input of the decoder 10.

The Start signal switches the first trigger 12 and the second trigger 13 to one state. At the same time, from the output of the first trigger 12, the signal goes to the input ZZx, CPU 24 and to the control unit 17, and from the output of the second trigger 13 to the input GT} 1DP 25.

During the processing of information in the MPS, this device reveals an appeal to a hardware-implemented function and, before taking control of the system, prepares

return to the program. The organization of the hardware transition to the main program is as follows. The Start signal switches the trigger 90 of register 3 to one state (Fig. 7). The signal from the trigger output 90 is fed to the inverted input of the I 92 element. The direct input of the latter is connected to the MPS output, which controls the resolution of the sample of the runway (usually this is the 15th bit of the address 18 bus). As a result, the runway is blocked. When a signal is output from the output of Th.CCP 20 to the bus 19 dan1x

15 counters 67-70 after sampling their contents. So at every. when accessing the counters, their contents will be increased by one (for the account (, tweeters 67 and 68) or reduced by the command code for exiting the PET subroutine from MEP 91, executed similarly to the IBR 79. The PET command will be reset when the Start signal disappears and the lock is reset Runway - when the signal from P3x output CPU 21,2Q is low (for counters 69 and 70). When the Time Diagram (Fig. 12) is observable, zero counters 69 and 70 have a hardware transition on the outputs signal arrives in the main program. CPU 1 exposes through nt AND-OR 75, on the input there is a single signal at the output of the P3x element I-ShSh 111 BU 17, which stops the access to the PP.

CPU 21 at the beginning of the third cycle of the machine cycle Reading, if the signal to the input ZZh, the CPU 21 arrived in the first clock for 180 not before the rising edge of the second clock pulse, otherwise this signal is PZh. is set in the third cycle of the next machine cycle.

The CAM 58, made on the modern element base, has a very short response time (about 70 ns), which allows 1-3 steps of the first machine cycle of the CPU 1 to perform the necessary actions to prepare the transition to the main program.

A runway lock also occurs when a signal appears at the output of node 7 (Fig. 9). The runway blocking reset is produced by a special signal from the output of the CU 17.

The Start signal arriving at the input of the register 8 (Fig. 5) first zeroes the counters 67-70, and then allows data to be written to them from the output of the bus driver 54 (FIG. 4) using the information inputs of the counters 67-70. The delay element 63 has a delay by resetting (resetting) the counters 67-70. At the same time, the first counter 67 records from the starting address of the input data, to the second counter 68 - the starting address of the output data, to the third counter 69 - the length of the input data, to even 35

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And 74 delays have a delay on the sampling time of the next micro-command from the list of 108 micro-commands (Fig. 11).

When a signal is started, the Start from the output of the element OR 57 to the input of the register 6 (Fig. 8) first clears the contents of the MBC 98 and 99. The delay element has a delay for the resetting (zeroing) time of the MBR 98 and the MBR 99. After that, the Start signal allows record in the MBR 98 and the MBR 99 of the contents of the bus 18 addresses by information inputs. Moreover, the MBR 99 records the contents of the low-order bits (7 - 0) of the address 18 bus, and the MBR 98 records the contents of the higher-order bits (15 - 8) of the address 18 bus 18. The signals from the BU 17 (from the output of the decoder 115) separated in time, open the outputs of the MBR 98-100. In this case, the data of the unconditional transfer command and the address of the transfer (the contents of the ICBM 100, then the ICBM 99, the MBR 98) arrive on the data bus 19. The code for the unconditional jump instruction in the MBR 100 appears when the power to the device is turned on.

The inputs of the node 7 (the inputs of the elements And 101, Fig. 9) are connected to the outputs of the decoder 10 and the outputs He. AP 26 of all AP 2 structures MPS. With

55 signals are available from these blocks on

one of the elements AND 101 at its output appears a signal that through the element OR 102 switches the trigger 45

50

Counter 70 is the length of the output. Upon the appearance of signals from the CU 17 (from the output of the first group of elements 116), a buffer circuit 71 or 72 with three states opens. The contents of the first counter 67 or the second counter 68 is fed to the bus 18 addresses. In the absence of signals from ib 17, the buffer circuits 71 and 72 are in a state of high resistance. Elements 65 and 66 of the delay (with a delay of the time of sampling the contents of the counters 67-70) transmit signals to the counting inputs

counters 67-70 after sampling their contents. Thus, each time the counters are addressed, their contents will be increased by one (for counters 67 and 68) or reduced by one (for counters 69 and 70). When the counters 69 and 70 are equal to zero, the signal arriving through the AND-OR 75 element appears at the outputs of the I-SHSh 111 BU 17 element, than

And 74 delays have a delay on the sampling time of the next micro-command from the list of 108 micro-commands (Fig. 11).

When the signal starts from the output of the element OR 57 to the input of the register 6 (Fig. 8), the contents of the MBR 98 and 99 are zeroed out. The delay element has a delay for the resetting (resetting) of the MBR 98 and the MBR 99. After that, the Start signal allows recording in the MBR 98 and the MBR 99, the contents of the bus 18 addresses the information inputs. Moreover, the MBR 99 records the contents of the low-order bits (7 - 0) of the address 18 bus, and the MBR 98 records the contents of the higher-order bits (15 - 8) of the address 18 bus 18. The signals from the BU 17 (from the output of the decoder 115) separated in time, open the outputs of the MBR 98-100. In this case, the data of the unconditional transfer command and the address of the transfer (the contents of the ICBM 100, then the ICBM 99, the MBR 98) arrive on the data bus 19. The code for the unconditional jump instruction in the MBR 100 appears when the power to the device is turned on.

The inputs of the node 7 (the inputs of the elements And 101, Fig. 9) are connected to the outputs of the decoder 10 and the outputs He. AP 26 of all AP 2 structures MPS. With

the presence of signals from these blocks on

one of the elements AND 101 at its output appears a signal that through the element OR 102 switches the trigger

to

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rep 103 in one state. From the unitary codes (each bit of the last stroke is fed to the inputs of the Sb. CPU 23, register 3, BU 17 and OR 15 element. Delay element 104 delays the signal for at least three clock cycles of the CPU 1 required for resetting the internal registers of CPU 1 (for K580). After that, the signal at the output of flip-flop 103 is reset.

Controls the operation of all units of the device in the active mode control unit 17 (Fig. 11). A push-pull GI 118 is used as a synchronization emitter, the sync signals from which are fed to the MPA blocks after the occurrence of the signal. The trigger is triggered to the single trigger input 117. The same signal is used for the initial setup. ,

setting (zeroing) of the counter 110, C vy- 20 trigger input 117. strokes of elements And 119 clock pulses- If there is a unit at zero distance, the first is received at the input of the register record 109 and elements 116, the second one at element And 123 At the first clock pulse, a record 25 is made. In the zero state of this bit, and issuing control signals from the regular clock, the wiper 109 is delivered to the internal nodes of the control unit and to the device nodes. momentum is added

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units to the contents of counter 110 and sampling of micro-instructions from the memory of 108 micro-instructions. In addition to the Start signal, the input of the CU receives signals from the outputs of node 7, CP 20, n3xi / Un 21 (Fig. 1), register 8 (Fig 5), KVO AP 29, as well as the output signal element 112 delay. The last four signals are designed to determine the sample time of the next microcommand.

The control unit uses a system with a rigid sequence of microinstructions.

the micro-command is associated with the control signal of the CU 17). The operation of the CU is described in the table, which is the sequence and encoding of microcommands (jointing) stored in the memory of 108 microcommands.

The micro-command bits arrive: CW - on the AND-OR elements 111 and NOT 125; X1 on a single trigger input 120; X2 - at the zero input of the trigger 120; HZ to the input of the decoder 10; X4 - to the input element And 16; X5 - to the inputs of the register К / Д АП 31; X6 - to the input of the first element AND of the first group of elements AND 116; X7 - at the entrance Run AP 32; X8 - to the input element And 116; X9 - at the zero input of the trigger 12; XIO - to the inputs of register 3 and zero

A number of microcontrollers of the CU are in the Standby mode until one of the external signals arrives at the AND-OR element 111.

Billing unit: into counter 110 and sampling the next micro-command from the memory 108 micro-commands into the register 109.

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Consider the work of the BU 17 (11). At startup. The control unit (appearance of the Start signal at the single input of the trigger 117) at the output of the register 109 appears zero MK, which switches the trigger 120 to the single state. The device sends at this time a signal to the input ZZh.SH 24. Signal PZh ,. CPU 21 is fed to the input element And 121 and produces a sample of the first microcommand in the register 109, which resets the trigger 120.

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in unitary codes (each bit

trigger input 117. In the presence of a unit in zero division, in the zero state of this bit, in the next cycle,

the micro-command is associated with the control signal of the CU 17). The operation of the CU is described in the table, which is the sequence and encoding of microcommands (jointing) stored in the memory of 108 microcommands.

The micro-command bits arrive: CW - on the AND-OR elements 111 and NOT 125; X1 on a single trigger input 120; X2 - at the zero input of the trigger 120; HZ to the input of the decoder 10; X4 - to the input element And 16; X5 - to the inputs of the register К / Д АП 31; X6 - to the input of the first element AND of the first group of elements AND 116; X7 - at the entrance Run AP 32; X8 - to the input element And 116; X9 - at the zero input of the trigger 12; XIO - to the inputs of register 3 and zero

trigger input 117. In the presence of a unit in zero division, in the zero state of this bit, in the next cycle,

A number of microcontrollers of the CU are in the Standby mode until one of the external signals arrives at the AND-OR element 111.

trigger input 117. In the presence of a unit in zero division, in the zero state of this bit, in the next cycle,

Billing unit: into counter 110 and sampling the next micro-command from the memory 108 micro-commands into the register 109.

Consider the work of the BU 17 (11). At startup. The control unit (appearance of the Start signal at the single input of the trigger 117) at the output of the register 109 appears zero MK, which switches the trigger 120 to the single state. The device sends at this time a signal to the input ZZh.SH 24. Signal PZh ,. CPU 21 is fed to the input element And 121 and produces a sample of the first microcommand in the register 109, which resets the trigger 120.

With the help of this MC BU 17 controls

By transferring the input data to the runway p AP 2. Since the signal Data at the input of the К / Д АП 31 is alternative to the command signal, then in the fifth bit of the MK when writing / reading the data of the АП 2 there is zero. general case in structure. MPS may contain several AP 2, then the input of each of them must go to the corresponding line from the output of the decoder 10. Initializing one or another AP 2 will be determined by the contents of register 5. From these same considerations, all the lines going to the inputs and the outputs of AP 2 are connected to the corresponding inputs and outputs of the remaining AP 2 (in Fig. 1, they are drawn by oblique lines to a common busbar). The end of data transfer to AP 2 occurs when a signal appears from register 8, using which the second micro-command is selected. The second micro-command controls the recording of the opcode in AP 2. Then, a signal is received at the input. AP-32 Launch - a third micro-command is executed. After that, the CU enters the Standby mode — a fourth microinstruction is executed (AP 2 processes the input data).

When a signal appears at the output. KB AP 29 (a pulse signal with a duration equal to the sampling time of the next command from the memory of 108 micro-commands is sampled by a fifth micro-command, with the help of which the operability of the AP 2 is checked. If the output of the fault trigger 48 (Fig. 3) is set to one

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If the signal is received from the output of node 7 (Fig. 9), the signal goes directly to the input from counter 110, by which writing to the information 110 of the content of its information inputs is permitted. In this case, code 9 is present at the information inputs of the counter 110, i.e. A coercive addressing of the ninth microinstruction is performed. If AP 2 is healthy, then the output from node 7 does not receive a signal at the input of counter 110 and a sixth microcommand is taken that controls the reading of the result from AP 2 to the runway. The end of the transfer of the result to the runway occurs when a signal appears from register 8, according to which the seventh micro-command is selected. This microinstruction resets the trigger 12 to zero, which removes the capture of the tires of the CPU 1. The eighth microinstruction stops the control unit 17.

Using the ninth microcommand, the device proceeds to the appropriate subroutine. In this case, the CU is in the Standby mode until the arrival of the signal from the output of the delay element 112. Signals from the output of MTiHn 20 permit the selection of the code of the unconditional branch command and the address of the transition to the data bus 19 (Fig. 8). These signals are separated in time by computer cycles of CPU 1. The first signal through the element 113, the counter 114 is fed to the input of the decoder 115, at the corresponding output of which appears the signal to the sample MBR 100. Similar to the following two signals from the output

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The CPU 20 is sampled containing In turn, AP 2 exposes a signal to the MBR 99 and MBR 98 (the address is passed to NS.AP 26 (in the event of a malfunction). Moreover, the output of the decoder 115 connected to the element NOT 94, is also connected to delay element 112, the signal from which arrives at the end of the signal from the output of WHP 20, which proceeds to the tenth micro-instruction.Ten micro-command resets the signal on the input of the GT with a signal to the zero input of the trigger 12. Eleventh micro-command removes the runway lock and stops the control unit 17. During information processing

10 In the first case, similar actions are performed from the device side. From the output of the CU 17, signals are sent to the input of the decoder 10, to the register 8 (the formation of addresses resulting from the MPS, this device is detected around the device), to the input of the And 11 element ( mode

read AP 2) and the input Zp.PPP 35 (write mode in the runway). After that, the capture of tires of the CPU 1 by a signal from the control unit 17 to the zero input of the trigger 12 and stop of the control unit 17 is performed. As a result, the CPU 1 proceeds to processing

The search for a hardware-implemented function, makes a request for capturing the tires of CPU 1 in the event of such a call, issues information to the appropriate device nodes from the memory of the catalog and, before taking control of the system, prepares a reverse transition to the main program (sends to the command register

CPU 1 command to return from subroutine-25 control subroutine necessary

WE are PET) and also prepares a possible transition to the appropriate subroutine.

After receiving control, the device determines the AP 2, which will process the function, and sends data to it via the data bus 19 from the runway in the direct memory access mode. The signals from the output of the CU 17 are fed to the inputs of the decoder 10 (initiation of the corresponding C # 2) , element 16 and (write mode in AP 2) register 3 (the formation of data addresses), WHP 33 (reading mode PP). After the data has been written to AP 2, the operation code is also written to it via the data bus 19. The signals from the output of the control unit 17 are fed to the inputs of the register 5 (selection of the operation code), the decoder 10, the element And 1.6 (recording mode in the AP 2). After that, from the output of the CU 17, a signal is sent to the input. Starting the AP 32, at which data processing begins (function calculation). The device then waits for the end of the calculation of the function in AP 2. When a signal is output from the CB AP 29, the device checks the operability of AP 2, which performs the calculation of the function. For this purpose, from the output of the CU 17, a signal is applied to the input of the decoder 10, which initiates the corresponding AC 2, and goes to the node 7 (Fig. 9).

AP 2), which also arrives at node 7. Then either results are output from AP 2 to the runway (if AP 2 is healthy), or a transition to the subroutine (if AP 2 is faulty), which implements this function.

In the first case, similar actions are taken from the device side. From the output of the CU 17, signals are sent to the input of the decoder 10, to the register 8 (the formation of the addresses of the final program.

In the second case, for transmission

0

five

.

five

0

make the transition to her first team. To do this, from the output of node 7, the signal is fed to the input of SCP. CPU 23 (with a duration of at least three cycles of the CPU 1 machine cycle), to the input of register 3 (runway interlock), to outputs of BU 17 and element OR 15 (removal of tire trapping CPU 1 and setting the signal to the input of the GT. CPU 23). When a signal is output from the output of CH.TCP 20, the code of the unconditional branch command and the address of the transition to the subroutine are transmitted to the bus 19. Then the signal is reset at the input of Gt., The runway is blocked by a signal from the CU 17 at the input of the register 3 and the CU 17 is stopped.

Claims (2)

1. A device for interfacing a central processor with a group of arithmetic processors, containing a decoder and two elements AND, with the outputs of the first and second elements AND connected to the read and write inputs of the arithmetic processors of the group, respectively, the output of the decoder connected to the first inputs of the first and second elements And it is connected to the inputs of a sample of arithmetic processors of the group, characterized in that, in order to increase speed, a microprogram control unit, a return register in the programs, is entered into it , address register, memory block, operation code register, number register, diagnostic transition register, reference node, two triggers and two OR elements, the read input of the return register to the program connected to the first input of the logic condition of the microprogram control unit and connected to the read output the central processor, the input of the record of the return register to the program is connected to the second input of the logical CONDITION of the microprogram control unit, the first input of the first OR element and is connected to the output of the acknowledgment the central processor, the output of the first trigger is connected to the third input of the logic condition of the firmware control unit and connected to the capture request of the central processor, the output of the second trigger is connected to the readiness input of the central processor, the output of the comparison node is connected to the fourth input of the logic condition of the microprogrammed control unit, the first input the second element OR, the first input of the setup of the return register to the program and is connected to the reset input of the central processor the memory unit is connected to the write output of the central processor; the first input of the comparison node is connected to the read input of the memory unit and connected to the fault outputs of the arithmetic processors of the group; the fifth input of the logic condition of the firmware control unit is connected to the outputs of the arithmetic processors of the group; the output of the microprogram control unit is connected to the start inputs of the arithmetic processors of the group, the second output of the microprogram control unit is connected to the recording input The register is an operation code and is connected to the inputs of the command / data of the arithmetic processors of the group, the first information input of the return register to the program, the information outputs of the operation code register, the register of the diagnostic transition and the information inputs of the memory unit are connected to the information input / output of the central processor, information inputs / outputs of group arithmetic processors and information, input / output of an external program memory o five 0 five 0 five 0 five 0 five information inputs of the program return register, diagnostic transition register, the first information output of the address register and the address input of the memory unit are connected to the address output of the central processor and the address input of the external program memory, the second information output of the return register to the program is connected to the sample enable input external program memory, the third output of the firmware control block is connected to the first read input of the address register, to the second input of the first AND element, and connected to the input the external program memory record, the fourth output of the firmware control block is connected to the second read input of the address register and connected to the read input of the external program memory, while the fifth output of the microprogram control block is connected to the single input of the first trigger, the zero input of which is connected to the sixth input the logic condition of the firmware control block, with the second input of the second element OR, with the input of the register of the address register, with the input of the resolution of the return register to the program, with the input of the register record on Omer, with the entry of the diagnostic transition register entry, with the installation input of the operation code register and the first information output of the memory unit, the second information output of which is connected to the information inputs of the operation code register, the number register and the address register, the second information input of which is connected to the seventh logical input the conditions of the firmware control block, the sixth output of which is connected to the second input of the second element I, the information output of the register of the number is connected to the information ones By the waters of the decoder, I authorize (the second input of which is connected to the seventh output of the firmware control unit, the eighth output of which is connected to the read input of the diagnostic transition register, the second input of the comparison node is connected to the output of the decoder, the ninth output of the microprogram control unit is connected to the second input of the return register into the program and with the second input of the first OR element, the output of which is connected to the single input of the second trigger, the zero input of which is connected to the output of the second OR element. 2. The device of claim 1, wherein the firmware control block contains a micro-instruction memory, a micro-instruction register, a micro-instruction counter, two triggers, a counter, a decoder, a pulse generator, a delay element, eight ten AND elements, OR element, AND-OR element, NOT element, the first input of the first element AND is connected to the clock input of the decoder and is the first input of the logical condition of the block, the first input of the second element AND is the second input of the logical condition of the block, the second input the first element of AND is the third input of the logical condition of the block; the sync input of the microinstruction counter is connected the Q output of which is connected to the fourth And-OR, the output of which is connected to the first input of the OR element, the output of which is connected to the first input of the sixth element AND, the output of which is connected to the second input of the third element AND, the output of which is connected to the counting input of the microcontrol meter whose output is connected with the microinstructions memory address input, the information output of which is connected to the information input the register of 55 microinstructions, the seventh and eighth output of which are connected respectively to the single and zero inputs of the second trigger, the output of which is connected to the second the second element And, 25 thirty with the first input of the third element AND is the fourth input of the logic condition of the block, the first input of the AND-OR element is the fifth input of the logic condition of the block, the single input of the first trigger is connected to the zero input of the micro-command counter and is the sixth input of the logic condition of the block, the second the input of the AND-OR element is the seventh M logical input of the block; the first, second, third, fourth, and fifth outputs of the micro-command register are the first, second, fifth, sixth, and seventh outputs of the block, respectively; ertogo and fifth AND gates being - are outputs of the third and fourth block, respectively, a sixth microinstruction register output connected to a zero input of the first flip-flop and is the ninth output of the first, second and third outputs forming eighth decoder output block at. This is in the firmware control unit the first output of the decoder the input of the AND-OR element, the fifth, sixth, seventh and eighth inputs of which are connected to the ninth output of the micro-command register and the input of the NOT element whose output is connected to the second input of the OR element — the second input of the sixth AND element is connected to the output of the seventh element And the first input of which is connected to the first input of the eighth element I, to the output of the first trigger and to the third input of the first element I, the output of which is connected to the counting input of the counter, the output of which is connected to the information input of the decoder, the first and second outputs of the generator The torus pulses are connected respectively to the second inputs of the seventh and eighth elements I, and the code of the eighth element I is connected to the first inputs of the fourth and fifth And elements and to the input of the register of microinstructions, the tenth and eleven outputs of which are connected to the second inputs of the fourth and fifth elements And, respectively. delay element, connected to the zero input and the third input the output of which is connected to the fourth is not with the entrance the course of which house is And-OR, the output of which is connected to the first input of the OR element, the output of which is connected to the first input of the sixth element AND, the output of which is connected to the second input of the third element AND, the output of which is connected to the counting input of the microcontrol meter whose output is connected with the address of the memory of microinstructions, the information output of which is connected to the information input of the register of microinstructions, the seventh and eighth outputs of which are connected respectively to the unit and zero inputs of the second trigger, the output of which is connected to the second input of the second AND gate, five 0 the input of the AND-OR element, the fifth, sixth, seventh and eighth inputs of which are connected to the ninth output of the micro-command register and the input of the HE element whose output is connected to the second input of the OR element — the second input of the sixth AND element is connected to the output of the seventh AND element, the first input of which is connected to the first input of the eighth element I, to the output of the first trigger and to the third input of the first element I, the output of which is connected to the counting input of the counter, the output of which is connected to the information input of the decoder, the first and second outputs The pulse generator is connected respectively to the second inputs of the seventh and eighth elements AND, the code of the eighth element I is connected to the first inputs of the fourth and fifth elements AND, and to the input of the register of microinstructions, the tenth and eleven outputs of which are connected to the second inputs of the fourth and fifth elements And correspondingly. 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