JPH05313946A - Debugging back-up device for multiprocessor system - Google Patents

Abstract

PURPOSE:To grasp the internal states of all processors constructing a multiprocessor system and all hard modules at the time of a break point of the processor to be debugged. CONSTITUTION:The processors 11-1n are connected to each other and work synchronously with a system clock 301, and the hardware modules 21-2m are also connected to each other and work synchronously with the clock 301. The processors 11-1n output the stop signals 311-31n at the time of their break points, respectively. A clock control part 3 usually outputs a system clock 400 as it is as the clock 30 and stops the clock 301 when a stop signal is inputted from a debugging subject processor designated by a processor selection signal 401. Then, the clock 301 is started again with application of a restart signal 402.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debug assisting device for a multiprocessor system in which a plurality of processors and a plurality of hardware modules execute processing in parallel while mutually transferring data, and more particularly to the processor and the hardware. You can clarify the operational relationship between modules,
The present invention relates to a debugging support device for a multiprocessor system, which facilitates debugging of the entire multiprocessor system.

[0002]

2. Description of the Related Art Generally, a program is debugged by inserting a breakpoint in the program, stopping the execution of the processor for each breakpoint, and observing the state of the processor at that time. On the other hand, in a multiprocessor system, a high-performance system is constructed by deploying a plurality of processors and a plurality of hardware modules and performing parallel processing while transferring data mutually.

Conventionally, as a technique for supporting the debug work of such a multiprocessor system, as described in, for example, Japanese Patent Laid-Open No. 63-85942, another technique is known in which a stop signal from a processor reaching a breakpoint is used. There is known a method of facilitating the grasp of the program states of all the processors when the debug target processors are stopped by also stopping the processors.

[0004]

In the above-mentioned prior art, since stopping the other hardware modules operating in synchronization with each processor at the time of a break point is not taken into consideration, stopping each processor. It was difficult to debug the entire system because the internal states of other hardware modules at that time could not be grasped.

An object of the present invention is to grasp the programs and internal states of all the processors constituting the multiprocessor system and the internal states of all other hardware modules when the processor to be debugged is stopped. It is to provide a debug support device that enables the above.

[0006]

A debug support device for a multiprocessor system according to the present invention operates in synchronization with a system clock, and operates in synchronization with a plurality of mutually connected processors in the same manner as the system clock. , If a stop signal is input from one or more processors to be debugged among the plurality of processors to a system composed of a plurality of hardware modules interconnected with the plurality of processors, A clock control means for stopping the system clocks to all the processors and all the hardware modules including the above and restarting the system clocks by a restart signal from the outside is provided.

[0007]

The user can specify one or more processors to be debugged. When any one or all of the debug target processors reach the breakpoint and send the stop signal, the clock control means stops the system clock at the break of the machine cycle of the processor and all the constituent elements of the entire system. Stop the operation at the same time. By reading the memory of all the processors, the contents of the registers, the contents of the registers of the other hardware modules, etc. at the time of this stop, the operating condition in the system can be accurately observed. After that, if the system clock is restarted by a restart signal from the outside, the system operation can be continued normally, and efficient tracing and debugging of all the components of the multiprocessor system are possible.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment to which the present invention is applied, and a plurality of processors 11 to 1n which operate in synchronization with a system clock 301 and are connected to each other.
And a plurality of hardware modules 21 to 2m which operate in synchronization with the system clock 301 and are mutually connected to the plurality of processors 11 to 1n, stop signals 311 to 31n from the processors 11 to 1n, and External processor selection signal 401, restart signal 40
2, the system clock 400 is controlled to be stopped / restarted, and the clock control unit 3 outputs the system clock 301 to each of the processors 11 to 1n and each of the hardware modules 21 to 2m.

Each of the processors 11 to 1n outputs a stop signal 311 to 31n when the break point is reached. The clock control unit 3 normally uses an external system clock 4
00 is supplied to the entire system as the system clock 301 through, but from the stop signals 311 to 31n from the respective processors 11 to 1n, the stop from the processor designated by the processor selection signal 401 indicating the debug target processor is stopped. When a signal is input, the system clock 3
The output of 01 is stopped. As a result, the processors 11 to 11
The operation of all system components of 1n and the hardware modules 21 to 2m is stopped at the same time. Therefore, the memory, register contents, and other hardware modules 21 to 2 of all the processors 11 to 1n at the time of this stop
By reading the contents of the m register and the like, it is possible to accurately observe all operating conditions in the multiprocessor system. After that, restart signal 402 from the outside
When is activated, the clock control unit 3 again supplies the system clock 400 to the entire system as the system clock 301 through, and restarts the operation of the system.

FIG. 2 shows a concrete configuration example of the clock controller 3 in FIG. In the figure, the decoder 4
1 decodes a processor selection signal 401 for designating a debug target processor given from the outside, and activates at least one of output signals 411 to 41n. Each of the AND circuits 51 to 5n has a decoder 41.
Output signals 411 to 41n and stop signals 311 to 31n from the processors 11 to 1n are input. The AN
Of the D circuits 51 to 5n, when the stop signal in the AND circuit in which the output signal of the decoder 41 is activated becomes active, that is, when the stop signal of the processor designated by the processor selection signal 401 becomes active, O
The flip-flop 42 is switched to the set state through the R circuit 50. Normally, the flip-flop 42 is in the reset state, and at that time, the system clock 400 is directly output as the system clock 301 through the AND circuit 30, but when it is in the set state, the AND circuit 30
Is closed and the system clock 301 is stopped. afterwards,
When the restart signal 402 is activated from the outside,
The flip-flop 42 returns to the reset state, the AND circuit 30 opens, and the system clock 400 is output again as the system clock 301 through the AND circuit 30.

When there are a plurality of processors to be debugged, a plurality of output signals 411 to 41n of the decoder 41 are selected. In this case, of the stop signals from the corresponding plurality of processors, the flip-flop 42 enters the set state when the stop signal that becomes active earliest is generated, and the output of the system clock 301 stops.

FIG. 3 is a block diagram of another embodiment of the portion 6 enclosed by a broken line in FIG. 2, in which the system clock is stopped when the stop signals of the plurality of debug target processors are all active. Is an example of. In FIG. 3, the decoder 41 activates the output signals of the output signals 411 to 41n other than the debug target processor designated by the processor selection signal 401. The OR circuits 61 to 6n include
When the output signals 411 to 41n of the decoder 41 and the stop signals 311 to 31n from the processors 11 to 1n are input, respectively, and when all the stop signals from the debug target processor designated by the processor selection signal 401 become active, the OR circuit All the outputs of 61 to 6n become active, and as a result, the output of the AND circuit 60 becomes active, and the set condition of the flip-flop 42 of FIG. 2 is satisfied.

FIG. 4 shows a concrete example of the hardware modules 21 to 2m in FIG. Figure 4 (a)
Is a configuration example of a FIFO0 buffer module. A plurality of registers (7 in this case) are connected in cascade, and an input data from a data input line is sequentially shifted to the data output line side in the input order. And the FIF
The shift operation of the 0 buffer 211 is performed by the system clock 30.
It is composed of a shift control register 212 which controls in synchronization with 1. 4B shows a configuration example of the timer module, which is a data register 221 in which data representing a designated time is preset, a counter 222 that counts time in synchronization with the system clock 301, a value of the data register 221, and a counter. It comprises a comparison circuit 223 which compares the count values of 222 and outputs a designated time report signal when they match each other, and a gate circuit 224 for setting a preset timing for the data register 221.

FIG. 5 is a block diagram showing a second embodiment to which the present invention is applied, and a plurality of mutually connected processors 11 which are synchronized with the system clock 301 and operate in one machine cycle. 1n, a plurality of hardware modules 21 to 2m which operate in synchronization with the system clock 301 and are mutually connected to the plurality of processors 11 to 1n, and stop signals 311 to 31n from the processors 11 to 1n, Also, the stop / restart control of the system clock 400 is performed by a processor selection signal 401, a restart signal 402, and a machine cycle signal 403 from the outside, and the system clock 30 is sent to each processor 11-1n and each hardware module 21-2m.
It is composed of a clock control unit 3 which outputs 1.

When each of the processors 11 to 1n reaches a breakpoint, it outputs a stop signal 311 to 31n. The clock control unit 3 normally supplies the system clock 400 through to the entire system as the system clock 301, but it is designated by the processor selection signal 401 among the stop signals 311 to 31n from the processors 11 to 1n. When the stop signal is input from the debug target processor, the output of the system clock 301 is stopped at the end point of the machine cycle being executed. As a result, all the system constituent elements of the processors 11 to 1n and the hardware modules 21 to 2m are stopped at the same time. Therefore, the memories and registers of all the processors 11 to 1n and the contents of other hardware modules 21 to 21n at the time of the stop. Two
By reading the contents of the register of m or the like, it is possible to accurately observe all operating conditions in the multiprocessor system at the end of the machine cycle. After that, when the restart signal 402 is activated from the outside, the clock controller 3 supplies the system clock 400 as the system clock 301 again to the entire system in synchronization with the start time of the machine cycle, and restarts the system operation. ..

According to the configuration of FIG. 5, the system clock can be accurately stopped / restarted in the instruction unit of the program of the processor, so that more efficient tracing is possible.

FIG. 6 shows a concrete configuration example of the clock control unit 3 in FIG. In FIG. 6, the operation of the part surrounded by the broken line indicated by 6 is the same as the same part of FIG. That is, among the stop signals of the processors 11 to 1n,
When the stop signal from the debug target processor designated by the processor selection signal 401 becomes active, the flip-flop 42 is switched to the set state through the OR circuit 50. The broken line portion 6 can be replaced with that shown in FIG. In this case, the processor selection signal 401
The flip-flop 42 is switched to the set state under the condition that all the stop signals from the plurality of debug target processors designated by are activated.

When the flip-flop 42 is set, its output signal 420 becomes active. As shown in FIG. 7, the machine cycle synchronization circuit 43 outputs the output signal 43 in synchronization with the machine cycle signal 403 when the output signal 420 of the flip-flop 42 becomes active.
Set 0 to 0. When the output signal 430 of the machine cycle synchronization circuit 43 becomes 0, the AND circuit 30 is closed and the system clock 301 is stopped. After that, when the restart signal 402 is activated, the flip-flop 42 is
Returns to the reset state, and as shown in FIG. 7, the output signal 430 of the machine cycle synchronization circuit 43 becomes 1 in synchronization with the machine cycle signal 403, and the system clock 30
1 resumes.

[0020]

【The invention's effect】

(1) According to claim 1, the user specifies a processor to be debugged, so that the entire system including the processor and other hardware modules is stopped at the same time according to the breakpoint of the target processor. Therefore, it is possible to accurately observe the operating status in the system by reading the memory of all the processors, the contents of the registers, the contents of other hardware modules, etc. at the time of stop. Further, the system operation can be normally continued by the restart signal from the outside from the stop point, and it can greatly contribute to the efficient tracing of all the constituent elements of the multiprocessor system and the facilitation of the debugging work. ..

(2) According to the second aspect, since the system clock can be stopped at the break of the machine cycle of the processor, the operation of the processor program can be stopped / restarted in the unit of instruction, and an accurate trace can be performed. Become.

(3) According to claim 3, the system clock can be stopped at the first breakpoint of the processor to be debugged. Therefore, even if many breakpoints are inserted in the program, it is efficient. Tracing is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment to which the present invention is applied.

FIG. 2 is a diagram showing a specific configuration example of a lock control unit in FIG.

FIG. 3 is a diagram showing another embodiment of a partial configuration in FIG.

FIG. 4 is a diagram showing a specific example of a hardware module.

FIG. 5 is a block diagram showing a second embodiment to which the present invention is applied.

FIG. 6 is a diagram showing a specific configuration example of a clock control unit in FIG.

FIG. 7 is a time chart showing the operation of the machine cycle synchronization circuit in FIG.

[Explanation of symbols]

 11-1n processor 21-2m hardware module 3 clock control unit 311 to 31n stop signal line 301, 400 system clock signal line 401 processor selection signal line 402 restart signal line 403 machine cycle signal line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kyozo Takahashi 1-14-5, Kichijojihonmachi, Musashino-shi, Tokyo NTT Electronics Technology Co., Ltd.

Claims (3)

[Claims] 1. A debug support device for a multiprocessor system, wherein a plurality of processors and a plurality of hardware modules are connected to each other and operate in synchronization with a system clock. When a stop signal is input, it comprises clock control means for stopping the system clocks to all the processors and the hardware modules including the processor and restarting the system clocks by a restart signal from the outside. Debugging support device for multiprocessor system. 2. The plurality of processors operate in a machine cycle having the same cycle, and the clock control means uses the stop signal from the processor to be debugged as a trigger to end the machine clock being executed. 2. The debugging support device for a multiprocessor system according to claim 1, wherein the system clock is restarted in synchronism with a start time of a machine cycle by an external restart signal. 3. The multiprocessor system according to claim 1, wherein the clock control means stops the system clock at the input of the first stop signal of the processors to be debugged. Debugging support device.