JPS62119663A - Information processing unit - Google Patents

Abstract

PURPOSE:To attain an analysis with high accuracy in applying debug or retrieval of a fault by designing the titled unit that the timewise relation when data read from a main storage device exists on a data bus and the timing when the data is stored in a register of a processor are equal to that at normal running when a SS read instruction is executed in the step mode. CONSTITUTION:In a system that a main storage device 6 and plural processors are constituted to use an information transfer bus 8 in common, and when a processor executes an instruction to read the content of the main storage device in the step mode, the information read from the main storage device is stored in the own register of a processor other than the processor executing the instruction reading the content of the main storage device and the said processor keeps transmission of the content of the register to the information transmission bus 8 except the time when the information transfer bus is used for other purposes. Thus, a large quantity of hardware exclusive for the step mode is not required to be provided to the main processor.

Description

[Detailed Description of the Invention] [Summary] When a processor executes an instruction without reading data from the main memory, the main memory is usually Other instructions that can be executed by the processor independently of the storage device are executed in advance.

Therefore, the read data is set in the registers of the processor after several instructions have been executed. When such a processor is used in step mode, the timing at which data read from the main memory is set in the processor and the timing at which other instructions are executed differ from the actual timing. For this reason, in the past, data read from main memory was temporarily held in a register, and when the appropriate timing came, it was stored in a predetermined register. However, there is a problem in that the relationship between the relevant subsequent instruction execution cycle section and the time period in which data read out on the information transfer bus exists is different from the actual case. In a system where a main memory device and a plurality of processors share an information transfer bus, the present invention operates the processors in step mode and reads data from the main memory device.
The present invention discloses the configuration and control of a processor that can obtain a state with few differences in actual running of data on an information transfer bus when executing an instruction.

[Industrial Field of Application] The present invention relates to the control of information processing devices, and in particular to the control of processors in step mode in systems configured such that a main storage device and a plurality of processors share a bus for information transfer. This relates to control when executing the "instruction to read data from the main memory".

[Prior Art] Instructions in an information processing device are executed continuously at a very high speed, and it is usually not possible to see the processing contents or the state of the hardware in the middle of a program. On the other hand, when debugging a program or searching for hardware failures, it is necessary to closely observe the state of each part of the processor related to instruction execution (such as the contents of internal registers and storage devices) at each transition of the executed instruction. often occurs.

Therefore, in general, information processing devices have a mode (step mode) in which step operation is performed in addition to the normal driving mode.
It is now possible to set. In the step mode, when a button provided on a maintenance panel or the like is pressed, only the - command is executed each time, and when the processing related to the command is completed, the process stops (stop state).

On the other hand, in normal running mode, among the instructions handled by the processor, an instruction to read data from the main memory (hereinafter referred to as S
In the case of an S read instruction), the processor executing the instruction does not waste time by idly spending a relatively long time while the corresponding data is being read from the main memory. During this time, other instructions are executed in advance.

FIG. 2 shows a timer I showing an example of the relationship between instruction execution and read cycles. ~1. 2 indicates an instruction execution cycle, and 2 indicates a read cycle.

As shown in FIG. 2, when the SS read instruction 11 is executed, the read command is set in the register of the processor at the end of read cycle 2, at the timing indicated by reference mark A in the figure. Become.

If we consider running this in step mode,
The time chart is shown in Figure 3. That is,
When the SS read instruction 31 is executed, data is read from the main memory in read cycle 4, and the data is read from the main memory with reference mark B.
It is stored in the processor register at the time indicated by . As explained earlier, in the normal running mode, the read cycle is as shown by 5, and the data read from the main memory at the end of instruction B, indicated by reference mark A', is read by the processor. Since it is supposed to be stored in the register, the movement of data in step mode will differ from the actual situation.

Therefore, in the past, a dedicated circuit was provided to temporarily hold the data read from the main memory by the SS read instruction in the step mode in another register within the processor, and at the appropriate timing, the data read from the main memory The method used was to store it in the register where it should be stored.

[Problems to be Solved by the Invention] FIG. 4 shows the SS in the conventional step mode described above.
This is a diagram showing a circuit for controlling a read command, where 6 is a main memory, 71 to 73 are processors, 8 is an information transfer bus (hereinafter also referred to as a data bus), 9 is a register (REGI), and 1
0 represents a register (REG2), and 11 represents a selection circuit.

In FIG. 4, normally when the processor 7 executes the SS read instruction, data read from the main memory 6 and placed on the data bus 8 is stored in the register 9 and passed through the selection circuit 11. It is stored in register 10.

On the other hand, in the step mode, the data on the data bus 8 is stored in the register 9, but not in the register 10. Then, at an appropriate timing, the contents of register 9 are stored in register 10 through selection circuit 11.

In such a conventional circuit, when an SS read instruction is executed in step mode, the timing relationship in which data read from the main memory is stored in the corresponding register of the processor is the same as in actual running. However, the situation in which data exists on the data bus 2 is significantly different from the actual situation. In other words, in normal running conditions, the data on the data bus 2 exists from the time the data is read from the main memory until point B shown in Figure 3, whereas in step mode the data exists up to point B. only exists.

Since step motion is originally used for program debugging, troubleshooting, etc., it is very inconvenient for the relative relationships of various parts to be different from the actual running conditions.

In addition, in the case of the configuration in which the processors 7 shown in Fig. 4 are the main processors and the processors 71 and 72 are the slave processors, there is a hardware problem in that the main processor must have a dedicated function for debugging. The problem was that it was subject to restrictions.

In view of these conventional problems, the present invention provides a control system in which the state of data on the data bus is similar to the actual running state, and there is no need to provide a large amount of hardware dedicated to the step mode in the main processor. The purpose is to provide an information processing device.

[Means for Solving the Problems] According to the present invention, the above object is achieved by providing a system configured such that a main storage device and a plurality of processors share an information transfer bus. In step mode, when a processor executes an instruction to read the contents of the main memory, the information read from the main memory is transferred to any processor other than the processor executing the instruction to read the contents of the main memory. An information processing device characterized in that a processor stores the contents in its own register, and the processor continues to send the contents of the register to the information transfer bus except when the information transfer bus is used for other purposes. This is achieved by

[Embodiment] FIG. 1 is a block diagram of one embodiment of the present invention, and includes 6.
8 is the same as in FIG. 4, 9 is an interface processor, 10 is a slave processor, 11 is a main processor, 12
．． 13 is a register, 12 is REG 1.13 is REG2
．． 14 represents a selection circuit, and 15 to 17 represent gates.

In FIG. 1, the main processor 11 is in the normal running mode.
When the SS read command is executed, the data read from the main memory 6 and placed on the data bus 8 is set in the register 13 via the gate 17. During this time, other instructions are being executed in advance.

The temporal relationship is exactly the same as the conventional case explained with reference to FIG. 2 above.

On the other hand, in the step mode, data read from the main memory 6 and placed on the data bus 8 by the execution of the SS read instruction by the main processor 11 is transferred to the register 12 (REGI) via the gate 16 of the slave processor 10.
is stored in The timing at which data is stored in the register 12 is indicated by reference numeral B in FIG. Then, the data stored in the register 12 passes through the selection circuit 14 and the gate 15 and is transferred to the data bus 8.

In FIG. 3, the main processor 11 opens the gate 17 and transfers the data bus 8 at the timing indicated by reference numeral A'.
The data stored in the register 13 (REG2) is stored in the register 13 (REG2).

Therefore, when the main processor 11 executes the SS read command in the step mode, data is stored in the register 13 in the same temporal relationship as in the normal running mode, and during that time, the data read from the main memory 6 is also present on the data bus 8'' as in the normal running mode.

[Effect of the invention] As explained above, according to the information processing device of the present invention, S
When an S read instruction is executed in step mode, the time relationship in which the data read from the main memory exists on the data bus and the timing at which the data is stored in the register of the processor differ from those in normal running. be equal. Therefore, there is an advantage that highly accurate analysis can be performed when debugging a program or searching for a failure.

It also has the advantage of eliminating the inconvenience of having to have a dedicated dedicated piece of hardware in the main processor that can only be used for debugging.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a time chart showing an example of the relationship between instruction execution and read cycles, and FIG. 3 is an example of the relationship between instruction execution and read cycles in step mode. FIG. 4 is a diagram showing a circuit for controlling the SS read command in the conventional step mode. 11-11.3. ~33... Instruction, 2.4.5
. . . Read cycle, 6 . . . Main memory, 7. ~73... Processor, 8...:...
・Information transfer bus, 9.10.12.13...
Register, 11.14... Selection circuit, 15-1
7...Gate Conventional Steps

Claims (1)

[Claims] In a system configured such that a main memory device and multiple processors share an information transfer bus, when a processor executes an instruction to read the contents of the main memory device in step mode, the information read from the main memory device is Any processor other than the processor that executes the instruction to read the contents of main memory stores the contents of the register in its own register, except when the information transfer bus is used for other purposes. An information processing device that continues to send data to the information transfer bus.