JP2684966B2 - I / O processor debug device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output processing device for controlling an input / output operation in an information processing system, and more particularly to a device for debugging or analyzing a failure.

[0002]

2. Description of the Related Art In a conventional debugging device for an input / output processing device of this type, a specific channel command in a main storage device is executed when evaluating the input / output processing device for controlling the input / output operation or investigating a failure. In order to check the state of the information processing system immediately after, the diagnostic processing unit has instructed the microprogram address of the input / output processing unit microprogram corresponding to the channel command. Then, when the input / output processing device microprogram address reaches the designated address, the clock of the input / output processing device is stopped to collect the data in the information processing system. For example, Japanese Patent Application Laid-Open No. 2-171937 discloses an address coincidence stop circuit that stops the clock of the processing device based on the comparison result of the execution addresses of the microprogram.

[0003]

However, in the debug device of the conventional input / output processing device, since the address matching is detected at the microprogram level,
When different channel commands share the same microprogram, it is difficult to detect that a specific channel command has been executed. Further, even if it is possible to detect that a specific channel command has been executed, it is necessary to stop only the clock of the input / output processing device as in the conventional case, for example, in the arithmetic processing device in the information processing system. Such other devices change the system state and cannot collect data properly. In particular, since the processing speed of the input / output processing device is significantly slower than the processing speed of the arithmetic processing device and the like, it is difficult to immediately interrupt the execution of other processing devices even if an interrupt is made by software.

[0004]

In order to solve the above-mentioned problems, a debug device for an input / output processing device according to the present invention comprises:
In an information processing system, a system control device that controls the entire information processing system, a main memory device, an arithmetic processing device that interprets software instructions and performs arithmetic processing and reference update processing to the main memory device, It has a diagnostic processing device for diagnosing the system and an input / output processing device for communicating with the input / output device. In this input / output processing device, the main storage device is responsive to a command from the arithmetic processing device. Channel program execution means for executing the stored channel program, channel program execution address storage means for holding a channel program address being executed by the channel program execution means, and a channel to be stopped instructed by the diagnostic processing device. Channel program stop address storage that holds the program address And a channel program address comparison means for comparing the address held by the channel program execution address storage means with the address held by the channel program stop address storage means to detect a match between the two. When the comparing means detects an address match, the input / output processing device is stopped.

In the input / output processing device, channel program executing means for executing a channel program stored in the main storage device in response to a command from the arithmetic processing device, and execution by the channel program executing means. The channel program execution address storage means for holding the channel program address therein, the channel program stop address storage means for holding the channel program address to be stopped instructed by the diagnostic processing device, and the channel program execution address storage means And the address held by the channel program stop address storage means to detect a match between the two, and when the channel program address comparison means detects an address match. And a system stop instruction means for instructing the stop of the entire information processing system to the system controller.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a debug device for an input / output processing device according to the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a debug device for an input / output processing device, which is an embodiment of the present invention, includes a system control device 10 for controlling the entire information processing system and a software command for interpreting various operations. An arithmetic processing unit 20 for performing processing, a diagnostic processing unit 30 for diagnosing an information processing system, a main storage unit 50, and an input / output processing unit 40 for controlling an interface with an input / output unit are connected via a system bus 100. Connected to each other.

The input / output processing device 40 further takes out channel program execution means 41 for fetching and executing the channel programs stored in the main storage device 50 one by one, and the main storage of the channel program being executed by the channel program execution means 41. Channel program execution address storage means 42 for holding addresses, and diagnostic processing device 3
Channel program stop address storage means 43 for holding the channel program address to be stopped, which is instructed from 0, and channel program execution address storage means 42
Address of the channel program stop address storage means 43 to detect a match between the two, and an information processing system when the channel program address comparison means 44 detects an address match. It has a system stop instruction means 45 for instructing stop of the whole.

Next, the operation of this embodiment will be described.

The system control unit 10 controls the entire information processing system and supplies a clock to each device in the system, disconnects a failed device and installs it after restoration, a main storage device and each device. Interface control and communication control processing between each device. In synchronization with the clock supplied by the system controller 10, the arithmetic processing unit 20 fetches software instructions from the main memory 20 and executes each instruction. Normal arithmetic instructions, main memory access instructions, etc. are advanced between the arithmetic processing unit 20 and the main memory 50. When the arithmetic processing unit 20 executes an input / output instruction to a disk device or the like, first, the arithmetic processing unit 20 sets a channel in a common area of the main storage unit 50 between the arithmetic processing unit 20 and the input / output processing unit 40. The program start address, the input / output device number (channel number), etc. are written, and the channel program execution wait state is set.
An I / O request is issued to the I / O processor 40 via 0. Then, the input / output processing device 40 receiving this input / output request sets the channel program waiting to be executed to the active (active) state, and sets the start address of the designated channel program in the channel program execution address storage means 42. As a result, the channel program stored at this address is read from the main storage device 50, and the channel program execution means 41 executes the channel program. After the first channel program execution, the channel program execution address storage means 42
The channel program address held in is updated to point to the next channel program address. Then, the channel program is read from the main storage device 50 using this address, and the channel program execution means 41 executes the channel program.

The execution of the channel program in the input / output processing device 40 is thus performed by reading the channel program from the main storage device 50 one by one. When the input / output command instructed by the arithmetic processing unit 20 ends in the input / output processing unit 40, the input / output processing unit 40
Issues a channel program end report to the arithmetic processing unit 20, so that the arithmetic processing unit 20 can know that the input / output instruction is completed. At this time, the input / output processing unit 40 describes the result code in the channel program end report, and by checking this result code, the arithmetic processing unit 20 can know whether or not the input / output instruction is normally ended. it can.

Referring to FIG. 2, in the schematic diagram of the processing of the input / output instruction of the present invention, the input / output instruction issued from the arithmetic processing unit 20 is a channel program composed of a channel command sequence in the input / output processing unit 40. Then, the microprogram is activated from each channel command and the actual input / output processing is performed. In addition,
This channel command can also be directly realized by hardware without going through a microprogram.

In order to know the state of the information processing system immediately after the execution of a specific channel command, the diagnostic processing unit 30 specifies the channel program address at which the execution of the channel program should be stopped, and the input / output processing unit 4 is preliminarily set.
Instruct 0 to that effect. Upon receiving this instruction, the input / output processing device 40 stores the address to be stopped in the channel program stop address storage means 43. When executing the channel program in the input / output processing device 40, the channel program address of the channel program execution address storage means 42 that is updated one by one and the channel program address of the preset channel program stop address storage means 43 are compared with each other. The means 44 compare and monitor whether they match. If the two addresses do not match, execution of the channel program proceeds normally. if,
When it is detected that the two addresses match, the channel program address comparison means 44 notifies the system stop instruction means 45 to that effect. Upon receiving the notification, the system stop instruction means 45 instructs the system controller 10 to stop the entire information processing system via the system bus 100. According to this instruction, the system control device 10 stops the clock supply to each device in the information processing system. As a result, all operations of this information processing system are stopped.

The reason why the information processing system is stopped at the clock level in this way is that the input / output processing unit 40 and the arithmetic processing unit 20 have a large processing speed gap as described above, and thus the input / output processing unit 40 is stopped. Even if only this is stopped, the arithmetic processing unit 20 will execute a considerable number of instructions, and there is a high possibility that the state of the main storage device 50 will be rewritten by the arithmetic processing unit 20. This is because even if an attempt is made to check the system state immediately after the execution of the channel command in (3), it will be difficult to collect appropriate data. By stopping the clock of the entire information processing system as in the present invention, the state immediately after the execution of a specific channel command can be accurately grasped, and appropriate system evaluation and failure investigation can be performed. When there is no gap between the processing speeds of the input / output processing device 40 and other devices in the system, it is possible to control so that only the input / output processing device 40 is stopped as in the conventional case.

[0015]

As described above, according to the debug device of the input / output processing device of the present invention, by stopping the clock of the entire information processing system when a specific channel command is executed, The system state immediately after execution can be accurately grasped, and appropriate system evaluation and failure investigation can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a debug device of an input / output processing device of the present invention.

FIG. 2 is a schematic diagram of processing of input / output instructions in the present invention.

[Explanation of symbols]

 10 system control device 20 arithmetic processing device 30 diagnostic processing device 40 input / output processing device 41 channel program execution means 42 channel program execution address storage means 43 channel program stop address storage means 44 channel program address comparison means 50 main storage device 100 system bus

Claims (1)

(57) [Claims] 1. In an information processing system, a system control device for controlling the entire information processing system, a main memory device, and an arithmetic process for interpreting a software instruction to perform an arithmetic process and a reference update process to the main memory device. A device, a diagnostic processing device for diagnosing the information processing system, and an input / output processing device for communicating with the input / output device. In this input / output processing device, in response to a command from the arithmetic processing device, A channel program executing means for executing a channel program stored in the main memory, a channel program execution address storing means for holding a channel program address being executed by the channel program executing means, and an instruction from the diagnostic processing device. Channel program stop that holds the channel program address to be stopped And stop address storage means, and the channel program address comparison means for detecting a coincidence of both by comparing the address which the address and the channel program stop address storing means for channel program execution address storing means for holding held, the channel programming
When an address match is detected by the RAM address comparison means
To stop the entire information processing system
And a system stop instruction means for instructing to the input / output processing device.