JPH01293447A - Control system for address coincidence interruption - Google Patents

Abstract

PURPOSE:To efficiently simulate the address coincidence stop of a real computer with a virtual computer, etc., by suppressing the action of a stopping means due to an output signal to indicate coincidence, and issuing a prescribed interruption with the output signal to indicate the coincidence when a prescribed mode is set. CONSTITUTION:A means exists which stops the action of a central processing unit 41 by means of the output signal to indicate the coincidence of address coincidence detecting parts 17 and 16. For example, when a virtual computer (VM) mode is not set, a system interruption generating part 43 to be provided in a central processing unit 41 is stopped by setting a stop latch 32 by means of a signal to indicate the address coincidence in the same way as usual, while, at the time of a VM mode, when the output signal to indicate the address coincidence is produced, the part 43 suppresses the setting of the stop latch 32, and generates the prescribed interruption according to the designated bit of a control register 44. Thus, even the VM can use an address stopping function.

Description

[Detailed Description of the Invention] [Summary] Regarding the control of the address match stop function of a processing device having an operation mode such as a virtual machine, an address match that can efficiently simulate the address match stop function of a real computer with a virtual machine etc. For the purpose of an interrupt control system, a comparison means for detecting a match with an address referenced by an executed program with respect to addresses set as logical addresses, real addresses, and absolute addresses, and an output signal of the comparison means indicating the match. , an information processing system having a stop means for stopping the operation of a processing device that executes the program, and the processing device has a mode set to selectively designate one of a plurality of different operation control states. In this case, when a predetermined mode is set, the operation of the stopping means is suppressed by the output signal indicating the match, and a signal for generating a predetermined interrupt is output by the output signal indicating the match. Configure.

[Industrial application field]

The present invention relates to the control of an address match stop function of a processing device having an operation mode such as a virtual machine in an information processing system, and in particular, an address match interrupt control method for simulating address match stop of a real computer in a virtual machine or the like. Regarding.

In an information processing system, in order to test the hardware or software of a processing device, the addresses of instructions and data in the main memory referenced by a program being executed are monitored, and when a specified address is referenced, the processing is performed. It is possible to stop the operation of the device and investigate the system status at that time (as is well known), and the function for this is called the address stop function.

[Conventional technology]

FIG. 2 shows a configuration example of an information processing system, in which a central processing unit 1 is configured to access a main storage device 15 via a storage control device 2, and a service processor (hereinafter referred to as (referred to as SVP) 3 is connected to each device. Although FIG. 2 shows only one central processing unit 1 and one storage control unit 2, it is possible to configure a multiprocessor system with a plurality of central processing units 1, and in that case, the storage control The number of devices 2 is also provided as required depending on, for example, the number of central processing units.

When using the address stop function for the purpose described above, first input the required command and operate the 5VP3, so that the SVP 3 can read the required status register 9 of the central processing unit 1 and the storage control unit 2. Turn on the address stop designation focus of the control register 10.

Next, when a command specifying an address to be stopped, etc. is input, and an address value, address mode, and access operation are specified, the SVP 3 sends them to the specified central processing unit 1 and storage control unit 2.

Commands are sent from the instruction control unit 12 to 5 according to predetermined instructions.
It can also be input to VP3.

Here, the address mode is a designation of whether to monitor an address using a known logical address, a real address, or an absolute address in a virtual memory type information processing system. If an address is specified, the above address value,
The address mode and access operation designation are sent to the designated central processing unit 1, and if an absolute address is designated, the address value and the access operation designation are sent to the designated central processing unit 1 or storage control unit 2.

Furthermore, the access operation refers to whether the access to a specified address is an instruction fetch, an operand fetch, or an operand store (however, in the case of a storage control device, only the distinction between fetch and store is valid); to the address of
Only the case where the access operation specified in I is executed is subject to monitoring.

The above specification information sent from the 5VP3 is received by the address-number register section 17 of the storage control unit 13 of the central processing unit 1 or the address-number register section 16 of the storage control device 2, and the address value is subjected to address comparison. Set in register 4 or 5.

When executing a program in the central processing unit 1, the address control unit 20 of the instruction control unit 12, which decodes instructions and performs address generation and other controls, determines the operand address of each fetched instruction and the instruction address of the next instruction. , along with the command information, is passed to the storage control unit 13, where the storage control unit 13 executes known control such as cache control, address conversion processing, and main memory access.
It performs fetching and storing of data and fetching of instructions to be processed in step 4.

At this time, the address-number part 17 of the storage control unit 13 is
According to the address mode designation and access operation designation received from the 5VP3, the logical address received from the address control unit 20 or the real address of the address translation result is compared with the address held in the address comparison register 4, A signal indicating the comparison result is returned to the instruction control unit.

The address stop control unit 30 of the instruction control unit 12 receives the signal of this comparison result, and if the addresses match and the address stop designation bit of the status register 9 is on, an appropriate action is taken, such as completion of execution of the instruction. By generating a stop signal 31 at a timing and setting a stop launch 32, the subsequent progress of instruction execution control is stopped. This state is, for example, from SVP 3 to stop latch 3.
Continues until 2 is reset.

If the address-number control unit 16 of the storage control unit 2 is set to monitor absolute addresses, when a main memory access request is issued from the storage control unit 13 to the storage control device 2, the control register If the address stop designation focus of No. 10 is on, the address-count register 16 compares the requested address with the address held in the address comparison register 5, and sends the signal of the comparison result to the address stop control unit 30.
Therefore, the address stop control section 30 controls the generation of the stop signal 31 in the same manner as described above.

[Problem to be solved by the invention]

When the central processing unit 1 executes a virtual machine (hereinafter referred to as VM) under the management of a known virtual machine monitor (hereinafter referred to as VM monitor), for example, the VM monitor allocates an appropriate time to each VM. Te VM
Execute.

At that time, the VM monitor turns on the VM mode bit of the extended control register 11 in the central processing unit 1 that is in a state where control is handed over to the VM to set it to VM mode, and if the central processing unit 1 is in the VM mode, For example, when a predetermined privileged instruction is fetched, the execution of the command is inhibited and control is returned to the VM monitor. By doing so, the central processing unit 1, which is a real computer, generally simulates multiple virtual computer systems. can be

However, regarding the above-mentioned address stop function, if it is used on one VM, the central processing unit of the real computer will stop due to address matching, and the VM monitor will not be able to be managed, so it should not be used. I couldn't do it.

The object of the present invention is to provide an address match interrupt control method that allows a virtual computer or the like to efficiently simulate the address match stop of a real computer as described above.

[Means to solve the problem]

FIG. 1 is a block diagram showing the configuration of the present invention.

The figure shows the configuration of an information processing system, which includes a central processing unit 41, a storage control device 2.5VP3, and a main storage device 1.
5, the central processing unit 41 includes a storage control unit 13 and an arithmetic control unit 14 that execute instructions under the control of the instruction control unit 42.
The instruction control unit 42 includes an address control unit 20 that generates addresses of instructions and operands, a status register 9, and a system interrupt generation unit 43. The instruction control unit 42 includes an address control unit 20 that generates addresses of instructions and operands, a status register 9, and a system interrupt generation unit 43. Generate a signal or generate a system interrupt.

[For production]

The information processing system shown in FIG. 1 includes an address-numerical section 17.16, which is a comparison means for detecting a match between an address set in the conventional manner and an address referenced by a program to be executed. Number of mountains 17.1
There is a means for stopping the operation of the central processing unit 41 in response to an output signal indicating a match of 6. Further, the central processing unit 41 is set to normal mode, V
One of a plurality of operation modes such as M mode can be set.

System interrupt generation unit 43 provided in the central processing unit 41
For example, if the VM mode is not set, the stop latch 32 is set and stopped in the same manner as in the past by a signal indicating address matching, but in the case of VM mode, the output signal indicating address matching is When , the setting of the stop launch 32 is suppressed and a predetermined interrupt is generated according to the designated bit of the control register 44.

With the above method, it becomes possible to use the address stop function even in a VM.

〔Example〕

In FIG. 1, parts indicated by the same reference numerals as those in FIG. It is assumed that this is similar to the instruction control unit 12 of the processing device 1. In addition, FIG. 1 shows one central processing unit 41 and one storage control unit 2, respectively.
Although only the device is shown, a multiprocessor system can be constructed in the same manner as described above.

When using the address stop function, the required central processing unit 41 is
status register 9 and control register 1 of storage controller 2
Turn on the address stop designation bit of 0, and then set the address value, address mode, and access operation that specifies the address to be stopped, etc. to the address-number control section 17 of the storage control section 13 of the central processing unit 41 or the storage control device. 2
address value is set in the address comparison register 4 or 5.

In the central processing unit 41, the address control unit 20 of the instruction control unit 42 determines the operand address of each fetched instruction and the instruction address of the next instruction, and passes them along with the command information to the storage control unit 13, as in the conventional manner. Storage control unit 1
3 performs fetching and storing of data to be processed by the arithmetic control unit 14, fetching of instructions, etc., as in the conventional case.

At this time, the address control section 20 also passes the address stop designation bit of the status register 9, and the address-number control section 17 of the storage control section 13 executes the address comparison as in the past and sends a signal indicating the comparison result to the instruction control section. Return to 42.

The system interrupt generating section 43 provided in the present invention in the instruction control section 42 receives the signal of this comparison result, and if the addresses match and the address stop designation bit of the status register 9 is on, execution of the instruction is completed. A signal corresponding to the conventional stop signal 31 is generated at an appropriate timing such as, etc., but at this point, the VM mode designation bit of the control register 44, similar to that of the conventional control register 11, is referred to, and if it is not the VM mode, Since the conventional stop signal 31 is generated and the stop latch 32 is set, the subsequent progress of instruction execution control is stopped as in the conventional case.

In the case of the VM mode, the CPU address comparison bit and the MCU address comparison bit, which are interrupt mask bits for each interrupt factor in the control register 44, are also referred to, and in the case of an address match signal from the address-count register 17, When the CPU address comparison bit is on, an interrupt signal 45 is generated to generate a system interrupt, and the interrupt cause is output to a signal line 46.

When the address/numerical register section 16 of the storage control section 2 is set to monitor absolute addresses, the signal of the comparison result sent from the address/numerical register section 16 as in the past can also be used as a system interrupt according to the present invention. The generation unit 43 takes the receiver and the stop latch 3 is not in the VM mode as described above.
Set 2. In addition, in the case of VM mode, the above MC
When the U address comparison bit is on, an interrupt signal 45 for system interrupt is generated.

When using the address stop function in the VM, for example, the VM monitor mediates and sets the required address etc. in the address-number part 16 and 17 via 5VP3, and also sets the above-mentioned interrupt mask bit in the control register 44. Set it to the required value and run the VM. The VM monitor needs to set the above-mentioned settings to the required state for each VM each time the VM to be executed is switched.

When an address stop condition occurs during execution of a VM, a system interrupt occurs without stopping the central processing unit 41 as described above, execution of the VM is interrupted, and the VM
Control is passed to the monitor. Therefore, the VM monitor can immediately start the necessary control processing corresponding to the system interrupt.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, in a processing device having an operation mode such as a virtual computer, there is a significant industrial effect in that an address match stop of a real computer can be efficiently simulated using the virtual computer or the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the present invention, and FIG. 2 is a block diagram showing an example of a conventional configuration. In the figure, 1.41 is the central processing unit, 2 is the storage controller, 3 is the service processor (SVP), 4.5 is the address comparison register, 9 is the status register, and 10.11.44 is the control register. , 12.42 is an instruction control unit, 13 is a storage control unit, 1
4 is an arithmetic control unit, 15 is a main storage device, 16.17
20 is an address control section; 30 is an address stop control section; 32 is a stop latch; 43 is a system interrupt generation section. FIG. 1 is a block diagram showing the configuration of the present invention.

Claims (1)

[Claims] Comparison means (16, 17) for detecting a match between addresses set as logical addresses, real addresses, and absolute addresses with addresses referenced by a program to be executed.
and a stopping means (32) for stopping the operation of a processing device (41) that executes the program in response to an output signal from the comparing means indicating the coincidence, and the processing device has a plurality of different operation control states. In an information processing system having a mode (44) set to selectively designate one mode, when a predetermined mode is set, the operation of the stopping means is inhibited by an output signal indicating the match. and is configured to output a signal (45) for generating a predetermined interrupt based on the output signal indicating the match (43).
An address match interrupt control method characterized by: