JPS6220039A - Stop operation suppressing control system - Google Patents

Abstract

PURPOSE:To make the operation easy to improve the test efficiency by making a stop command ineffective in a prescribed program execution state if the stop command for test is set. CONSTITUTION:A status bit 21 is one bit of a program status word and is turned on in the problem state and is turned off in the supervisor state. When the stop operation is designated from a testing equipment 1 by an instruction stop designating line which instructs a processor 29 to stop execution for every instruction or an address stop designating line 4 which instructs the processor 20 to stop execution for coincidence of access address, a stop designation latch 5 is set. A gate 22 operates AND among the signal of the stop designation latch 5, the signal on an instruction end line 7 which is outputted from an execution control part 6 and indicates the execution end of every instruction, and the status bit 21 and outputs the result to a signal line 23. A stop control part 10 is started by the turn-on signal on the signal line 23 to stop the advance of the execution control part 6.

Description

[Detailed Description of the Invention] [Summary] This is a control method for automatically suppressing the execution stop operation of a processing device for tests such as program debugging under specific conditions. In order to test a program that runs in a so-called problem state, for example, if you set a stop designation to stop at every step, if you index from that program to a program that runs in supervisor state, for example, the stop designation will be set. A control mechanism is provided to disable the program, and programs in the supervisor state can be executed continuously to improve operational efficiency such as debugging.

[Industrial application field]

The present invention relates to a control method for automatically inhibiting the execution stop operation of a processing device for testing such as program debugging in a computer system under specific conditions.

The processing unit of a computer system has a function that stops the program every time it executes one instruction until instructed by a key on the test equipment, or a function set in the test equipment, which is mainly used as an aid for program debugging. A function is provided to stop execution when a storage address is accessed.

These stop functions are used in such a way as to find clues for detecting program errors by investigating the contents of various registers of the processing device in the stopped state.

Furthermore, the programs executed by the computer system include programs created by users and generally called user programs or problem programs.
These programs are broadly divided into management programs that manage the execution of these programs and service specific functions, and control is transferred between the two programs at any time during program execution, but these programs are not subject to the above test. In most cases, it is the former program.

[Problems to be solved by the prior art and the invention] As is well known, the so-called problem program and the so-called management program as described above are designed to maintain system security. Generally, a method is adopted in which certain restrictions are imposed on the execution of a problem program by setting different program execution states, such as not allowing execution of specific types of instructions (for example, privileged instructions).

Such program execution status is indicated, for example, by specific bits of a known program status word, such that the program status word of the problem program indicates the problem status, and the program status word of the management program indicates the supervisor status. Set it to be displayed.

When a privileged instruction is fetched in a problem state due to execution of an unauthorized program, a mechanism is provided that allows control to be handed over to the management program by determination without executing the instruction.

Therefore, the problem program needs to request processing services from the management program, at least for processing that requires the execution of privileged instructions. The transfer of control to the management program by the service processing, and the return of control to the problem program by the termination of the service processing, occur.

In such an environment, in order to debug a problem program, for example, if you specify that instruction execution should be stopped for each instruction and start execution of the problem program, the program will start executing the problem program while monitoring changes in the contents of the registers of the processing device. The problem program can be stepped through one instruction at a time to accomplish the purpose of the test.

FIG. 2 is a block diagram showing an example of the configuration of a stop designation mechanism. A test device 1 such as a service processor is sent to a processing device 2 by an instruction stop designation line 3 that specifies that execution should be stopped for each instruction, or an address stop designation line 4 that specifies that execution should be stopped when an access address matches. When an operation is designated, a stop designation latch 5 is set.

The output of the stop designation latch 5 and the instruction end line 7 outputted from the execution control unit 6 and indicating the end of execution of each instruction are ANDed by a gate 8 and outputted to a signal line 9.

This ON signal of the signal line 9 activates the stop control section 10,
The stop control unit 10 identifies a stop condition (not shown) specified by the test device 1, and sends an instruction increment signal from the test device 1 when the instruction stop is specified or when the addresses match in the address stop specification. The progress of the execution control section 6 is stopped until the receipt is taken.

When controlling the execution stop operation using such a mechanism, even if control is transferred from the problem program under test to the management program as described above, the increment specification for each instruction is valid, so the problem program If the test is to be continued even after recovery, it is necessary to manually advance one instruction at a time during the management program.

Alternatively, in order to avoid stepping for each instruction, for example, after setting a specification to stop at the return destination address of the problem program, ■ cancel the stop specification for each instruction, run the management program, and then After stopping at an address, it is necessary to reset the stop designation for each instruction, and in any case, there is a problem that the operation is complicated and takes time.

[Means for solving problems] FIG. 1 is a block diagram showing the configuration of the present invention.

In the figure, ■ is a test device, 20 is a processing device, and 2
Reference numeral 1 indicates a status bit that indicates the program execution state, and reference numeral 22 indicates a gate that outputs a signal to start the stop control section 10.

[For production]

From the test device 1, the stop designation latch 5 is connected in the same manner as before.
Set.

The status bit 21 is, for example, one bit in a program status word, and is on in a problem status and off in a supervisor status.

The gate 22 adds the signal of the status bit 21 to the conventional signals of the stop designation latch 5 and the instruction end line 7, performs an AND operation, and outputs the result to the signal line 23.

When the stop control unit 10 is activated by the ON signal on the signal line 23, stop control is executed in the same way as in the conventional case.

With the above configuration, even when a stop is specified, the signal line 23 is prevented from turning on when the status bit 21 is off, that is, in the supervisor state, so for example
The instruction-by-instruction step is automatically enabled only during problem programming, and the above problem is solved.

〔Example〕

In FIG. 1, a test device 1, an instruction stop designation line 3, an address stop designation line 4, and an execution control unit 6 in a processing device 20 are shown.
The stop control unit 10 and the like operate in the same manner as before.

The status bit 21 is, for example, one bit in the program status word, and is turned on in the problem status and off in the supervisor status. As the program status word is loaded into processor 20, status bit 21 indicates whether the program being executed is in problem or supervisor status.

When instruction stop or address stop is specified from the test device 1, the stop designation latch 5 is set in the same manner as in the conventional case.

The gate 22 adds the signal of the status bit 21 to the conventional signals of the stop designation latch 5 and the instruction end line 7, performs an AND operation, and outputs the result to the signal line 23.

When the stop control unit 10 is activated by the ON signal on the signal line 23, stop control is executed in the same way as in the conventional case.

With the above configuration, the signal line 23 is prevented from being turned on when the status bit 21 is off, that is, in the supervisor state, even when a stop is specified.

Note that if a latch 30 is provided to allow cents to be sent in an appropriate manner, if necessary, by turning on the latch 30, the stop designation will be valid regardless of the program execution state, as in the past. A usage mode can be provided.

In the above explanation, it was decided to perform control to suppress the stop specification based on the problem state and the supervisor state. For example, when running a known virtual machine, the state of the virtual machine and the hypervisor program that manages the virtual machine From the above explanation, it is easy to suppress the stop designation in the hypervisor program by identifying and displaying the state in which the hypervisor program is executed.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, an execution stop specification for the program execution state of a computer system is automatically made effective only for a program executed in a problem state, for example. Because it is controlled
It has a significant industrial effect of facilitating operation and improving test efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a conventional configuration. In the figure, 1 is a test device, 2.20 is a processing device, 3 is an instruction stop designation line, 4 is an address stop designation line, 5 is a stop designation latch, 6 is an execution control unit, 7 is an instruction end line,
8.22 is a gate, 9.23 is a signal line, 10 is a stop control section, 21 is a status bit, 30 is a latch Embodiment of the present invention tI? iJ block diagram (Fig. 1) Conventional 1-column block diagram (Fig. 2)

Claims (1)

[Claims] A processing device having a plurality of different program execution states,
When the stop designation for testing is set, if the program is in the specified execution state (21),
A stop operation inhibition control method, characterized in that it is configured to invalidate the stop designation.