JPH09146789A - Emulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an emulator which detects the error that is caused when a branch instruction is carried out and can shorten the debugging time by using a wrong branch address decision circuit. SOLUTION: A branch enabling flag storing memory 15 includes the addresses corresponding in 1-to-1 to every address of a memory ROM area of a target substrate and also stores the information to discriminate the addresses to which the accesses are permitted and not permitted respectively among those addresses related to the branch instructions. A branch address decision circuit 16 decides a branch address when the branch instruction is carried out. A wrong branch address decision circuit 18 detects the address errors at the time of execution of the branch instruction based on the information stored in the memory 15 and without delaying the execution of a target program. Thus it is possible to easily detect the error that is caused in regard to the address of the branch destination when the branch instruction, for example, is carried out and also to shorten the debugging time of the target program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulator used for supporting microcomputer program development.

[0002]

2. Description of the Related Art In program development in a microcomputer, an emulator is used to detect and correct errors in a target program. FIG. 6 is a conceptual diagram showing the connection relationship between the emulator, the target board, and the personal computer. In the figure, 41 is a target board created by the user, 42 is an emulator central processing unit that can output signals of an address bus, a data bus, a control signal line, and an input / output port on the target board 41 to the outside, and 43 is an emulator central processing unit. This is an emulator for controlling the execution of the target program based on the respective signals output from 42 to detect and correct errors in the target program. 43a is the emulator 4
3 is a target program memory for storing the target program. Reference numeral 44 is a personal computer that controls the emulator 43 and assembles the target program, and is equipped with an assembler for assembling the source program. The target program assembled by this assembler is the target of the emulator 43 via the communication cable 45. It is stored in the program memory 43a.

FIG. 7 is an explanatory diagram showing the correspondence relationship between the memory map of the memory on the target substrate 41 and the memory map of the target program memory 43a for storing the assembled target program. In the figure, 51 is a RAM area of the memory on the target substrate 41, 52 is an unused area of the memory on the target substrate 41, 53 is a ROM area of the memory on the target substrate 41, 54 is a data area of the target program memory 43a, 55 and 57 are unused areas of the target program, and 56 and 58 are program areas of the target program.

The emulator 43 is a program area 56, 58 of the target program memory 43a which stores the target program during execution of the target program.
Some data is written to the unused area 55,
It has a memory protection function of stopping the execution of the target program when 57 is accessed.

FIG. 8 is a block diagram showing the configuration of the emulator 43 which realizes the memory protection function. In the figure, 43c is a monitor circuit that constantly monitors the signal output from the emulator central processing unit 42, 43e is a memory for a memory protection function that sets the access conditions of the target program memory 43a, and 43d is the execution or execution of an instruction at a specified address. It is a break circuit that compares the access state of the address with the access condition of the memory 43e for memory protection function and stops the execution of the program when the access state is different from the access condition.

Next, the operation will be described. The user assembles the source program by the assembler of the personal computer 44 with the configuration shown in FIG. 6 and executes the assembled target program on the emulator 43 to find or correct an error in the target program. Before executing the above on the emulator 43, the user sets the access condition of the target program memory 43a storing the target program in the memory for memory protection function 43e in order to set the memory protection function. As a result, the target program memory 43a storing the target program
Of the program areas 56 and 58 are prohibited from being written, and unused areas 55 and 57 of the target program memory 43a are prohibited from being accessed, so that the memory protection function is established.

When the target program is executed on the emulator 43 with such a memory protection function set, the monitor circuit 43c causes the emulator central processing unit 4 to operate.
The signal of the address bus and the data bus output from 2 and the signal of the control signal line are constantly monitored, and the access state to the target program memory 43a indicated by the address being accessed and the access condition set to the memory 43e for the memory protection function are shown. Compare with. When the access conditions do not match, a control signal indicating that they do not match is sent to the break circuit 43d. In the break circuit 43d,
A signal for stopping the program being executed is sent to the emulator central processing unit 42 by the control signal sent from the monitor circuit 43c. When receiving the signal, the emulator central processing unit 42 stops the execution of the program and protects the target program memory 43a. Therefore, writing to the program areas 56 and 58 of the target program memory 43a storing the target program and accessing to the unused areas 55 and 57 (Fetch
/ Read / Write) is detected, an error in the target program is detected, and the target program memory 43a is protected by avoiding destruction of the target program and data stored in the target program memory 43a. It will be possible.

[0008]

Since the conventional emulator is constructed as described above, it detects an error in the target program and avoids destruction of the target program and data stored in the target program memory 43a. Can be protected by
For example, when a problem such as an illegal branch occurs due to a phenomenon in which originally correct data is transformed into erroneous data due to stack destruction or the like, an abnormality is detected when the branch destination area is the executable program area 56 or 58. There was a problem that I could not do it. That is, even if the branch destination program areas 56 and 58 are accessed due to such an illegal branch within the program areas 56 and 58 of the target program memory 43a, the state can be distinguished from the normal branch access. I can't do it,
The break circuit 43d does not operate, a program runaway may occur, and there is a problem that it takes time for debugging to search the cause when such a phenomenon occurs.

The present invention has been made in order to solve the above problems, and detects an error that occurs during execution of a branch instruction without affecting the time required for executing a target program, and the time required for debugging. The purpose is to obtain an emulator that can shorten.

[0010]

According to a first aspect of the present invention, there is provided an emulator for storing a branch permission flag having a one-to-one address corresponding to each address of a ROM area of a memory used as a target circuit. Identification information storage means for storing in advance the information for identifying the address permitted and the address not permitted as the address related to the branch instruction in the memory for storing the branch permission flag, and stored by the identification information storage means An incorrect branch address determination circuit for detecting an error related to access to the address when the branch instruction is executed without delaying execution of the target program based on the information obtained, and the incorrect branch address determination The target program when the circuit detects the error when the branch instruction is executed It is obtained by a break circuit for stopping the execution.

An emulator according to a second aspect of the present invention provides flag data set by "1" or "0" for identifying an address permitted and an address not permitted as an address related to a branch instruction, ROM of memory used for target circuit
The identification information storage means stores in advance a branch permission flag storage memory corresponding to each address of the area on a one-to-one basis.

An emulator according to a third aspect of the present invention detects an error relating to an address when the branch instruction is executed based on whether or not the absolute address is specified by an opcode of the branch instruction. Therefore, “1” or “0” is used to identify an address that is permitted to be accessed and an address that is not permitted as an address related to the branch instruction depending on whether or not the address is an absolute address designated by the opcode of the branch instruction. ROM of the memory used for the target circuit for the flag data set by
The identification information storage means stores in advance a branch permission flag storage memory corresponding to each address of the area on a one-to-one basis.

An emulator according to a fourth aspect of the present invention detects an error relating to an address when a branch instruction is executed based on whether the label is the start address of a program in which the label is defined. A flag set by "1" or "0" for distinguishing between an address which is permitted to be accessed and an address which is not permitted as an address related to the branch instruction depending on whether or not the label is the start address of the defined program ROM of memory used for the target circuit
The identification information storage means stores in advance a branch permission flag storage memory corresponding to each address of the area on a one-to-one basis.

An emulator according to a fifth aspect of the present invention detects an error related to an address when the branch instruction is executed based on whether or not the instruction address is the address next to the branch instruction to the subroutine. The address related to the branch instruction is set by "1" or "0" for distinguishing between the address which is permitted to access and the address which is not permitted according to whether or not it is the next instruction address of the branch instruction to the subroutine. ROM of the memory used for the target circuit for flag data
The identification information storage means stores in advance a branch permission flag storage memory corresponding to each address of the area on a one-to-one basis.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. 1 is a block diagram showing a configuration of an emulator according to a first embodiment of the present invention. In the figure, 11 is a central processing unit of the emulator, 12 is a monitor circuit (monitoring means) for constantly monitoring the signal output from the central processing unit of the emulator 11, 13 is a target program memory for storing the target program and data, and 14 is designated. When the instruction execution of the address or the illegal branch is performed, and the instruction execution of the specified address or the access status of the execution address is compared with the access condition of the memory 17 for the memory protection function, the access status is different from the access condition. In this case, the break circuit for stopping the execution of the target program, 15 has an address corresponding to each address of the ROM area of the memory on the target substrate on a one-to-one basis, and access is permitted as an address related to the branch instruction. Identify addresses and disallowed addresses A memory for storing a branch permission flag for storing information, 16 for a branch address discriminating circuit for discriminating a branch address when a branch instruction is executed, and 17 for the memory for memory protection function (memory protection means) for setting an access condition of the target program memory 13. , 18 is an erroneous branch address for detecting an error related to the address when the branch instruction is executed without delaying the execution of the target program based on the information stored in the memory 15 for storing the branch permission flag. Judgment circuit, 19 is a monitor circuit 12,
Target program memory 13, break circuit 14,
1 shows an emulator including a memory 15 for storing a branch permission flag, a branch address discrimination circuit 16, a memory 17 for a memory protection function, and the like. Reference numeral 20 is a personal computer for generating the information for identifying the address which is permitted to access and the address which is not permitted as the address related to the branch instruction in advance when assembling the source program and storing the information in the memory 15 for storing the branch permission flag. It is a computer (identification information storage means).

FIG. 2 is an explanatory diagram showing the correspondence relationship between the memory map of the memory on the target substrate and the memory map of the target program memory 13 for storing the assembled target program. In the figure, 2
1 is a RAM area of the memory on the target substrate, 22 is an unused area of the memory on the target substrate, 23 is a ROM area of the memory on the target substrate, 24 is a data area of the target program memory 13, and 25 and 27 are target programs. Unused area of memory 13, 26 and 28
Is a program area of the target program memory 13.

FIG. 3 is a block diagram showing a branch permission flag storage memory 15 in which a flag indicating whether or not branching is permitted is stored. In the figure, the flag "1" indicates that branching is possible, and the flag "0" indicates that branching is not possible.

FIG. 4 is a timing chart showing an address output on the address bus and data output on the data bus and control signals output to the read control signal line and the write control signal line when a branch instruction is executed. Is. In the figure, 31 is a signal output onto the address bus, which indicates the current execution address, 32 is the address of the branch destination output onto the address bus, 33 is the opcode of the branch instruction output onto the data bus, Reference numeral 34 is an operand of a branch instruction output onto the data bus, and a branch destination address designated by this can be referred to.

For assembling the source program shown in FIG. 5, the addresses permitted to be accessed in relation to the branch instruction are generated as a branch permission information file, and the addresses permitted to be accessed and the addresses not permitted are identified. Information of the flag is "1" when branching is possible to each address of the branch permission flag storing memory 15 corresponding to each address in the ROM area of the memory on the target substrate, and when branching is not possible, as shown in FIG. The flag is stored as "0". In this case, the address permitted to branch is (1) the absolute address specified by the operation code of the branch instruction, (2) the address where the label is defined, and (3) the instruction address next to the subroutine instruction as shown in FIG. Is.

Before executing the target program on the emulator, the user sets the access condition of the target program memory 13 storing the target program for the memory protection function to set the memory protection function as described in the prior art. Set in the memory 17. As a result, the program areas 26 and 28 of the target program memory 13 storing the target program are write-protected and the unused areas 25 and 27 are access-disabled, and the memory protection function is established.

Next, the break function in the emulator of the first embodiment will be described with reference to FIGS. 1, 2, and 3. Before executing the target program on the emulator, the user needs to assemble the program area 2 of the target program memory at the time of assembling the source program.
A flag indicating whether the branch is permitted or not is set in the branch permission flag storage memory 15 in a one-to-one correspondence with the addresses 6 and 28, as shown in FIG.

During execution of the target program, the branch address determination circuit 16 determines the branch destination address 32 output on the address bus. At this time, the flag set in the branch permission flag storage memory 15 of the branch destination address determined by the branch address determination circuit 16 is referred to. As a result, when the flag that is set indicates that branching is not possible, a control signal that indicates that the flag that is not branching is set is sent to the break circuit 14. When the break circuit 14 receives from the branch address determination circuit 16 a control signal indicating that the branch not possible flag is set, the break circuit 14 stops the execution of the target program.

Next, the case where the break circuit 14 operates to stop the execution of the target program will be specifically described. As described above, the address permitted to branch is (1) the absolute address specified by the operation code of the branch instruction, (2) the address in which the label is defined, and (3) the instruction address next to the subroutine instruction. The case where the break circuit 14 operates by not satisfying the condition (2) is as follows.

That is, since the address in which the label is defined is the start address of the branch destination program,
Since this start address must be permitted as a branch destination, the flag set in the branch permission flag storage memory 15 for this start address is, of course, the flag "1" permitted as the branch destination address.
Is set. Therefore, when an error occurs in which an originally correct address changes to an incorrect address and the branch does not branch to the address in which the label is defined, the break circuit 14 operates and branching to an incorrect branch destination is effective. Will be avoided.

The case where the break circuit 14 operates by not satisfying the condition (3) is as follows.

That is, in the conventional emulator, when an error occurs in the address stored in the stack, an error occurs in the stack pointer, or an error occurs due to hardware, the address changed by the error is stored in the program area. In some cases, the memory protection function does not operate and the break circuit does not operate, which may result in a runaway state. However, in the first embodiment, the branch destination address is further branched. The break circuit operates by taking into account the condition of whether the address is allowed or not allowed to branch, so when returning to the wrong branch destination address due to stack destruction, etc., the branch enable flag is stored for that address. As long as the flag indicating that branching is not possible is set in the memory 15 for break, the break circuit 1
It is possible to effectively avoid runaway or the like due to the operation of 4 and returning to the wrong return address.

As described above, according to the emulator of the first embodiment, the execution of the target program is immediately stopped when an erroneous branch is attempted, so that the runaway due to the erroneous branch can be effectively avoided. There is an effect that can be.

[0028]

As described above, according to the first aspect of the invention, the RO of the memory used in the target circuit is RO.
Information for identifying an address permitted and an address not permitted as an address related to a branch instruction is stored in advance in the branch permission flag storage memory corresponding to each address in the M area by the identification information storage means, An error related to the address when the branch instruction is executed based on the stored information without delaying the execution of the target program is detected by an erroneous branch address determination circuit, and a break circuit is used to detect the target program. Since the execution is configured to be stopped, it is possible to easily know, for example, an error that occurs in relation to the branch destination address when the branch instruction is executed, and it is possible to shorten the time required for debugging the target program. effective.

According to the second aspect of the present invention, the branch information is stored in the branch permission flag storage memory corresponding to each address in the ROM area of the memory used as the target circuit in a one-to-one relationship with the branch instruction in advance by the identification information storage means. The flag data set by "1" or "0" for discriminating between the access-permitted address and the access-disabled address is stored in advance, and the stored data is stored without delaying the execution of the target program. Since the error related to the access to the address when the branch instruction is executed based on the flag data is detected by the erroneous branch address determination circuit, and the break circuit is configured to stop the execution of the target program, The error relating to the access to the address when the branch instruction is executed Lag data can be easily known based on, which reduces the time required for debugging of the target program.

According to the third aspect of the present invention, the branch information of the branch instruction flag is stored in advance in the branch permission flag storing memory corresponding to each address of the ROM area of the memory used as the target circuit by the identification information storing means. The flag data set by "1" or "0" for identifying the address permitted and the address not permitted according to whether or not the address is an absolute address designated by the code is stored in advance and stored in the target program. An error occurring in the access to the absolute address when the branch instruction is executed based on the stored flag data without delaying the execution is detected by an erroneous branch address determination circuit, and the target program is executed by a break circuit. Since the execution of the branch instruction is stopped, the operation when the branch instruction is executed is executed. An error occurring in accessing the absolute address specified in the over-de can be easily known, which reduces the time required for debugging of the target program.

According to the fourth aspect of the present invention, the label is previously defined by the identification information storage means in the branch permission flag storage memory corresponding to each address of the ROM area of the memory used as the target circuit in a one-to-one correspondence. The flag data set by "1" or "0" for distinguishing between the access-permitted address and the access-disabled address depending on whether the program is the start address or not is stored and the target program is executed. An error caused by accessing the start address of the program in which the label is defined when the branch instruction is executed based on the stored flag data without delay is detected by an erroneous branch address determination circuit, The break circuit is configured to stop the execution of the target program. , The branch instruction is an error can be known facilitate caused to access the leading address of the program labels when executed is defined, which reduces the time required for debugging of the target program.

According to the fifth aspect of the present invention, a branch permission flag storage memory corresponding to each address of the ROM area of the memory used as the target circuit is provided one-to-one with the identification information storage means to branch to a subroutine in advance. The flag data set by "1" or "0" that distinguishes the address permitted and the address not permitted depending on whether the instruction address is the next instruction address or not is stored, and the target program is executed. An error occurring in the access to the next instruction address of the branch instruction to the subroutine when the branch instruction is executed based on the stored flag data without delay is detected by an erroneous branch address determination circuit, Since the break circuit is configured to stop the execution of the target program, It is easy to know the error that occurs in accessing the next instruction address of the branch instruction to Brutin, especially the error caused by the error that occurred in the data in the stack, and the time required for debugging. There is an effect that can shorten.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an emulator according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a correspondence relationship between a memory map of a memory on a target substrate of the emulator according to the first embodiment of the present invention and a memory map of a target program memory for storing an assembled target program.

FIG. 3 is a configuration diagram of a branch permission flag storage memory in which a flag indicating whether branching of the emulator is permitted or not permitted according to the first embodiment of the present invention is set.

FIG. 4 is an address output on an address bus and data output on a data bus and a read control signal line and a write control signal line when a branch instruction is executed by the emulator according to the first embodiment of the present invention. FIG. 6 is a timing diagram showing control signals according to the present invention.

FIG. 5 is an explanatory diagram showing a configuration of a source program by the emulator according to the first embodiment of the present invention.

FIG. 6 is a conceptual diagram showing a connection relationship between a target board and a personal computer in a conventional emulator.

FIG. 7 is an explanatory diagram showing a correspondence relationship between a memory map of a memory on a target board in a conventional emulator and a memory map of a target program memory that stores an assembled target program.

FIG. 8 is a block diagram showing a configuration of a conventional emulator.

[Explanation of symbols]

12 monitor circuit (monitor means), 13 target program memory, 14 break circuit, 15 branch enable flag storage memory, 17 memory protection function memory (memory protection means), 18 incorrect branch address determination circuit, 19
Emulator, 20 Personal computer (identification information storage means).

Claims (5)

[Claims] 1. A target program memory for storing a target program for operating a target circuit, monitor means for monitoring various data when the circuit operates by executing the target program, and the monitor means. In an emulator provided with a memory protection unit that detects an erroneous access to the target program memory by the target program based on the obtained monitor result, in each address of the ROM area of the memory used for the target circuit. A memory for storing a branch permission flag having an address corresponding to one-to-one and information for identifying an address which is permitted to be accessed and an address which is not permitted as an address related to a branch instruction are stored in the memory for storing the branch permission flag in advance. Identification information store And a false branch for detecting an error related to access to the address when the branch instruction is executed without delaying execution of the target program based on the information stored by the identification information storage means. An emulator comprising: an address determination circuit; and a break circuit that stops execution of the target program when the incorrect branch address determination circuit detects the error when the branch instruction is executed. 2. The information stored in advance in the branch permission flag storage memory by the identification information storage means is "1" or "1" for identifying an address which is permitted to be accessed and an address which is not permitted as an address related to a branch instruction. 0 "
The emulator according to claim 1, wherein the emulator is flag data set by. 3. The emulator according to claim 2, wherein the address related to the branch instruction is an absolute address designated by the opcode of the branch instruction. 4. The emulator according to claim 2, wherein the address related to the branch instruction is a start address of a program in which a label is defined. 5. The emulator according to claim 2, wherein the address related to the branch instruction is the instruction address next to the branch instruction to the subroutine.