JP2808757B2 - Microprocessor for debugging - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debug microprocessor, and more particularly to a debug interrupt generation circuit.

[Conventional technology]

As a means for improving the performance of a conventional microprocessor, there is a method using a pipeline structure. The inside of a microprocessor with this pipeline structure is
The unit is divided into units having independent functions, and the units are connected so as to operate in parallel.

FIG. 3 is a block diagram of a basic example of a microprocessor 23 having a conventional pipeline structure. First, the operation of each unit will be described. Bus control unit 2
Is a unit for transferring data to and from the external memory and peripheral devices of the microprocessor 23. The prefetch unit 3 is a unit for controlling prefetching of instruction codes, and stores prefetched instructions in a buffer in the prefetch unit 3. Keep it. The instruction decode unit 4 sequentially fetches instructions prefetched into the buffer in the prefetch unit 3 and decodes them into a data format for the next execution unit 5. The execution unit 5 is a unit that executes according to the decoded instruction.

There is a method of using a break for debugging a program using an in-circuit emulator. This break will be described. An address (breakpoint) at which the user program is stopped during execution of the monitor program of the in-circuit emulator is set. A break detection circuit for executing the user program and detecting an address at which execution of the user program is stopped causes an interrupt to be generated after an instruction at which a breakpoint is set is executed, and transfers control of the instruction to the monitor program. , A function for performing processing such as viewing the contents of a register or the contents of a memory.

FIG. 4 is a block diagram showing a flow of a break operation of the debug microprocessor having the pipeline structure of FIG. Data bus 8 by bus control unit 2
When the fetch from is performed, the address is obtained by the break detection circuit 21 outside the debug microprocessor 1a.
An external break (external interrupt) signal 6, which is made active when the address matches the breakpoint address, is simultaneously taken into the prefetch unit 3. The information of the external break signal 6 is carried to the execution unit 5 together with the fetched instruction 22.

An instruction execution unit 9 and an interrupt processing unit are provided in the execution unit 5.
The instruction execution processing unit 9 is where the instruction is actually executed, and the interrupt processing unit 17 performs processing such as generation of an interrupt. After the instruction is executed by the instruction execution processing unit 9 in the execution unit 5, the instruction execution processing unit 9 outputs an instruction execution end signal 19. At this timing, the output of the DF / F 24 is input to the interrupt processing unit 17, and an interrupt is generated when active, that is, when a breakpoint has been set in the currently executed instruction.

Here, consider the case of debugging a program described in a high-level language. For debugging a program described in a high-level language, a high-level language debugger capable of debugging at a high-level language level is used. When using a breakpoint with a high-level language debugger, a break is often made at the head of a specified line. Since one line of a high-level language is expanded into several machine language instructions, to break at the beginning of one line of a high-level language, break just before the first machine language instruction is executed. Must-have. However, the conventional debug microprocessor breaks after executing an instruction, so that it is not possible to set a breakpoint at the first instruction of one line of a high-level language. For this reason, conventionally, in order to perform a break at the beginning of one line of a high-level language, single-step execution is performed using a break function of a debug microprocessor. By executing a machine language instruction step by step, and comparing the program counter after execution of the instruction with the head address of the line to be broken, it is determined at each step execution whether a high-level language breakpoint has been reached. A break is occurring.

[Problems to be solved by the invention]

As described above, in the conventional high-level language break function, the program is executed in a single step, the software determines whether the breakpoint of the high-level language has been reached, and a break is generated. There was a problem that emulation in real time was not possible.

An object of the present invention is to solve such a problem, and to input an interrupt request signal for requesting the execution of an instruction to generate an interrupt,
A debugging microprocessor that has a circuit for selecting whether an interrupt is generated before execution of an instruction or after an instruction is executed, thereby enabling an interrupt to be generated even before the fetched instruction is executed. Is to provide.

[Means for solving the problem]

According to the configuration of the present invention, when there is a debug interrupt generation request from the outside of the microprocessor for an instruction code fetched by the microprocessor, processing up to execution of the instruction code and execution of the interrupt request are performed internally. In the debug microprocessor synchronizing the above processes, the debug microprocessor generates the debug interrupt before the instruction is executed by using the external debug interrupt request signal and the signal indicating immediately before the execution of the instruction code. A first interrupt request signal to be requested and a second interrupt request signal generated using the first interrupt request signal and a signal indicating the end of execution of the instruction and requesting generation of a debug interrupt after execution of the instruction. An interrupt request signal generating circuit for outputting each of them; The output of the static, and having a selection circuit for selecting one of said first and second interrupt request signals.

In the present invention, an interrupt request creation circuit includes a first flip-flop that outputs a first interrupt request signal using a debug interrupt request signal as a data input, an instruction input signal as a clock input, and an output of the first flip-flop. And a second flip-flop that outputs a second interrupt request signal using the instruction execution end signal as a clock input and a command execution end signal as a clock input.

〔Example〕

FIG. 1 is a block diagram of one embodiment of the present invention. The difference between this embodiment and the debug microprocessor 1a of FIG. 4 will be described. In the conventional example, the information of the external break signal 6 is input to the interrupt processing unit 17 at the timing when the instruction execution end signal 19 for notifying the end of the instruction execution from the instruction execution processing unit 9 in the execution unit 5 is output. In this embodiment, a signal indicating that an instruction has entered the execution unit 5 from the instruction decoding unit 4 is newly generated, so that an interrupt can be generated before the instruction is executed.

In the figure, a case where a breakpoint is set for an instruction taken in the execution unit 5 will be described.
When a fetch from the data bus 8 is performed by the bus control unit 2, the external break signal 6 is activated by the break detection circuit 21 external to the debug microprocessor 1. This information is taken into the prefetch unit 3 simultaneously with the fetched instruction 22. The information of the external break signal 6 is carried to the execution unit 5 together with the fetched information.

The transfer of information from the instruction code unit 4 to the execution unit 5 will be described with reference to the schematic diagram of FIG. Inside the instruction code unit 4, there is a buffer 27 having information on the decoded instruction 25 and the external break signal 6. This information is stored in the instruction execution processing unit 9 in the execution unit 5,
It is sent to the interrupt control unit 26. The instruction decode unit 4 activates the instruction input signal 18 when sending the information of the decoded instruction 25 and the external break signal 6 to the execution unit 5. This instruction input signal 18 is also
It is sent to 26.

Next, when the execution of the fetched instruction is completed, the instruction execution processing unit 9 activates the instruction execution end signal 19.

Two signals, an instruction input signal 18 and an execution end signal 19, are input to DF / F10 and DF / F11, respectively. Since the external break signal 6 is now active, that is, a breakpoint is set in the instruction taken into the instruction execution processing unit 9, the output of the DF / F 10 is output when the instruction input signal 18 is output. Become active. Next, when the execution of the instruction taken into the instruction execution processing unit 9 is completed, the output of the DF / F 11 becomes active when the instruction execution end signal 19 is output. The outputs of the DF / Fs 10 and 11 are the inputs A and
Input as input B. The selector 14 selects either the input A or the input B of the selector by the selection input 15 from the register 16 and determines whether to generate an interrupt when the instruction enters the execution unit 5 or when the instruction is executed. Is completed, that is, whether the interrupt is generated immediately before the execution of the instruction or immediately after the execution of the instruction.

An interrupt is generated by activating the output from the selector 14 to the interrupt processing unit 17. Upon receiving the interrupt generation request, the interrupt processing unit 17 suspends execution of the subsequent instruction and shifts execution to another address.

〔The invention's effect〕

As described above, in the present invention, in the debug microprocessor, the point of occurrence of the interrupt can be set immediately before the execution of the instruction at the breakpoint or immediately after the execution of the instruction.
By setting a breakpoint in the first machine language instruction of a high-level language one line, an interrupt can be made immediately before the high-level language one line is executed. By using such a break function of the debug microprocessor, an execution speed can be increased and a real-time high-level language debugger can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
FIG. 1 is a schematic diagram showing the exchange of information between the instruction decode unit 4 and the execution unit 5 in FIG. 1, FIG. 3 is a block diagram of an example of a conventional microprocessor having a pipeline structure, and FIG. FIG. 2 is a block diagram showing in detail an execution unit 5 in FIG. 1, 1a microprocessor, 2 bus control unit, 3 prefetch unit, 4 instruction decode unit, 5 execution unit, 6 external break signal, 7 address bus, 8 Data bus, 9 ... instruction execution processing unit, 10, 11, 24 ... DF / F, 14 ... selector, 15 ... selection input, 16 ... register, 17 ... interrupt processing unit, 18 ... Command input signal, 19 …… Command execution end signal,
21: Break detection circuit, 22: Fetched instruction,
23: microprocessor, 25: decoded instruction, 26: interrupt control unit.

Claims (2)

(57) [Claims] When a debug interrupt generation request is issued from the outside of a microprocessor to an instruction code fetched by a microprocessor, processing up to execution of the instruction code and execution of the interrupt request are executed internally. In the debug microprocessor synchronizing the processing, a debug interrupt request signal is generated using the external debug interrupt request signal and a signal notifying immediately before the execution of the instruction code. A second interrupt request signal generated by using the first interrupt request signal to be executed and a signal notifying the end of execution of the instruction, and requesting generation of a debug interrupt after execution of the instruction.
And a second interrupt request signal generating circuit for outputting the first and second interrupt request signals, and an output of a register provided inside the microprocessor for giving a switching command.
And a selection circuit for selecting one of the interrupt request signals. 2. An interrupt request generation circuit comprising: a first flip-flop for outputting a first interrupt request signal using a debug interrupt request signal as a data input, an instruction input signal as a clock input, and a first flip-flop. 2. The debug microprocessor according to claim 1, further comprising: a second flip-flop that outputs a data input and outputs a second interrupt request signal by using an instruction execution end signal as a clock input.