JPH0659934A - Program evaluating microcomputer - Google Patents

Abstract

PURPOSE:To provide a program evaluating microcomputer capable of breaking an expected address without requiring many control circuits or complex control by providing a command with an instruction queue having a queue format, prereading an instruction code and executing pipeline processing. CONSTITUTION:The program evaluating microcomputer A is constituted of a queue 10 for storing an instruction code and an address break request signal corresponding to an address outputted from the microcomputer itself, a break control circuit 12 for inputting an address break request signal from the queue 10, judging whether an instruction code inputted together with the address break request signal is to be executed next or not and outputting the judged result and a breaking circuit 14 for stopping the execution of a program at the time of inputting the judged result that the instruction code inputted together with the address break request signal is to be exerted next.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ICE (in-circuit emulator) used for program development of a one-chip microcontroller (hereinafter referred to as a microcomputer).
The program evaluation microcomputer incorporated in the (tor).

[0002]

2. Description of the Related Art A program evaluation microcomputer is an IC used when a program for a one-chip microcomputer is developed.
It is built into the E and operates like an ordinary one-chip microcomputer, and has a special control terminal for evaluating a program.

The control terminal has a function for stopping the operation of the program evaluation microcomputer, an instruction bus for reading an instruction code (instruction code), a monitor bus for monitoring the operation of the microcomputer, and the like. By controlling these control terminals by ICE commands, the contents of the internal registers and data memory of the program evaluation microcomputer are displayed / changed, and the data output from the monitor bus during execution of the user program is traced. This makes it possible to debug the program created by the user.

The ICE function has a break function by an address, and FIG. 2 shows a functional block which has conventionally realized this break function.

Conventionally, a program evaluation microcomputer is provided with a break control circuit 24 and a break circuit 26 for realizing a break function. The break control circuit 24 is a circuit that controls the break circuit 26, and is connected to a break input signal line 312 to which a break signal is input from the outside.

The break circuit 26 has a clock input line 31.
4, a signal line for outputting the control clock 316 and a signal line from the break control circuit 24 are connected, and the control clock 316 is stopped by a signal from the break control circuit 24. The address bus 300 is an address output bus of the program evaluation microcomputer.

The address comparison unit 20 includes an address bus 30.
It is checked whether the address output to 0 matches the address to be broken, and if they match, a signal indicating the match is output to the address break signal line 310.
The break control circuit 24 uses the address break signal line 31.
0 and other break signal lines (not shown) are connected, and when the break signal corresponding to the specified break factor is input, the break signal is output to the break signal input line 312.

Next, the operation of the prior art will be described. First, the address to be broken in the address comparison unit 20 is set in advance in the break control unit 24 as the break factor. In this state, the program evaluation microcomputer is operated to execute the user program. The address output from the program evaluation microcomputer to the address bus 300 is compared with the address comparison unit 20.
It is checked whether or not the address matches the address to be broken, and if they match, an address break signal indicating an address match is output to the address break signal line 310.

In the break control unit 22, since the address break as a cause of the break is valid, when the address break signal is input, the break signal input line 312 is input.
The break signal is output to. When the break signal is input to the break control circuit 24 in the program evaluation microcomputer, the break control circuit 24 generates a timing signal for stopping (breaking) the program evaluation microcomputer, and the break signal is sent to the break circuit 26 as a break timing signal. send. The break circuit 26 stops the control clock 36 by the break timing signal sent from the break control circuit 24.

By the above operation, the operation of the program evaluation microcomputer is stopped and the break is established.

In addition to this, there is an instruction replacement method as a break method. With this method, when the program evaluation microcomputer reads the user program corresponding to the address you want to break, another instruction (jump instruction, etc.) is forcibly read and the control program prepared separately from the user program is executed. To make a break.

[0012]

However, in such a conventional technique, a command evaluation microcomputer in which a command has a queue form is used to pre-read instruction codes and perform pipeline processing. In this case, the instruction code of the address output from the address bus is different from the instruction code actually executed, so that the instruction code of the expected address could not be broken at the time of execution.

Further, in order to establish an address break by the conventional method, complicated control is required together with a control circuit such as an address holding circuit and instruction bus switching for replacing instruction codes.

The present invention solves the problems of the prior art as described above, and has many program evaluation microcomputers that have an instruction queue in which commands are in the form of a queue and prefetch instruction codes and perform pipeline processing. It is an object of the present invention to provide a program evaluation microcomputer that can break at an expected address without requiring the control circuit or complicated control.

[0015]

According to the present invention, in order to solve the above-mentioned problems, a program evaluation microcomputer applied to a debugging device used for program development corresponds to an address output from the program evaluation microcomputer. The instruction code to be stored is stored in the queue buffer, and if there is an address break request signal for requesting an address break, the storing means for storing this address break request signal together with the instruction code in the queue buffer, and the address break from the storing means. Break control means for inputting a request signal and judging and outputting whether or not the instruction code input together with this address break request signal is executed, and said instruction code inputted together with the address break request signal from the break control means Input the judgment result that is executed next , And a break means for stopping the execution of the program.

[0016]

According to the present invention, when the address output from the program evaluation microcomputer is the address to be broken, the address break request signal is output to the storage means.
When the storage means receives this request signal, it stores it together with the instruction code at that time. After that, the address break request signal is output to the break control means after the instruction stored in the storage means is executed. Then, when the break control means outputs the determination result that the instruction code is to be executed next, the break means stops the execution of the program.

[0017]

Embodiments of the program evaluation microcomputer according to the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a functional block diagram showing an embodiment of a program evaluation microcomputer according to the present invention. In the figure, an address bus 100 is an address output bus of a program evaluation microcomputer and is usually connected to an address line (not shown) of a memory. The instruction bus 102 is an instruction code (instruction code).
Is a bus for inputting to the program evaluation microcomputer,
Queue (command queue) in the program evaluation microcomputer 1
It is connected to 0. Address break signal input line 11
0 is an address break signal dedicated input line connected to the queue 10.

The break signal input line 112 is connected to the break control circuit 12, and when a break other than the address break occurs, a break signal is output via this signal line. The clock input line 114 is a signal line for inputting a basic clock for operating the program evaluation microcomputer, and is connected to the break circuit 14, and the input basic clock is output as a control clock 216 via the break circuit 14. The output of the queue 10 is the data bus 20.
0 and the break control circuit 12 are connected to the queue 1
The instruction code in 0 is the data bus 200
The address break signal is output to the break control circuit 12.

The data bus 200 is a main bus of the program evaluation microcomputer and is connected to an arithmetic circuit, a control circuit, a timer / register, a data register, an instruction register and the like (all not shown). The jump command signal 210, the STOP control signal 212, and the interrupt control signal 214 are signals that are input to the break control circuit 12 and indicate that a jump command, STOP, and an interrupt have occurred, respectively.

The program evaluation microcomputer operates by the control clock 216. Therefore, by stopping the control clock 216, it is possible to stop the execution of the program, that is, break the program.

When the program evaluation microcomputer is operated, an address is output from the address bus 100. The instruction code corresponding to the output address is queued 1 via the instruction bus 102.
Input to 0. The queue 10 has a structure of several stages and can store instruction codes for several instructions.

For example, in the case of a three-stage queue, three instruction codes can be stored. The instruction code stored in the queue is output to the data bus 200 and executed at a certain timing.
When there is a space in the queue 10, the address changes and the instruction code is read. The program evaluation microcomputer repeats the above operation to execute the program.

If the address output from the address bus 100 is the address to be broken, the address break signal input line 110 outputs an "H" level address break request signal. For example, the address break request signal is read into the queue 10 together with the instruction code input via the instruction bus 102.

The instruction code and address break request signal read in the queue 10 are usually
In the case of a three-stage queue, an instruction code is output to the data bus 200 and an address break request signal is output to the break control circuit 12 after execution of three instructions. However, in the case of an instruction for re-reading the instruction code such as a jump instruction or interrupt execution, the contents of the queue 10 are all cleared.

When the address break request signal is input, the break control circuit 12 determines whether the instruction code input together with the address break request signal will be executed next. The jump instruction signal 210 and the STOP control signal 2
12, the interrupt control signal 214 or the like. Then, if this instruction code is executed, a timing signal for breaking is generated and the break timing signal is sent to the break circuit 14. However, if a STOP, interrupt, jump instruction or the like occurs and the instruction code for which the break request is issued is not executed, the break request is canceled.

A break request signal is input from the break signal input line 112 except for the break related to the address (asynchronous break). Even in this case, STOP
When an interrupt is generated by the control signal 212 and the interrupt control signal 214, the break request is held, and the break request is controlled by outputting a break timing signal after transition to the interrupt. The break circuit 14 stops the control clock 216 when the break timing signal sent from the break control circuit 12 is input. This causes the program execution to stop (break).

[0028]

As described above, according to the program evaluation microcomputer of the present invention, the address break request signal is queued in the storage means together with the instruction code from the input terminal dedicated to the break related to the address (the break synchronized with the address). input. As a result, even if the execution address and the address output to the address bus are different or there is no timing to input the break signal, such as a program evaluation microcomputer that has an instruction queue and prefetches instruction codes to perform pipeline processing. Debug processing becomes possible.

Further, since the program evaluation microcomputer is stopped, there is no change in data inside the program evaluation microcomputer due to the instruction replacement method. As described above, according to the present invention, the program evaluation microcomputer can be broken easily and accurately, so that the use condition of the ICE is eliminated and the debugging efficiency of the program can be improved.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an embodiment of a program evaluation microcomputer according to the present invention.

FIG. 2 is a functional block diagram showing an embodiment of a program evaluation microcomputer in the prior art.

[Explanation of symbols]

 10 queues 12 break control circuit 14 break circuit 100 address bus 102 instruction bus 110 address break signal input line 112 break signal input line 114 clock input line 210 jump command signal 212 STOP control signal 214 interrupt control signal 216 control clock

Claims (1)

[Claims] 1. In a program evaluation microcomputer applied to a debugging device used for program development, an instruction code corresponding to an address output from the program evaluation microcomputer is stored in a queue buffer and an address break is requested. When there is an address break request signal to be stored, a storage means for storing the address break request signal in a queue buffer together with the instruction code, and the address break request signal from the storage means are input, together with the address break request signal. Break control means for judging and outputting whether or not the inputted instruction code is executed next, and judgment that the instruction code inputted together with the address break request signal from the break control means is executed next. When you enter the result, A program evaluation microcomputer having break means for stopping execution.