JPH0315948A - Address bus test system - Google Patents

Abstract

PURPOSE:To test the fault of an address bus by providing a comparison circuit comparing an address bus signal, a flip flop circuit for holding a result and a control signal generation circuit controlling a timing. CONSTITUTION:The title system consists of a central processing unit 1 executing a program, a storage circuit 2 storing the program, the comparison circuit 4 comparing the address bus 12 signal from an input/output controller of every kinds with a signal from an input/output controller 3, the flip flop 6 holding the result of the comparison circuit 4 and the control signal generation circuit 5 outputting various timing signals for holding the result. An address '0' and all addresses that the address bus 12 comes to '1' are set in the address bus 12 and the signal from the input/output controller 3 is compared with the signal of the address bus 12. Thus, the abnormal operation of the program and the fault of the address bus can be speedily tested.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer address bus test method.

[Conventional technology]

Conventionally, this type of address bus test consists of a central processing unit that executes a program, a memory circuit that stores the program, and various input/output control devices.
A failure in which it is fixed to “o” or “1” is
Writes data from the central processing unit to an address in the memory circuit, then reads the data and writes the written data.
The address bus was tested by comparing it with

[Problem that the invention seeks to solve]

In the conventional address bus test described above, when a failure occurs, the failure location is the memory circuit. It was not possible to determine whether it was the data path or the address bus. Especially WORK
When the area is at an older address than the program area, WORK the bits of addresses that are not used in the program area.
When used as an area address, there is a drawback that the program appears to operate normally even if this bit is abnormal. For example, if the program area is from address O to 1000 (
H) Address (address bus 212 bits only “1”) WO
The RK area is address 1001 (H) (address bus 2
'2+2' Bit is "1"> to 3000
(H) Address (address bus 213212Bit is “1”
) program, the address bus is 213 Bits.
is fixed to "O", 212Bit remains ゜゛O'' in the program area and operates normally, but when the contents of address 3000 (H) of the WORK area are read from the program area, 213Bit is fixed to ``0''. Therefore, the contents of address 1000 (H) will be read and the operation will be performed using abnormal data.

[Means for solving problems]

The address bus test method of the present invention includes a central processing unit that executes a program, a storage circuit that stores the program,
A comparison circuit that compares address bus signals from various input/output control devices with signals from the input/output control device, a flip-flop that holds the results of the comparison circuit, and outputs various timing signals to hold the results. It consists of a control signal generation circuit, sets an address where the O address and the address bus are all "'1" on the address bus, and compares the signal line from the input/output device with the address bus signal. There is.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In the figure, a central processing unit 1, a memory circuit 2, an input/output control device 3, a comparison circuit 4
, control signal generation circuit 5, flip-flops 6, 7, AN
D circuit 8, signal inversion circuit 9, 10.11, address bus line 12. Data path line 13. memory request line 14,
IO request line 15, lead line 16, write line 17 memory lead line 18, memory write line 19, IO lead line 20, work write line 21, machine cycle it! ! 22
, result output lines 23, 28 . It is composed of a comparison data line 24, gate lines 25 and 27, and a result holding line 26.

FIG. 2 is a diagram showing the processing flow of the program stored in the storage circuit 2. As shown in FIG. The central processing unit 1 sequentially loads programs from the storage circuit 2 and executes them. Step 30 in FIG. 2 sets address O in a register inside the central processing unit 1.

Since the program at step 31 in FIG. 2 reads the instruction code from the memory circuit 2, the address bus line 1 is
2, sends the contents of the program counter. Next, the central processing unit 1 sends signals to the memory request line 14, lead line 16, and machine cycle 1 line 22 in order to read the contents of the memory circuit 2 indicated by the program counter.

Signals on the memory request line 14 and lead line 16 are input to the control signal generation circuit 5, converted into a memory read signal, and input to the memory circuit 2 through the memory lead line 18.

When the memory circuit 2 receives this signal, it sends the contents of the memory circuit (instruction code) to the data path line 13, and the central processing unit 1 receives this instruction code and knows that it is an output instruction. If it is an output command, in order to read the address of the output device from the memory circuit 2, the central processing unit 1 sends a signal to the memory request line 14 and lead line 16 as soon as it sends the address of the program counter +1 to the address bus line 12. Send out. (At this time, machine cycle 1 line 22
No signal is sent. This signal on the machine cycle 1 line 22 is a signal sent only when reading an instruction code. > These signals are converted into memory read signals by the control signal generation circuit 5, passed through the memory lead wire 18,
The contents of the memory circuit are sent from the memory circuit 2 to the data path line 13, and are read by the central processing unit 1.

When the address of the output device is known in the central processing unit 1, the central processing unit 1 sends the address of the output device already read on the address line 12, and then sends the address of the output device already read on the address line 12, and then on the data path line 13.
Comparison data shown in step 31 of Fig. 2 and gate ON
The data is sent, and then signals are sent to the E/○ request line 16 and write line 18. This signal is converted into a memory read signal by the control signal generation circuit 5 and the memory lead line 1
8 and is input to the memory circuit 2 and simultaneously input to the AND circuit 8. The memory circuit 2 sends the contents of address 0 to the data bus 13 and is read by the central processing unit 1, but this content is invalidated in the program. Furthermore, only memory reading does not affect the program. On the other hand, A
The memory read signal input to the ND circuit 8 is reset to the flip-flop 7 by the gate ON signal set in the input/output control device 3, and the output signal of the flip-flop 7 passes through the gate line 27 and the signal inversion circuit 11. , since the gate of the AND circuit 8 is ON, the result is output to the AND circuit 8 and then to the result holding line 26. At this time, the address O has already been output to the address bus line 12, and this address O is also input to the comparison circuit 4, and the comparison circuit 4 compares it with the signal O passed through the comparison data line 24, and if it is normal, the O address is output. , if it is abnormal, 1 is output to the result output line 28 and input to the flip-flop 6. This signal is set to the flip-flop 6 by the signal output to the result latch line 26, and is input through the result output line 23. It is input to the output control device 3. On the other hand, the signal passing through the result latch line 26 is transferred to the signal inverting circuit 1.
0 and operates the flip-flop 7. The output signal of the flip-flop 7 passes through the gate line 27 and the signal inversion circuit 11 to turn off the gate of the AND circuit 8. Next, in order to read the result using the program in step 33 of FIG. 2, the central processing unit 1 reads the instruction code from the memory circuit 2 as described above, determines it as an input command, and then reads the contents of the memory circuit 2 and addresses the input device address. Know the address bus line l
2, and then sends the input device address to the IO request line 15. A signal is sent to the lead wire 16, and this signal is converted into a ■○ lead signal in the signal generating circuit 5, output to the IO lead wire 20, and inputted to the input/output control device 3. The input/output control device 3, which has achieved an address match with the input device address output to the address bus line, outputs the data from the result output line 23 to the data path line 13 by the above-mentioned ■○ read signal, and sends this result to the central Processor l takes the lead. At step 34 in FIG. 3, the result is judged and, if abnormal, the abnormality processing at step 42 in FIG. 2 is executed. Also, if it is normal, the game is 1-OF at Step 35 in Figure 2.
In order to turn the gate OFF, when the gate is turned OFF in the manner described above for turning ON the gate in FIG. 2, the gate line 25 of the input/output control device 3 turns OFF
The gate of the AND circuit 8 is turned OFF, the flip-flop 6.7 is reset, and the circuit becomes operable.

As described above, by setting the address O on the address bus line 12, setting the comparison data to O, and comparing, a fault fixed to 1 on the address bus line 12 can be found. On the other hand, the operations in steps 36 to 41 in Fig. 2 are performed in steps 30 to 35 in Fig. 2.
By setting the address FFFF on the address bus line 12, setting the comparison data 1, and comparing, it is possible to identify a fault that is fixed to 0 on the address bus line 12.

〔Effect of the invention〕

As explained above, the present invention does not require any modification of the conventional circuit by simply adding a comparison circuit for comparing address bus signals, a flip-flop circuit for holding the results, and a control signal generation circuit for controlling timing. By simply adding a program that judges address bus test results as an extension of the conventional functionality without making any changes, it is effective to quickly test for abnormal program operations and address bus failures.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a processing flow of a program for operating the embodiment of the present invention. In the figure, 1... Central processing unit, 2... Memory circuit, 3... Input/output control device, 4... Comparison circuit, 5...
・Control signal generation circuit, 6, 7... flip-flop,
8...AND circuit, 9,10.11...Signal inversion circuit, 12...Address bus line, 13...Data path line, 14...Memory request line, 15...Work○ request Line, 16...Lead line, 17...Write line, 18...Memory lead line, 1...Memory write line, 20...IO lead wire, 21...■0 write line, 22...Machine cycle 1 line, 23...Result output line, 25...Gate line, 26...Result holding line, 27
...Gate line, 28...Result output line.

Claims (1)

[Claims] a central processing unit that executes a program; a storage circuit that stores the program; an input/output control unit; and a comparison circuit that compares an address bus signal from the central processing unit with a signal from the input/output control unit. , a flip-flop that holds the results of the comparison circuit, and a control signal generation circuit that uses the results to control the storage circuit, input/output control device, comparison circuit, and flip-flop according to control information from the central processing unit. , sequentially set an address 0 and an address where the address bus is all 1 on the address bus,
An address bus test method characterized in that the address bus is tested by comparing the signal line from the input/output control device with the address bus signal.