JPH0782407B2 - Reset processing method for microprocessor - Google Patents

Description

The present invention relates to a reset processing method of a microprocessor in an electronic device that controls using a microprocessor, and relates to a reset operation while maintaining an operating state when a reset occurs during operation of the electronic device. The reset level information assigned to each signal in response to the generation of a signal indicating an abnormal state in which a reset should be executed is provided to the reset level setting circuit for the purpose of providing a reset processing method for a microprocessor. A reset control circuit for setting and subsequently outputting a reset signal to the microprocessor is provided, the microprocessor accesses the reset level address by the reset level access means, reads the reset level by the reset level reading means, and reads it by the execution address setting means. Reset The branch destination address is set according to the level.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset processing method for a microprocessor in an electronic device that performs control using the microprocessor.

2. Description of the Related Art In recent years, a technique of controlling by a micro program has been widely used in various electronic devices from industrial use to home use. In a device that performs control by such a microprocessor, when an abnormality occurs in the microprocessor (abbreviated as MPU), the MPU is reset and the MPU is initialized. Upon completion of the reset, the MPU clears the contents of RAM (random access memory) and external registers and then starts control.

Therefore, when an abnormality such as a reset occurs, there is a problem that the internal state of the MPU is lost by the reset operation, and improvement thereof is desired.

[Prior Art] In an electronic device in which a microprocessor performs a function of inputting a signal indicating a device state or an environmental condition and outputting a corresponding control signal, an abnormal state of an MPU (for example, a parity error of input data occurs) MP) when detected)
The reset signal is input to the reset terminal of U. In that case, the MPU usually has one reset pin.
There is only one, and when the reset input arrives at the reset terminal, it stops the operation of MPU. That is, the address bus and the data bus are set to a high impedance state, interrupts cannot be accepted, and the output control signal is made inoperative.

Then, when the reset signal is released, the MPU automatically performs the initialization operation, and unconditionally the RAM that is the main storage device.
The initial program loading operation is performed by clearing the contents of (random access memory) and external registers, and this operation has the same contents as the processing executed when the power is turned on.

[Problems to be Solved by the Invention] As described above, according to the conventional technique, when the set signal is input, the microprocessor is reset and clears all the contents of RAM and registers. Even if the electronic device is stopped and the operation is stopped, and then the reset is released, the MPU needs to restart the operation after the initialization process similar to the power-on.

Therefore, there is a problem that the reset operation impairs the reliability of the electronic device controlled by the MPU.

An object of the present invention is to provide a reset processing method for a microprocessor that can perform a reset operation while maintaining the operating state when a reset occurs during operation of an electronic device.

[Means for Solving the Problems] FIG. 1 is a principle configuration diagram of Invention 1, and FIG. 2 is a principle configuration diagram of Invention 2.

In FIG. 1, 10 is a microprocessor (hereinafter referred to as MPU), 11 is a reset control circuit, 12 is an MPU abnormality detection circuit, 13 is a reset level setting circuit, 101 is a reset level access means, 102 is a reset level reading means, 103. Represents an execution address setting means.

In FIG. 2, 20 is a microprocessor 2 (hereinafter referred to as MPU2).
, 21 is a microprocessor 1 (hereinafter referred to as MPU1), 220 and 221 are abnormality detection circuits, 230 and 231 are reset level setting circuits, and 240 and 241 are reset instruction circuits.
211 is reset level setting means, 212 is reset instructing means, and MPUs 201 to 203 are means similar to 101 to 103 in FIG.

The present invention provides a circuit for setting a reset level corresponding to an abnormality of the MPU, sets setting data in the reset level setting circuit before resetting the MPU, and the MPU resets corresponding to the reset level after the reset is released. It is an operation.

[Operation] The operation of the configuration of the invention 1 shown in FIG. 1 will be described.

When an abnormality occurs in the MPU 10, one of a plurality of signals representing the abnormality is supplied to the MPU abnormality detection circuit 12, and the signal is output to the reset control circuit 11. Reset control circuit 11 is MP
The level is identified according to the abnormal signal from the U abnormality detection circuit 12, the level data is set in the reset level setting circuit 13, the level data is supplied to the MPU 10, and then the reset signal is output to the reset terminal of the MPU 10.

When the MPU 10 receives the reset signal, the operation is stopped, and when the reset is released, the reset level access means 101 accesses the address at the time of reset. As a result of the access, the reset level reading means 102 operates to read the reset level setting circuit 13. Next, the execution address setting means 103 sets the execution address corresponding to the read reset level, branches to the routine corresponding to the reset level, and the processing is performed.

The principle configuration of the invention 2 shown in FIG. 2 is that the function performed by the reset control circuit 11 in the configuration of FIG. 1 is executed by the MPU1 (21), and the MPU1 and MPU2 each have an abnormal signal from the partner device. It is characterized in that it is provided with a configuration in which the controls for the reset operation are mutually executed when receiving the. However, FIG. 2 shows the technical means of each MPU in the case where the MPU 1 performs control operations such as reset level setting and the MPU 2 executes the reset process when an abnormality occurs in the MPU 2.

Explaining the operation of FIG. 2, when an abnormality occurs in MPU2,
The abnormality signal is set in the abnormality detection circuit 221 via the bus. The abnormality detection circuit 221 is read by the MPU 1.

The MPU 1 identifies the abnormal level according to the contents of the abnormality detection circuit 221, and sets the level data in the reset level setting circuit 231 by the reset level setting means 211. Then, the reset instruction means 212 operates to set the reset instruction circuit 241. When the reset instruction circuit 241 is set,
The output becomes a reset input signal to the reset terminal of MPU2. As a result, the MPU2 stops its operation, and when the reset is released, thereafter, each means 201 similar to the MPU (10) in FIG.
Processing is performed according to 203. At that time, the reset level reading means 202 reads the contents of the reset level setting circuit 231 set by the MPU 1.

When a failure occurs in MPU1, an abnormality signal is determined in the abnormality detection circuit 220, a level is set in the reset level setting circuit 230 by the MPU2, and a reset instruction is set in the reset instruction circuit 240.

[Embodiment] FIG. 3 is a configuration diagram of an embodiment of the invention 1, FIG. 4 is a process flow chart of the embodiment, FIG. 5 is a diagram showing a configuration example of a reset control circuit, and FIG. 6 is an embodiment of the invention 2. Configuration diagram, Fig. 7 shows partner MPU
FIG.

In FIG. 3, 30 is MPU (microprocessor), 31
Is MPU reset control circuit, 32 is MPU abnormality detection circuit, 33
Is a reset level register, 36 is an interface (indicated by IF), and 37 is an electronic device to be controlled.

The operation of the embodiment shown in FIG. 3 will be described with reference to the process flow chart shown in FIG.

In the MPU 30 of FIG. 3, when an abnormality occurs in any of the internal circuits, an output indicating the corresponding abnormal state is input to the MPU abnormality detection circuit 32. The MPU abnormality detection circuit 32 outputs a signal corresponding to the abnormality input to the MPU reset control circuit 31.

Upon receiving the signal, the MPU reset control circuit 31 identifies the reset level and sets one output line of the reset level (1 to k) to "1" according to the identification result and sets it in the reset level register 33. Then, the reset control circuit 31 of the MPU outputs a reset signal to the MPU 30. In FIG. 4, the MPU 30 is reset (released) after a reset signal is input to enter the reset state (stop state) (step 41). Then immediately jump to the reset level (step 42). This reset level is a preset address of the memory (normally FFFE (H) to FFFF (H):
(H) represents a hexadecimal number).

Next, when the instruction of the address of this reset level is accessed (step 43), the reset level register 33 is written there.
Is stored and the instruction is executed (step 44).

When a table (not shown) is referred to by the read contents, the branch destination address is stored in the table corresponding to the reset level, and the address corresponding to the read reset level is output (step 4
Five). Next, the program is executed by branching to the address obtained from the table (step 46).

As for this branch destination, the routine of the program exists from the initial routine 471 to the normal routine A472 to the normal routine C474 as shown in FIG. 4, and after the initial routine, the normal routines A to C are executed as a loop. For example, when branching to the beginning of the initial routine (clearing all RAM, registers, etc. before entering the reset state) depending on the level, or normal routine A, B, C (reset state) The state before it becomes a part or all is saved).

FIG. 5 shows a configuration example of the reset control circuit (31) of the MPU of FIG. 3, and its operation will be described. In the abnormality signal line connected to the MPU abnormality detection circuit (FIG. 32). One abnormal signal output is set in the flip-flop circuit 50 through the OR circuit 52. On the other hand, the level of the signal input from the abnormality detection circuit is identified, and in this example, it is identified by hardware, and the OR circuit 53 outputs the level 1 when the signal from the signal line 1 or the signal line 2 of the abnormality detection circuit is input. Is generated and input to the reset level register 33.

Input lines from other abnormality detection circuits are also converted into corresponding level signals and output to the reset level register. The signal set in the flip-flop circuit 50 is output from the AND circuit 51 when the timing signal input is given, and is supplied to the MPU as an MPU reset signal.

An embodiment of the invention 2 will be described with reference to FIG.

In FIG. 6, 60 and 61 are MPU1 and MPU2, 630 and 631 are registers, 640 and 641 are abnormality detection circuits for MPU1 and MPU2, 650 and 651, respectively.
Is a flip-flop circuit that generates a reset signal (hereinafter referred to as reset FF), and 660 and 661 are reset level registers. In the configuration of FIG. 6, each of the MPU1 and MPU2 controls a different electronic device, and is provided with a configuration in which reset control is performed when an abnormal signal occurs.

The operation of FIG. 6 will be described with reference to the process flow chart of the partner MPU of FIG.

When an abnormal signal is generated from MPU2, the MPU2 abnormality detection circuit 64
An abnormal signal is input to 0, and its output is set in the register 630.

Here, the MPU1 is performing the processing shown in FIG.
The register 630 is read to determine whether there is data, and if there is, the abnormal level is identified by the data (step 72). Next, the identified level data is set in the reset level register 660 (step 73). Then, the reset FF650 is set (step 74).

Reset of MPU1 When the reset signal is input to the reset terminal of MPU2 as shown in Fig.6 by setting FF650,
The MPU2 executes the processing shown in FIG. 4, and after releasing the reset, reads the contents of the reset level register 660 and branches to the address corresponding to the level.

The MPU1 and MPU2 shown in FIG. 6 perform independent control of the electronic devices, respectively, and perform reset control operations when an abnormal signal occurs. Therefore, it has a function of executing the processing flows shown in FIGS. 4 and 7.

[Effect of the Invention] According to the present invention, the processing device (microprocessor) can accurately determine the processing after reset, and can recover from the abnormal state of the processing device to the normal operating state while maintaining the operating state according to the reset level. Therefore, it is possible to return to the normal operation without bringing down the electronic device to be controlled, and it is possible to improve the reliability.

According to the second aspect of the invention, in addition to the above effects, the processing devices monitor each other, whereby the processing of further subdividing the degree of the abnormal state and making a determination can be efficiently executed, and high reliability is realized. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the invention 1, FIG. 2 is a block diagram showing the principle of the invention 2, FIG. 3 is a block diagram of the embodiment of the invention 1, FIG. 4 is a process flow chart of the embodiment, and FIG. Is a configuration diagram of a reset control circuit, FIG. 6 is a configuration diagram of an embodiment of the invention 2, and FIG. 7 is a counterpart MPU.
FIG. In FIG. 1, 10: MPU 11: reset control circuit 12: MPU abnormality detection circuit 13: reset level setting circuit 101: reset level access means 102: reset level reading means 103: execution address setting means

Claims (2)

[Claims] 1. A reset processing method for a microprocessor in an electronic device for controlling using a microprocessor, wherein reset level information assigned to each signal in response to generation of a signal indicating an abnormal state in which reset is to be executed. Is set in the reset level setting circuit (13), and subsequently a reset control circuit (11) for outputting a reset signal to the microprocessor is provided.
1) The reset level address is accessed by the reset level reading means (102), the reset level is read by the reset level reading means (102), and the branch destination address is set according to the reset level read by the execution address setting means (103). Reset processing method for microprocessor. 2. A method for resetting a microprocessor in an electronic device that controls using a microprocessor, comprising two microprocessors that each control the electronic device, and each microprocessor should execute a reset. Equipped with an anomaly detection circuit (220, 221) that holds the signal when an abnormal condition signal is generated, and one microprocessor identifies the corresponding anomaly level when the anomaly detection circuit (221) detects an anomaly signal from another microprocessor. Then, the reset level is set by the reset level setting means (211), and the reset instruction is issued by the reset instructing means (212), and the other microprocessor accesses the reset level address by the reset level access means (201) and resets. Reread by the level reading means (202) It reads Ttoreberu, reset processing method of the microprocessor, characterized in that the branch destination address in response to the reset level read by the execution address setting means (203) is set.