JPH02165310A - Method for processing reset of microprocessor - Google Patents

Abstract

PURPOSE:To execute reset operation while keeping an operation state at the time of generating reset during the operation of an electronic apparatus by setting up set data in a reset level setting circuit before resetting an MPU, and after releasing the reset executing reset operation corresponding to the reset level. CONSTITUTION:At the time of receiving a reset signal, the microprocessor(MPU) stops its operation, and when the reset is released, accesses an address obtained at the time of reset by a reset level accessing means 101. As the result of the access, a reset level reading means 102 is driven to read out the contents of the reset setting circuit 13. An execution address setting means 103 sets up an execution address corresponding to the read reset level and branches the operation to a routine corresponding to the reset level to execute the processing. Thereby, the reset operation can be executed while keeping the operation state even at the time of generating reset during the operation of the electronic apparatus.

Description

[Detailed Description of the Invention] [Summary] Regarding a microprocessor reset processing method in an electronic device controlled using a microprocessor, when a reset occurs while the electronic device is operating, the reset operation is performed while maintaining the operating state. The purpose of this invention is to provide a microprocessor reset processing method that can perform a reset, and in response to the occurrence of a signal representing an abnormal state in which a reset should be executed, reset level information assigned to each signal is sent to a reset level setting circuit. The microprocessor accesses the reset level address by the reset node level access means, reads the reset level by the reset level reading means, and then outputs the reset signal to the microprocessor. FIELD OF THE INVENTION The present invention relates to a microprocessor reset processing method in an electronic device controlled using a microprocessor.

In recent years, technology for controlling using microprograms has been widely used in various electronic devices from industrial to home use. In devices controlled by such a microprocessor, when an abnormality occurs in the microprocessor (abbreviated as MPU), the MPU is reset and initialized. When the MPU completes its reset, it clears all the contents of RAM (random access memory) and external registers, and then starts control.

For this reason, when an abnormality that causes a reset occurs, there is a problem in that the entire internal state of the MPU is lost due to the reset operation, and there is a desire to improve this problem.

[Prior Art] In electronic equipment in which a microprocessor performs the function of inputting a signal representing the equipment status or environmental status and outputting a corresponding control signal, an abnormality G of the MPU (for example, a parity error of input data) A configuration is adopted in which a reset signal is input to the reset terminal of the MPU when an event (such as the occurrence of an error) is detected. In that case, the MPU is usually provided with only one reset terminal, and when a reset input arrives at the reset terminal, the operation of the MPU is stopped. That is, the address bus and data bus are brought into a high impedance state, interrupts cannot be accepted, and output control signals are rendered inactive.

Then, when the reset signal is released, the MPU automatically performs an initialization operation and unconditionally sends the main rudder't! The device is configured to clear the contents of the RAM (random access memo, external registers, etc.) and perform an initial program loading operation, and this operation is similar to the process executed when the power is turned on.

[Problem to be Solved by the Invention] As described above, according to the conventional technology, when the microprocessor receives the cent signal, it is reset and the RAM is
MPL
Even if the electronic device controlled by J goes down and stops operating, and the reset is subsequently released, the MPU needs to resume operation through the same initialization process as when the power is turned on.

Therefore, there is a problem in that the reset operation impairs the reliability of electronic devices controlled by the MPU.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor reset processing method that can perform a reset operation while maintaining the operating state when a reset 7) occurs during the operation of an electronic device.

[Means for Solving the Problems] FIG. 1 is a diagram showing the basic configuration of invention 1, and FIG. 2 is a diagram showing the basic configuration of invention 2.

In Figure 1, lO is a microprocessor (MP
11 is a reset control circuit, 12 is an MPU abnormality detection circuit, 13 is a reset level setting circuit, 101 is a reset level access means, 102 is a reset level reading means, and 103 is an execution address setting means.

In FIG. 2, 20 is a microprocessor 2 (hereinafter M
21 is a microprocessor l (hereinafter referred to as MPUI), 220 and 221 are abnormality detection circuits, 2
30, 231 are reset level setting circuits, 240, 24
1 represents a reset instruction circuit, 211 of MPUI is a reset level setting means, 212 is a reset instruction means, MPUI
201 to 203 of U2 are the same means as 101 to 103 in FIG. 1 above.

The present invention provides a circuit for setting a reset level in response to an abnormality in the MPU, and sets setting data in the reset level setting circuit before resetting the MPU.
After the reset is released, a reset operation corresponding to the reset level is performed.

[Effect] The operation of the configuration of invention 1 shown in FIG. 1 will be explained.

When an abnormality occurs in MPU10, one of the plurality of signals representing the abnormality is supplied to the MPU abnormality detection circuit 12, and that signal is output to the reset control circuit 11. The reset control circuit 11 identifies the level according to the abnormal signal from the MPU abnormality detection circuit 12, sets the level data in the reset level setting circuit 13, supplies it to the MPU10, and then sends a reset signal to the reset terminal of the MPU10. Output.

When the MPLIIO receives a reset signal, it stops operating, and when the reset is released, the reset level access means 101 accesses the address at the time of reset. As a result of the access, the reset level reading means 102 operates, and the reset level setting circuit 13 is read.

Next, the execution address setting means 103 sets an execution address corresponding to the read reset level, branches to a routine corresponding to the reset level, and performs processing.

The principle configuration of the second invention shown in FIG. 2 is that the machine R performed in the reset control diagram Ill in the configuration of FIG.
21), and that the MPUI and MPU2 each have a configuration in which they mutually execute control for the reset operation when they each receive an abnormal signal from a partner device.

However, in Figure 2, when an abnormality occurs in MPU2,
The technical means of each MPU is shown when the MPUI performs control operations such as reset level setting and the MPU 2 executes reset processing.

To explain the operation of FIG. 2, when an abnormality occurs in MPLI2, the abnormality signal is sent to the abnormality detection circuit 222 via the bus.
is set to The abnormality detection circuit 221 is +fAPU
read by l.

MPtJl identifies the abnormal level according to the contents of the abnormality detection circuit 221, and sets the level data in the reset level setting circuit 231 by the reset level setting means 211. Next, the reset instruction means 212 operates to set the reset instruction circuit 241. Reset instruction circuit 24
When set to 1, its output becomes a reset input signal to the reset terminal of MPU2. The MPU 2 thereby stops its operation, and when the reset is released, processing is thereafter performed by each means 201 to 203 similar to the MPU (10) in FIG. At that time, reset level reading means 2
02 reads the contents of the reset level setting circuit 231 set by the MPUI.

Note that when a failure occurs in the MPUI, an abnormality signal is determined in the abnormality detection circuit 220, a level is set in the reset level setting circuit 230 by the MPLI 2, and a reset instruction is sent to the recess/node instruction circuit 240. Become.

[Example] Fig. 3 is a configuration diagram of an embodiment of invention 1, Fig. 4 is a processing flow diagram of the embodiment, Fig. 5 is a diagram showing a configuration example of a reset control circuit, and Fig. 6 is an embodiment of invention 2. Configuration diagram, Figure 7 is the partner MPU
FIG. 2 is a processing flow diagram.

In Fig. 3, 30 is an MPU (microprocessor), 31 is an MPU reset control circuit, 32 is an MPU abnormality detection circuit, 33 is a reset level register, 36 is an ink face (indicated by IF), and 37 is a control target. Represents a certain electronic device.

The operation of the embodiment shown in FIG. 3 will be explained with reference to the processing flow diagram shown in FIG.

In the MPU 30 of FIG. 3, when an abnormality occurs in any of the internal circuits, an output representing the corresponding abnormal state is input to the abnormality detection circuit 32 of the MPU.

The abnormality detection circuit 32 of the MPU outputs a signal corresponding to the abnormal input to the reset control circuit 31 of the MPU.

When the MPU reset control circuit 31 receives the signal,
The reset level is identified, and one output line of the reset levels (1 to k) is set to "1" in the reset level register 33 according to the identification result. Next, the MPU reset control circuit 31 outputs a reset signal to the MPU 30. In FIG. 4, the reset signal is input to the MPU 30 and the MPU 30 enters the seven-step state (stopped state), and then the reset is released (step 41). Then, it immediately jumps to the reset level (step 42). This reset level is set at a preset address in memory (usually F
FFE()l) to FFFF(II): (H) represents a hexadecimal number).

Next, when the instruction at this reset level address is accessed (step 43), an instruction to read the reset level register 33 is stored there, and that instruction is executed (step 44).

When a table (not shown) is referred to based on the read contents, branch destination addresses corresponding to the reset level are stored in the table, and the address corresponding to the read reset level is output (step 45).
). Next, the program branches to the address obtained from the table and executes the program (step 46).

As shown in FIG. 4, the branch destination is the initial routine 471 and the normal routine A47.
If we take an example in which there are routines 2 to c474 and normal routines A to C are executed in a loop after the initial routine, the beginning of the initial routine (RAM before entering the reset state) , to clear all registers, etc.), or to normal routines A, B, and C (in which part or all of the state before entering the reset state is saved).

Figure 5 shows the reset control circuit (31) of the MPU in Figure 3.
I will show an example of the configuration and explain its operation.

An abnormal signal output from one of the abnormal signal lines connected to the abnormality detection circuit (FIG. 3, 32) of the MPU is set to the flip-flop circuit 50 through an OR circuit 52. on the other hand,
The level of the signal input from the abnormality detection circuit is identified, and in this example, it is identified by hardware, and the OR circuit 53 generates an output of level l when a signal from the signal line 1 or signal NiA2 of the abnormality detection circuit is input. , is input to the reset level register 33.

Human power lines from other abnormality detection circuits are also converted into corresponding level signals and output to the reset level register. The signal sent to the flip-flop circuit 50 is outputted from the AND circuit 51 when a timing signal is applied to the MP.
It is supplied to the MPU as a U recent signal.

A configuration diagram of an embodiment of invention 2 will be explained with reference to FIG.

In FIG. 6, 60 and 61 are MPUI, respectively.

MPU2.630,631 are registers, 640°641
650.degree. 651 is a flip-flop circuit that generates a reset signal (hereinafter referred to as reset F, F), and 660.degree. 661 is a reset level register. The configuration shown in Figure 6 consists of MPUI and M
Each of the PUs 2 controls another electronic device, and is configured to mutually execute reset control when an abnormal signal occurs.

The operation shown in FIG. 6 will be explained with reference to the process flow diagram of the partner MPU shown in FIG.

When an abnormal signal is generated from the MPU 2, the abnormal signal is input to the abnormality detection circuit 640 of the MPU 2, and its output is set in the register 630.

Here, the MPUI executes the process shown in FIG. 7, reads the register 630 to determine whether there is data, and if so, identifies the abnormality level based on the data (step 72). Next, the identified level data is set in the recessed level register 660 (step 73). Thereafter, reset F, F, 650 is set (step 74).

When a reset signal is input to the reset terminal of the MPU2 as shown in FIG. 6 by reset F, F, and 650 cents of the MPUI, the MPU2 executes the process shown in FIG.
After the reset is released, the contents of the reset level register 660 are read and branched to the address corresponding to the level.

The MPUI and MPU2 in FIG. 6 each execute independent control of the electronic equipment, and mutually perform reset control operations when an abnormal signal occurs. Therefore, it has the function of executing the process a shown in FIGS. 4 and 7.

[Effects of the Invention] According to the present invention, the processing device (microprocessor) can accurately determine the processing after being reset, and the reset level allows the processing device to return to the normal operating state from an abnormal state while maintaining the operating state. It is possible to return to normal operation without shutting down the electronic device being controlled, and improve reliability.

Further, according to invention 2, in addition to the above-mentioned effects, by mutually monitoring the processing devices, it is possible to efficiently execute processing for determining the degree of abnormality in more detailed manner, thereby achieving high reliability. Can be done.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle configuration of invention 1, Fig. 2 is a diagram of the principle configuration of invention 2, Fig. 3 is a diagram of the embodiment of invention 1, Fig. 4 is a processing flow diagram of the embodiment, and Fig. 5 6 is a configuration diagram of the reset control circuit, FIG. 6 is a configuration diagram of an embodiment of invention 2, and FIG. 7 is a diagram of the counterpart MP.
It is a processing flow diagram of U. In Figure 1, 10: MPU 11: Reset control circuit 12: MPU abnormality detection circuit 13: Reset level setting circuit 101: IJ upper set level access means 102: Reset level reading means 103; Execution address setting means Patent applicant: Fujitsu Kazuo Hosaka, Patent Attorney Sub-Agent, Co., Ltd., Rieditto, Genma, Q44 - Diagram $ 5 Diagram 8 MPU flow diagram. 7 cups of tea

Claims (2)

[Claims] (1) In a microprocessor reset processing method for electronic equipment controlled using a microprocessor, reset level information assigned to each signal is reset in response to the occurrence of a signal representing an abnormal state that requires a reset. It is equipped with a reset control circuit (11) that sets the level setting circuit (13) and then outputs a reset signal to the microprocessor, and the microprocessor accesses the reset level address by the reset level access means (101) and reads the reset level. The reset level is read by the means (102), and the execution address setting means (
A microprocessor reset processing method characterized in that a branch destination address is set according to a reset level read by 103). (2) A method for resetting a microprocessor in an electronic device controlled using a microprocessor, wherein each microprocessor is provided with two microprocessors that control the electronic device, and each microprocessor is in an abnormal state in which it should be reset. An abnormality detection circuit that holds the signal when it occurs (
220, 221), when one microprocessor detects an abnormal signal from the other microprocessor by an abnormality detection circuit (221), it identifies the corresponding abnormal level and sets a reset level by a reset level setting means (211). At the same time, the reset instruction means (212) issues a reset instruction, and the other microprocessor accesses the reset level address using the reset level access means (201), reads the reset level using the reset level reading means (202), and reads the execution address. A microprocessor reset processing method, characterized in that a branch destination address is set according to a reset level read by a setting means (203).