JPS61210441A - Bug detecting method for program - Google Patents

Abstract

PURPOSE:To detect the bug of a program by adding the hardware to make a parity mode into the odd or even optional condition in a system having a parity generator checker G/C. CONSTITUTION:When the bug of the control program stored in a main RAM 8 is detected, first, a debugging mode setting circuit 11 is a debugging mode. When the electric power source is turned on, a microprocessor (MPU) 1 executes the initializing processing, discriminates the debugging mode of the circuit 11, writes zero into a parity mode setting circuit 12 and sets to an even parity mode. Next, all zero is written in the definition area of a RAM 8, and all zero is written at the corresponding area of a parity RAM 9. Next, the MPU 1 writes one into the parity mode setting circuit 12, sets to an odd parity mode and executes the control program of the main RAM 8. Thus, the bug such as a definition forgetting of a significant variable can be detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In the present invention, before executing a program targeted for bug detection, the parity mode is changed to a first mode (for example, even parity mode) and a predetermined area of memory is Detects bugs such as forgetting to define a significant variable in the program by storing data and parity bits in the program, then changing the parity mode to a second parity mode (for example, odd parity mode) and running the program. This is how it was done.

[Industrial application field]

The present invention relates to a method for detecting bugs present in a program.

To ensure the operation of a microprocessor system,
It is necessary to improve the reliability of hardware and eliminate bugs in programs. As a measure to improve the reliability of the hardware, a parity generator/checker (hereinafter referred to as parity G/C) is installed, and the parity bit generated by the parity G/C when writing data to and reading data from memory is installed. It writes the parity bit along with the data and reads out the written parity bit along with the data to check it, and when a parity error occurs, interrupts the microprocessor to change or stop its operation so that the microprocessor does not perform abnormal processing. It is possible to do so. Additionally, bugs in the program can be detected and corrected using existing debugging tools and the like.

[Conventional technology]

Conventionally, in systems with a parity G/C, the parity G/C is used only to detect hardware errors, and program bugs are detected using a separate debugging tool. ing.

[Problem that the invention seeks to solve]

Therefore, without debugging tools, finding bugs becomes extremely difficult.

The present invention has been made in view of these circumstances,
The purpose is to enable a system having a parity G/C to detect simple program bugs using this parity G/C.

[Means for solving problems]

In order to solve the above problems, the present invention writes a parity bit generated by a parity generator/checker to the memory at the same time when data is written from the microprocessor to the memory, and when reading data from the memory. In a microprocessor system, the parity pin stored in memory is added to the parity generator/checker to perform a parity check, and when a parity error is detected, an interrupt is generated to the microprocessor to stop or change its operation. In a program bug detection method, before executing the program to be detected, the parity mode of the parity generator/checker is changed to the first parity mode and data and parity bits are stored in a predetermined area of memory. Then, the parity mode of the parity generator/checker is changed to a second parity mode, and the program is executed.

[Effect]

If a step to define a significant variable is originally required in the program but is not done, the significant variable definition area has already been written in the first parity mode, so When that area is read in the control program, the parity bit indicates the first parity mode, and the microprocessor stops operating at that point due to the occurrence of a parity error. If a significant variable is defined in the control program, writing to the area is performed in the second parity mode, so no parity error occurs during reading.

〔Example〕

FIG. 1 shows an example of a system implementing the present invention.

FIG. 2 is a block diagram of main parts. In the figure, a microprocessor (MPU) 1 has, for example, an 8-bit data bus 2, a 16-bit address bus 3, and an 8-bit address bus 3. Data bus 2 is main RAM8. It is connected to a parity G/C 10 and a debug mode setting circuit 11, and the address bus 3 is connected to an address decoder 6.7, a main RAM 8 and a parity RAM 9. Address decoder 6 includes depack mode setting circuit 11. Parity mode setting circuit 1
The address decoder 7 is used to select chips of the main RAM 8 and the parity RAM 9. The main RAM 8 has an area for storing control program, variable definition area, etc., and has a parity RAM.
M9 has an area for storing 1-bit parity of each data stored in the main RAM 8, and both RAMs 8.9 are selected by the chip select signal from the address decoder 7 and connected to the same address line of the address bus 3. Ru. That is, the address spaces of both RAMs 8.9 and 9 are the same. The 1-bit output a of the parity RAM 9 becomes 0'' during writing by the gate circuit 15 which inputs the signal 4 for identifying it, and becomes 0'' or 1 during reading, corresponding to the stored parity bit. becomes. Parity C, / C
10 is the total of 8 bits of data and 1 bit of output a, 9
If there is an even number of "1"s among the bits (including zero), the output C is set to "0", and on the other hand, if there is an odd number of "1"s, the output C is set to "1". The output C of the parity G/C10 is added to one input of the exclusive OR circuit 11,
The output of the parity mode setting circuit 12 is added to the other input. In the parity mode setting circuit 12, "0" is written by the microprocessor 1 in the even parity mode, and "1" is written in the odd parity mode. Note that the parity mode setting circuit 12 may be configured with an external switch or the like. The output d of the exclusive OR circuit 13 is input to the parity RAM 9 and the gate circuit 14. A signal 4 indicating a read cycle is applied from the microprocessor 1 to the gate circuit 14, and the output d of the exclusive OR circuit during that period is input to the microprocessor 1 as an interrupt signal 5. The debug mode setting circuit 11 is for determining whether or not to set the present system to a debug mode, and is composed of, for example, one switch.

In the even parity mode in which “O” is written to the parity mode setting circuit 12 and the output is 0, for example, all “0” data is sent to the data bus 2, and this is written to a certain area of the main RAM 8. When the data is written, the output a of the parity RAM 9 is set to "0" by the gate circuit 15, so the output C of the parity G/C 10 is set to "0" at the time of writing.
Therefore, the corresponding address of parity RAM 9 is set to “0”.
” is written. Also, when this area is read, the output a of the parity RAM 9 is “O”, and if the data is read normally from the main RAM 8, all “0” will be output. C becomes "O" and no interrupt is applied to the microprocessor 1. However, if the data read from the main RAM 8 has an error in an odd number of bits, the output C of the parity G/C becomes "L".
This is applied to the microprocessor 1 via the gate circuit 14, which is opened during the read cycle, and the microprocessor 1 executes the interrupt processing.

FIG. 2 is a flowchart showing an example of processing by the microprocessor 1.

When detecting a bug in the control program stored in the main RAM 8, first, data indicating a debug mode is set in the debug mode setting circuit 11 from the outside. When the power is turned on, the microprocessor 1 first performs initialization processing (SL) as shown in FIG. S2). When in debug mode, set the even parity mode by writing 0'' to the parity mode setting circuit 12 (53), then write all “O” data to all significant variable definition areas of the main RAM 8 ( S4). Through this process, for example, as shown in FIG.
is written, and all "
O” should be written.

When the above processing is completed, the microprocessor 1 sets the system to the odd parity mode by writing 1'' to the parity mode setting circuit 12 (S5), and the main RA
The control program of M8 is executed (S6). For example, if the execution of this control program includes step S7 of setting the value 15 to address A of the main RAM 8, the microprocessor 1 writes "15" to address A.

With this process, for example, as shown in FIG.
15 (00001111) is written to the parity R and the parity R is changed to odd parity mode.
``1'' is written in the corresponding area of AM9. In later processing, if there is a step S8 where C=AX2, for example, when the microprocessor 1 goes to read address A to execute this step, it will find that step S7 has been executed and there is no hardware error. In this case, "15" is accurately read from address A and no parity error occurs. However, if the significant variables are not defined in step S7, the parity RAM 9
Since the parity bit that matches the even parity mode is still stored in the address A, in step S8
When I try to read the contents, a parity error occurs. This causes an interrupt to be placed on microprocessor 1,
As shown in FIG. S, the microprocessor 1 stops or changes its operation, turns on a lamp, etc. (not shown), and generates an alarm externally (SIO, 5ll).

After completing the bug detection and correcting the program, if the contents of the debug mode setting circuit 11 are set to a mode other than the debug mode, the microprocessor 1 will proceed to step S3. S4
bus, the process moves to step S5, sets the system to odd parity mode, and immediately executes the control program.

In the above embodiment, the debug mode setting circuit 11 is provided, and a step is provided to determine whether or not the microprocessor 1 is in the debug mode when the power is turned on.
Although data is written to a predetermined area of M8, the setting of the even parity mode and the data writing may be performed by another program or an external command. Alternatively, the control program may be executed in even parity mode, and the debug mode may be in odd parity mode.

〔Effect of the invention〕

As explained above, according to the present invention, the parity G/C
By simply adding some hardware to set the parity mode to any odd or even number, bugs in the program can be detected using the parity G/C function.

[Brief explanation of drawings]

FIG. 1 is a main block diagram showing an example of a system implementing the present invention, FIG. 2 is a flowchart showing an example of processing by the microprocessor 1, and FIGS. 3 and 4 show the RAM 8.
FIG. 5 is a flowchart showing an example of interrupt processing by the microprocessor 1. ■ is the microprocessor, and 8 is the main RAM. 9 is a parity RAM, 10 is a parity G/C, and 12 is a parity mode setting circuit.

Claims (1)

[Claims] When writing data from the microprocessor to the memory, a parity bit generated by a parity generator/checker is written to the memory at the same time as the data, and when reading data from the memory, the parity bit is stored in the memory. A method for detecting bugs in a program in a microprocessor system, wherein a parity bit is added to the parity generator/checker to perform a parity check, and when a parity error is detected, an interrupt is issued to the microprocessor to stop or change its operation. Before executing the program targeted for bug detection, the parity mode of the parity generator/checker is changed to a first parity mode and data and parity bits are stored in a predetermined area of memory, and then the parity generator/checker - A method for detecting bugs in a program, characterized in that the parity mode by the checker is changed to a second parity mode and the program is executed.