JPS5860362A - Interruption signal generating system - Google Patents

Abstract

PURPOSE:To enable an interruption signal to be outputted at the access time of a prescribed address by providing a CPU with a parity inversion circuit and mismatching the parity code of a data in an address corresponding to a break point. CONSTITUTION:In respect of data to be stored in a storage device 1, a parity is added to the contents of a data register 5 in a parity generating circuit 4. Ordinally a break point setting processing part 7 outputs ''1'' to a parity inversion circuit 8 to add a normal parity. In case of break point setting, the processing part 7 accesses the device 1 at an address where an interruption signal is to be generated and reads out data from the device 1. When the processing part 7 outputs ''0'' to the cirlcuit 8 and the contents of the register 5 is written in the device 1, a value having an inverted parity code is stored in the device 1. If a CPU2 accesses to said address in the device 1, a parity error checking circuit 3 detects an error and outputs an interruption signal to an interruption processing part 6. Consequently the interruption signal is outputted at the break point.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interrupt signal generation method in an information processing device, and particularly to a method capable of generating an interrupt signal at a breakpoint with a simple configuration.

For information processing equipment, for purposes such as testing.

A function is provided to detect the point in time when an Akyas occurs at a predetermined address in the memory. This is used to stop the information processing device at a predetermined address, collect and analyze various register information at the time of access to the predetermined address, or test the circuit state.

Conventionally, methods for detecting that a predetermined address of a memory has been accessed include an address match method, a software interrupt instruction rewriting method, and the like. The former method requires extra hardware such as a register to store a predetermined address and a comparator to compare the address signal for accessing the memory with the contents of the register, resulting in a high price. The latter method achieves its purpose by rewriting the contents of a predetermined address into a software interrupt instruction and generating an interrupt when it is executed. If it is not executed, the software interrupt instruction will remain in the memory as it is, and if the instruction is executed when it is not related to a test or the like, it will instead become an abnormal interrupt, causing a kind of failure.

The aim of the invention is to eliminate the above-mentioned drawbacks.

The purpose of this is to perform a parity check with 1ε of information successively received from the storage device, and store a parity check section that generates an interrupt signal when an error occurs, and a process that should generate an interrupt signal when executed. This is accomplished by including a parity change processing unit that assigns an incorrect parity code to the contents of the storage area of the storage device. The present invention will be described in detail below using the drawings.

The figure shows three embodiments of the present invention. In figure 1, l is a storage device, 2 is a central processing unit, 3 is a parity check circuit which is a parity check section, 4 is a parity generation circuit, 5 is a data register, and 6 is an interrupt A processing section, 7 is a breakpoint setting processing section which is a parity change processing section, 8 is a parity inversion circuit for changing parity, 9 is a data bus, and 10 is one of the data storage locations in the storage device.

Next, I will explain my work. A parity generation circuit 4 assigns parity to the data stored in the storage device 1 to the contents of the data register 5. Normally, the breakpoint setting processing section 7 outputs rlJ to the parity inverting circuits 3+, 9, and is given a normal parity power. The data successively output from the storage device 1 is checked by the parity check circuit 3.
Tsuku was done.

If an error is detected, the interrupt processing unit 6 is notified.

Next, breakpoint setting 4 will be explained. The breakpoint setting processing section 7 accesses the storage device 1 at an address at which a breakpoint, that is, an interrupt signal should be generated, and outputs data one after another. The breakpoint setting processing unit 7 now outputs "0" to the parity inversion circuit 8, and when the contents of the data register 5 are written to the storage device 1, a value opposite to the original parity code is stored. The Rukoto.

Next, the central processing unit 2 sequentially accesses the storage device 1 to proceed with the processing, and when the address is accessed, the parity check circuit detects that the address has been assigned an incorrect parity code. 3 detects an error and 1
Generates an interrupt signal to the interrupt processing section 6. Therefore, an interrupt signal will be generated at the breakpoint.

As described above, one aspect of the present invention is to generate an interrupt signal at the time of accessing a predetermined address by simply providing the parity inverting circuit 8 and making the parity codes of data at the address corresponding to the breakpoint mismatched. I can do it.

[Brief explanation of the drawing]

The figure shows an embodiment of the invention. In the figure, 21 is a storage device, and 2 is a central processing unit. 3 is a parity check circuit, 4 is a parity generation circuit, 5
1 is a data register, 6 is an interrupt processing section, 7 is a breakpoint setting processing section, 8 is a parity inverting circuit, 9 is a data bus, and 10 is a data storage location in the storage device.

Claims (1)

[Claims] From a storage device that stores information with a parity code,
In a system for generating interrupt signals at breakpoints in a processing device that advances processing by sequentially issuing commands, the information successively received from the storage device is checked on a parity basis.
A parity check unit that generates an interrupt signal when an error occurs, and a parity change that adds an incorrect parity code to the contents of the storage area of the storage device that stores the process that should generate an interrupt signal when executed. An interrupt signal generation method characterized by comprising a processing section.