JPH0486932A - Memory fault detecting system - Google Patents

Abstract

PURPOSE:To detect the fault of a random access memory by a memory fault detecting circuit in an operation code fetch cycle by connecting the output terminals of the first and second address buffers with the chip enable terminal of the random access memory. CONSTITUTION:An address bus buffer B15 is enabled by a fetch cycle displaying signal 13, the output of a counter 17 counted up by the signal 13 appears at the output of the buffer B15 and inputted to both an RAM 7 and a parity bit holding memory 9. A decoder 12 receives a signal MREQ from a CPU 1. The decoder 12 transmits a signal CE1 to an ROM 6, and transmits a signal CE2 to an AND gate 18. A signal CE3 of both an RAM 7 and the memory 9 is forcedly inputted from the AND gate 18, and an RD signal of an OP code fetch is simultaneously inputted. Thus, data are read out from the RAM 7, and the parity bits of a parity PTY are read out from the memory 9. The read parity bits are checked by a parity checker 10, and the fault is detected by a fault detecting part 11.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a CPU (Central Process
The present invention relates to a memory fault detection method for a (Sing Unit) system.

[Conventional technology]

This kind of memory fault detection method is applicable to CPU, ROM (R
ead 0nly Memory), RAM (Ra
ndom AccessMemory) is equipped with a memory failure detection circuit and performs memory failure detection. An example of such a memory fault detection method is shown in FIG.

In Figure 3, 1 is the CPU, 2 is an oscillator that generates the system clock for the CPUI, 3 is a power-on reset circuit that resets the CPLll, and 4 is an address bus with 16
5 is a data bus with 8 bits, 6 is a ROM that stores the OP code of CPU1, and 7 is a CPU I
RAM for data storage used by , 8 is CPU R
A parity generator that generates a parity bit when writing data to AM7, 9 is a parity generator 8
10 is a parity checker that performs a parity check based on the read data and the data output from the parity bit storage memory 9 when the CPUI reads data from the RAM 7; 11 is a parity checker for parity storage; A memory failure is detected from the signal output from the checker 10, and if there is a failure, C
A failure detection unit that outputs an interrupt signal to the PUI, 12 is R
This is a decoder that generates chip enable signals for OM6 and RAM7.

In the conventional memory fault detection method having such a configuration, a memory fault is detected as follows. First, when the CPU writes data to RAM7,
A parity bit is generated by a parity generator 8,
It is held in the parity bit holding memory 9. Next, C.P.
When the UI reads data from the RAM 7, a parity checker IO performs a parity check using the read data and data output from the parity bit holding memory 9, and a failure detection unit 11 detects a failure. If there is a failure, the failure detection unit 11 outputs an interrupt signal to the CPUI.

[Problem to be solved by the invention]

In such conventional memory fault detection methods, the CPU
The drawback is that memory failures can only be detected when reading data from AM. Another drawback is that it can only detect memory failures at read addresses.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory fault detection method that eliminates such drawbacks and can detect memory faults by frequently checking the memory.

[Means for Solving the Problems] The present invention provides a central processing unit that accommodates a read-only memory and a random access memory via a data bus and an address bus, and a fetch cycle indicator that indicates that an operation code fetch cycle is in progress. a first address buffer provided on the address bus and disabled by the fetch cycle indication signal; a data bus buffer provided on the data bus and disabled by the fetch cycle display signal; a counter counted up by the fetch cycle display signal; and a data bus buffer provided at the output terminal of the counter and disabled by the fetch cycle display signal. a second address buffer enabled by a signal; and a gate provided at a chip enable input terminal of the random access memory to AND the chip enable signal of the decoder and the fetch cycle indication signal; The output terminals of the first and second address buffers are connected to a chip enable terminal of the random access memory, and a memory fault detection circuit detects a fault in the random access memory during the operation code fetch cycle. .

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. Note that portions common or corresponding to those of the conventional example shown in FIG. 3 are represented by the same numbers.

In Figure 1, 1 is the CPU, 2 is an oscillator that generates the CPtJl system clock, 3 is a power-on (ON) reset circuit that resets CPU 1, 4 is an address bus with 16 bits, and 5 is data. The bus has 8 bits, 6 is ROM to store the CPUI OP code, 7 is RAM for storing data used by CPUI, 8 is CPUI
A parity generator that generates parity bits when the LJI writes data to the RAM 7, 9 a parity bit storage memory that stores the parity bits generated by the parity generator 8, and 10 a parity bit that is used to store read data and parity when the CPU reads data from the RAM 7. A parity checker performs a parity check on the data output from the bit holding memory 9; 11 is a parity checker 1;
12 is a decoder that generates chip enable signals for ROM 6 and RAM 7;

13 is a fetch cycle indication signal indicating that the CPU is in an OP code fetch cycle; 14 is an address bus buffer A 115 disabled by the fetch cycle indication signal 13; and address bus buffer B enabled by the fetch cycle indication signal 13.
It is. The outputs of address bus buffer A14 and address bus buffer B15 are connected and input to address inputs of RAM 7 and parity bit holding memory 9.

16 is a data bus buffer that is disabled by the fetch cycle display signal 13; and 17 is a counter that is counted up each time the fetch cycle display signal 13 is input. The output of the counter 17 is connected to the input of the address bus buffer B15.

18 is an AND gate that performs a logical sum (AND) between the fetch cycle display signal 13 and the chip enable signal of the RAM 7 and parity pinto holding memory 9 output from the decoder 12. This is to force the CPU to input the chip enable signal to the RAM 7 and parity bit holding memory 9 during the OP code fetch cycle.

Next, the operation of this embodiment will be explained with reference to the time chart of FIG.

First, the CPUI is reset by the power-on reset circuit 3, and the clock φ from the oscillator 2 is applied to the CPUI.
'0' is written. Then, interrupts to the CPUI are enabled. The CPUI also generates the signal RFSH.

When the CPU bus cycle becomes an OP code fetch cycle, the TI of clock φ,
In the T2 state, the signal M1, that is, the fetch cycle indication signal 13 is asserted. The fetch cycle display signal 13 disables the address bus buffer A 14 and the data bus buffer 16, and the CPU
The address bus 4 and data bus 5 of I and the bus on the RAMT side are separated. That is, the signals on the address bus 4 become the signals A and AA, and the signals on the data bus 5 become the signals RI and DD.

Further, the address bus buffer 15 is enabled by the fetch cycle display signal 13, and the counter 1 counted up by the fetch cycle display signal 13 is enabled.
7 appears at the output of address bus buffer B15,
The data is input to RAM 7 and parity bit holding memory 9.

Decoder 12 receives and receives signal MREQ from CPUI. The decoder 12 also receives a chip enable signal CEI.
is sent to ROM6, and the chip enable signal CE2 is sent to AN.
Send to D gate 18. The chip enable signal CE3 of the RAM 7 and the parity bit holding memory 9 is forcibly inputted by the AND gate 8, and the R of the ○P code fetch is input.
A D signal is also input at the same time. Therefore, data is read from the RAM 7 and the parity pin of the parity PTY is read from the parity bit holding memory 9.

The read parity bit is sent to the parity checker 10.
The fault detection unit 11 detects the fault.

If it is a failure, the failure detection unit 11 sends the interrupt signal to the CPU.
Output to I.

In the next OP code fetch cycle, the output value of the counter 17 is counted up. In other words, the address of the RAM 7 is updated and a failure is detected as described above.

In this way, on every opcode fetch cycle, the RA
M7's address is updated and a failure is detected. In addition,
The memory fault detection method when the pass cycle of the CPU 1 becomes a read cycle is the same as the conventional technology.

As described above, the present embodiment has a CPU, a ROM, a RAM, and a memory fault detection circuit, and outputs a signal indicating that the CPU is in an OP code fetch cycle, that is, a fetch cycle display signal.
An address buffer A that is disabled by a fetch cycle indication signal is provided on the address bus of the system, and an address buffer A is provided on the address bus of the system.
A data bus buffer that is disabled by a fetch cycle indication signal is provided on the data bus of the PU system,
A counter that is counted up by the fetch cycle display signal and an address buffer B that is enabled by the fetch cycle display signal are provided at the output of this counter, and the outputs of address buffer A and address buffer B are connected, and a decoder is connected to the chip enable input of the RAM. An AND gate is provided to AND the chip enable signal output from the OP code and the fetch cycle indication signal, and a memory fault detection circuit performs fault detection during the OP code fetch cycle.

That is, this embodiment has an address bus buffer A and a data bus buffer that are disabled by the fetch cycle indication signal, an address bus buffer B that is enabled by the fetch cycle indication signal, and a counter that is counted up by the fetch cycle indication signal. By having an AND gate that ANDs the fetch cycle indication signal and the chip enable signal of the RAM and parity bit holding memory output from the decoder, potential failures of the RAM can be detected early without reducing the processing power of the CPU. can be detected.

〔Effect of the invention〕

As described above, the present invention detects a fault in a random access memory during an operation code fetch cycle, and therefore has the advantage of being able to discover an abnormality in this memory at an early stage.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the memory fault detection method of the present invention, FIG. 2 is a time chart of the OP code fetch cycle of the memory fault detection method shown in FIG. 1, and FIG. 3 is the conventional memory fault detection method. FIG. 2 is a block diagram for explaining a memory failure detection method. 1... CPU 2... Oscillator 3... Power-on reset circuit 4... Address bus 5... Data bus 6... ROM 7... ...RAM 8...Parity generator 9...
Parity pit holding memory 10... Parity checker 11... Fault detection unit 12... Decoder 13, 14, 15, 16, 17, 18, Fetch cycle display signal address bus buffer A address Bus buffer B Data bus buffer counter AND gate

Claims (1)

[Claims] (1) A central processing unit accommodates a read-only memory and a random access memory via a data bus and an address bus, and outputs a fetch cycle display signal indicating that an operation code fetch cycle is in progress, and the decoder In a memory failure detection method that outputs a chip enable signal according to instructions from a device, the first address buffer is provided on the address bus and is disabled by the fetch cycle indication signal; and the first address buffer is provided on the data bus and is disabled by the fetch cycle indication signal. a data bus buffer that is disabled by an indication signal; a counter that is counted up by the fetch cycle indication signal; and a second address buffer provided at an output terminal of the counter and enabled by the fetch cycle indication signal; a gate provided at a chip enable input terminal of the random access memory to take an AND of the chip enable signal of the decoder and the fetch cycle display signal; A memory fault detection method, characterized in that the memory fault detection circuit is connected to a chip enable terminal of the random access memory, and detects a fault in the random access memory by a memory fault detection circuit during the operation code fetch cycle.