JPH0643221A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the test cost and shorten the development period of the test program in the functional test of the central arithmetic processing device of a semiconductor integrated circuit. CONSTITUTION:The functional test program of a CPU 1 is stored in a code memory 2. The data expected to be outputted from the CPU 1 when the CPU 1 is operated according to the functional test program and the command codes of the code memory 2 are stored in a data memory 3. When the functional test program is executed, the data outputted from the code memory 2 and the CPU l and the data outputted from the data memory 3 are compared in sequence by a comparing circuit 5. If they are the same data as a result of the comparison, the RESULT signal 33 is made a low level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a central processing circuit (hereinafter abbreviated as "CPU") as a core,
In particular, the present invention relates to a semiconductor integrated circuit capable of easily performing a functional test of a CPU.

[0002]

2. Description of the Related Art As a semiconductor integrated circuit, a standard cell type is often used for a so-called special purpose. In the standard cell method, a desired semiconductor integrated circuit is constructed by combining cells designed in advance.
A standard cell type semiconductor integrated circuit includes a circuit block including a CPU function (hereinafter, abbreviated as “CPU block”) as a core and is often used for various controls. The semiconductor integrated circuit is 100% due to its manufacturing process.
Yield cannot be expected and must be assessed individually. In a post-manufacturing evaluation test of a semiconductor integrated circuit including a CPU block, a functional test of the CPU block and other blocks is performed, and then the entire evaluation test is performed.

In a conventional functional test of a semiconductor integrated circuit including a CPU, each function is divided into blocks, and the functional test is performed on each block. Similarly, in the case of the CPU block, the function test is performed by separating the functions from other blocks. The test method in this case is to connect the CPU to an external test device and set the conditions for operating the CPU to CP.
It is set by inputting to U, and the output state corresponding to the input condition is monitored by an external storage device to C
Check PU functionality.

[0004]

In a conventional functional test of a CPU block of a semiconductor integrated circuit, a C test is performed by an external test device.
A large number of terminals for inputting to the PU and terminals for monitoring the output state of the CPU are required, and the content of the functional test is complicated. Therefore, highly functional external test equipment is required. Furthermore, when performing a functional test, it is necessary to consider a signal delay within the semiconductor integrated circuit. Therefore, even if the same CPU block is used, it is necessary to examine the timing of the test signal in the external test apparatus every time the system configuration of the semiconductor integrated circuit is different, and the development period of the test program becomes long.

The object of the present invention is to provide a CPU for a semiconductor integrated circuit.
It is an object of the present invention to provide a semiconductor integrated circuit for reducing a test cost and a test program development period in a block functional test.

[0006]

According to the present invention, in a semiconductor integrated circuit having a central processing circuit, a code memory circuit for storing a code for a functional test program of the central processing circuit and a code memory circuit for operating in accordance with the functional test program are provided. A data memory circuit that stores data expected to be output by the central processing unit, and a function test program in a code memory circuit that is selected by an address signal output from the central processing unit in response to a predetermined test input. The central processing circuit is operated according to the code for use, the data output from the operating central processing circuit is compared with the stored contents of the data memory selected by the address signal, and the central processing unit is based on the comparison result. And a control circuit for detecting the presence or absence of a failure of the semiconductor integrated circuit.

[0007]

According to the present invention, a semiconductor integrated circuit capable of performing a functional test of a CPU block includes a code memory circuit, a data memory circuit and a control circuit. The code memory circuit stores the code for the function test program of the central processing unit. The data memory circuit stores the data expected to be output from the central processing unit when operating according to the function test program. The control circuit responds to a predetermined test input and operates the central processing circuit in accordance with the code for the function test program in the code memory circuit selected by the address signal output from the central processing circuit, and operates the central processing circuit during operation. The data output from the arithmetic processing circuit is compared with the stored contents of the data memory selected by the address signal, and the presence or absence of a failure in the central arithmetic processing circuit is detected based on the comparison result. Therefore, in the functional test of the central processing unit, the test can be performed by using a small number of input / output terminals of the central processing unit, and a highly functional external test device is unnecessary. Moreover, since the test can be performed by the test program that does not depend on the system configuration of the semiconductor integrated circuit, it is possible to reduce the test cost and the development period of the test program.

[0008]

1 is a block diagram showing a schematic electrical structure of a semiconductor integrated circuit according to an embodiment of the present invention. CPU
Reference numeral 1 is a central processing unit that is the target of a functional test. The code memory 2 stores an instruction code of a program for performing a functional test of the CPU 1 and the like. The data memory 3 stores data expected to be output from the CPU 1 when the CPU 1 operates according to the function test program,
That is, the expected value is stored. Also, the code memory 2
The same instruction code as is stored in the same address. C
Address designation from the PU 1 to the code memory 2 and the data memory 3 is performed via the address bus 4. The comparison circuit 5 compares the data output from the CPU 1 with the data output from the data memory 3. CPU1
The output of the data from the to the comparison circuit 5 is performed via the data bus 6. The data output from the data memory 3 to the comparison circuit 5 is output via the data line 7, the latch circuit 8 and the data line 9. The comparison circuit 5
Code memory 2 for data memory 3
You may store the code different from. The latch circuit 8 is
The output data of the data memory 3 is latched, and the latch timing is controlled by the gate (GATE) signal output from the control signal generation circuit 11. When the GATE signal is not input, the output data of the data memory 3 is
It is directly output to the comparison circuit 5.

The decoder 13 is a decoder for generating a data read (RMRD1) signal 15 of the code memory 2. The decoder 14 is a decoder for generating a data read (RMRD2) signal 16 of the data memory 3. The decoder 13 and the decoder 14 have a C
Bus acknowledge (BUSAK) output from PU1
Signal 20, M1 cycle (M1) signal 21, memory request (MREQ) signal 22, IO request (IOR)
The Q) signal 23, the read (RD) signal 24, and the write (WR) signal 25 are input. Control signal generation circuit 11
Is a circuit for generating a control signal for the CPU 1, and C
An arbitrary control signal can be generated by designating an address from PU1 via the address bus 4. In the control signal generation circuit 11, the interrupt request (IN
T) signal 26, non-maskable interrupt (NMI) signal 2
7. A bus request (BUSRQ) signal 28 and a wait (WAIT) signal 29 can be output.

A clock (CKL) signal 30 and a reset (RESET) signal 31 are signals that are externally input to the CPU 1 in order to set conditions for a functional test.
The test (TEST) signal 32 is a signal for bringing the CPU 1 into a testable state. Test result (RESULT)
The signal 33 outputs the determination result of the comparison circuit 5, and the result of the function test can be confirmed. Reference numeral 40 indicates a CPU block that performs a functional test.

When carrying out a functional test of the CPU block 40, a low level T is sent from the external functional test device to the CPU 1.
Input the EST signal 32. (All the control signals input to and output from the CPU 1 are valid at a low level.) As a result, the control signal generation circuit 11, the decoder circuit 13, and the decoder circuit 14 are in the operating state. Also at this time, CP
The control signal 38, the address bus and the data bus 39 outside the U block 40 are in a high impedance state,
The CPU block 40 is separated from the CPU block 40.
Is ready for testing.

Next, CLK is sent to the CPU 1 from the external test equipment.
The signal 30 and the low level RESET signal 31 are input. As a result, the CPU 1 is set to the initial state,
The program counter starts operation from # 0000.
At this time, the CPU 1 enters a read cycle (abbreviated as “fetch cycle”) of the instruction at address # 0000. Also CP
U1 outputs the MREQ signal 22 and the RD signal 24 to the code memory 2 and the data memory 3. As a result, the output RMRD1 signal 15 of the decoder 13 and the output RMRD2 signal of the decoder 14 become low level, and the code memory 2 and the data memory 3 become readable. Next, the contents of address # 0000 in code memory 2 are read by CPU 1. At this time, since the same instruction code as the code memory 2 is stored in the address # 0000 of the data memory 3, if the function of the CPU block 40 is normal, the data output from the code memory 2 and the data memory The data output from 3 is the same. Therefore, the RESUL output from the comparison circuit 5
The T signal 33 becomes low level. Next, the program counter of the CPU 1 is automatically incremented, the CPU 1 decodes the instruction code, and the content enters the write cycle.
In this case, the address signal A for writing from the CPU 1
The xx to A0 and the WR signal 25 are output. further,
If the content of the instruction code is a write instruction to the memory, MR
The EQ signal 22 is output, and the IORQ signal 23 is output when writing to the input / output unit. At this time, the RMRD1 signal 15 output from the decoder 13 becomes high level, and the code memory 2 becomes unreadable. Further, the RMRD2 signal 16 output from the decoder 14 becomes low level, and the data memory 3 becomes readable. In this case, the expected output value output from the data bus of the CPU 1 is stored in advance in the address of the data memory 3 designated by the CPU 1. As a result, if the function of the CPU is normal, the output data of the CPU 1 input to the comparison circuit 5 and the output data of the data memory 3 become equal, and the RESULT signal 33 is output at a low level.
Therefore, it can be determined that the function of the CPU is normal. After that, the CPU 1 sequentially increments the program counter and repeats the above-mentioned processing to test the function of the CPU block 40.

FIG. 2 is an electric circuit diagram of the decoder circuit 13 shown in FIG. RD is input to the NAND gate 41.
Signal 24 and MREQ signal 22 are provided. NAND
The RD signal 24 and the IORQ signal 2 are input to the gate 42.
3 and are given. IO is input to the NAND gate 43.
The RQ signal 23 and the M1 signal 21 are provided. The inputs of the NOR gate 44 are supplied with the outputs of the NAND gates 41, 42 and 43 and the BUSAK signal 20. NA
The output of the NOR gate 44 and the TEST signal 32 are applied to the input of the ND gate 45. These gates 41
The inputs to 45 are all negative logic. Further, all the control signals input / output from each gate are valid at a low level.
The name of each gate does not depend on the logic on the input side of Fig. 2 and below.
Determined by the logic on the output side. RD signal 24 and MR
When the EQ signal 22 is low level, the NAND gate 41 outputs a low level signal. This signal is NOR
When input to the gate 44, the NOR gate 44 outputs a low level signal. This signal and low level TE
When the ST signal 32 is input to the NAND gate 45, N
The AND gate 45 outputs the low level RMRD1 signal 15. Therefore, the RD signal 24 and the MREQ signal 2
2 and TEST signal 32 are low level, RMR
The D1 signal 15 is output at a low level. Similarly, RD
When the signal 24, the IORQ signal 23 and the TEST signal 32 are at the low level, the RMRD1 signal 15 is output at the low level, and the IORQ signal 23, the MI signal 21 and the TE are output.
When the ST signal 32 is at low level, the RMRD1 signal 15
Is output at a low level. Also, the BUSAK signal 20
And TEST signal 32 is low level, RMRD
1 signal 15 is output at a low level.

FIG. 3 is an electric circuit diagram of the decoder circuit 14 shown in FIG. RD is input to the NAND gate 51.
Signal 24 and MREQ signal 22 are provided. NAND
The RD signal 24 and the IORQ signal 2 are input to the gate 52.
3 and are given. The input of the NAND gate 53 is I
The ORQ signal 23 and the M1 signal 21 are provided. NAN
The IORQ signal 23 and the WR signal 2 are input to the D gate 54.
And 5 are given. W is input to the NAND gate 55.
The R signal 25 and the MREQ signal 22 are provided. NOR
The inputs of the gate 56 are supplied with the outputs of the NAND gates 51 to 55 and the BUSAK signal 20. The output of the OR gate 56 and the TEST signal 32 are applied to the input of the NAND gate 57. Therefore, the RD signal 24, M
When the REQ signal 22 and the TEST signal 32 are at low level, the RMRD2 signal 16 is output at low level.
Similarly, RD signal 24, IORQ signal 23 and TES
When the T signal 32 is at the low level, the RMRD2 signal 16 is output at the low level, and the IORQ signal 23 and the M1 signal 2 are output.
1 and TEST signal 32 are low level, RMR
The D2 signal 16 is output at a low level. Also, IOR
When the Q signal 23, the WR signal 25 and the TEST signal 32 are at the low level, the RMRD2 signal 16 is output at the low level, and the WR signal 24, the MREQ signal 22 and the TEST signal are output.
When the T signal 32 is at low level, the RMRD2 signal 16 is output at low level. In addition, the BUSAK signal 20
And when the TEST signal 32 is low level, RMRD2
The signal 16 is output.

FIG. 4 is an electric circuit diagram of the comparison circuit 5 shown in FIG. The data DA0-DA7 from the latch circuit 8 and the data DB0-DB7 from the data bus 6 are compared. In the circuit block 90, the data DA0 from the latch circuit 8 and the data DB0 from the data bus 6 are applied to the inputs of the AND gate 60. AND gate 7
Similarly, data DA0 and data DB0 are given to 0. The input of the AND gate 70 is negative logic. The inputs of NOR gate 80 are provided with the outputs of AND gates 60 and 70. The circuit blocks 91 to 97 also have a circuit configuration similar to that of the circuit block 91, and data DA1 to DA7.
And DB1 to DB7 are given. NAND gate 1
The output of the OR gates 80 to 87 is given to the input of 01. The input of the buffer 100 is the NAND gate 10
An output of 0 is given. The output of the buffer 101 is controlled by the RMRD2 signal 16, and the RESULT signal 33 is output.
Is output.

Therefore, when the data DA0 and DB0 are high level, or when the data DA0 and DB0 are low level, the NOR gate 80 outputs a low level signal. Furthermore, when all the output levels of the NOR gates 80 to 81 are low level and when the RMRD2 signal 16 is low level, the RESULT signal 33 is output at low level. That is, the data DA0 to DA
7 and DB0 to DB7 have the same corresponding data values, and the RMRD2 signal 16 is at low level, RE
The SULT signal 33 is output at a low level.

FIG. 5 is an electric circuit diagram of the latch circuit 8 shown in FIG. Output data D0 to D from the data memory 3
7 is latched and output to the comparison circuit 5. In the circuit block 150, the data D0 is applied to the input of the D flip-flop 110, and the GATE signal 12 is applied to the clock input CK. The input of the AND gate 120 is
The output Q of the D flip-flop 110 and the GATE signal 12
And are given. Data D0 is applied to the input of the AND gate 130, and GA is applied to the other negative logic input.
A TE signal 12 is provided. The inputs of the OR gate 140 are supplied with the outputs of the AND gates 120 and 130. The circuit blocks 151 to 157 also have a circuit configuration similar to that of the circuit block 150, and the data D1 to D7
Is given.

Data input D of D flip-flop 110
When the data D0 is input to the GATE signal 12 and the GATE signal 12 is changed from the low level to the high level at the same time, the GATE signal 1
At the rising edge of 2, the data D0 is latched and output from the output Q. While the GATE signal 12 is at the high level,
The value of output Q is retained. The latched signal is output from the output Q of the D flip-flop 110, and when the GATE signal 12 is at high level, the signal is output from the OR gate 140 via the AND gate 120. Also, G
When the ATE signal 12 is always set to the low level, the data D0 is output from the OR gate 140 via the AND gate 130. The operation of the other circuit blocks 151 to 157 is similar to that of the circuit block 150. Therefore, the data D0 to D7 are latched when the GATE signal 12 changes to the high level, are held while the GATE signal 12 is in the high level, and the OR gates 140 to 147.
Is output from. When the GATE signal 12 is at the low level, the values of the input data signals D0 to D7 are O as they are.
Output from the R gates 140 to 147.

FIG. 6 shows a control signal generation circuit 11 shown in FIG.
It is an electric circuit diagram of. Address signals A0-A15 are applied to the inputs of NAND gates 160-163. N
Of the inputs of the AND gate 160, all are negative logic except the input to which the address signal A4 is applied. NAN
Of the inputs of the D gate 161, all the inputs except the input to which the address signal A5 is applied are of negative logic. Of the inputs of the NAND gate 162, all are of negative logic except the input to which the address signal A6 is applied. Of the inputs to the NAND gate 163, all are negative logic except the inputs to which the address signal A7 is applied. Therefore, when the address signals A0 to A15 are # 0010, the NAND gate 160 outputs the BWAIT signal at a low level,
When the address signals A0 to A15 are # 0020, NAN
The BBUSRQ signal is output from the D gate 161 at a low level. Further, the address signals A0 to A15 are # 004.
At 0, the NMI signal 27 is output from the NAND gate 162 at a low level, and the address signals A0 to A15 are # 0.
When it is 080, the INT signal 2 is output from the NAND gate 163.
6 is output at low level.

The inputs of the NAND gate 170 are supplied with the outputs Q0 to Q2 of the hexadecimal counter 171 and the output of the AND gate 160. The output of NAND gate 170 is
It is input to the reset input RST of the hexadecimal counter 171. The inputs of the NOR gate 172 are supplied with the outputs Q0 to Q2 of the hexadecimal counter. The output of the NOR gate 172 is given to the input of the buffer 173, and the buffer 1
The output signal WAIT 29 of 73 is controlled by the TEST signal 32. The inputs of the NAND gate 180 are the outputs Q0 to Q2 of the hexadecimal counter 181 and the NAND gate 16
And an output of 1. The output of the NAND gate 180 is input to the reset input RST of the hexadecimal counter 181. The inputs of the NOR gate 182 are supplied with the outputs Q0 to Q2 of the hexadecimal counter. The output of the NOR gate 182 is given to the input of the buffer 183, and the buffer 1
The output signal BURSQ 28 of 83 is controlled by the TEST signal 32. The output of the NAND gate 162 is given to the buffer 166, and when the TEST signal 32 is at the low level, the NMI signal 27 is output from the buffer 166 at the low level. The output of the NAND gate 163 is given to the buffer 168, and when the TEST signal 32 is low level, the INT signal 26 is output from the buffer 168 at low level. The inputs of the NOR gate 190 are supplied with the outputs of the NOR gates 172 and 182, and the GATE signal 32 is output from the NOR gate 190. The CLK signal 30 is input to the clock input CLK of the hexadecimal counters 171 and 181.

When the count value of the hexadecimal counter 171 is # 6, that is, when the outputs Q0 to Q1 are all at the high level, when the BWAIT signal is input at the low level, the output of the NAND gate 170 is output. Become low level. Therefore, the reset input R of the hexadecimal counter 171 is
ST goes to low level, the counter value is reset,
# 0. In this state, CLK
When the signal 30 is input, counting is performed at the rising edge of the CLK signal 30, and the count value is output to the outputs Q0 to Q2. The outputs from the output terminals Q0 to Q2 are valid at a low level, and any one of the outputs Q0 to Q2 is at a low level until the count value changes from # 0 to # 6. At that time, the output value of the OR gate 172 is always at the low level. Therefore, in TEST mode, B
The WAIT signal 29 can be output at a low level from the time when the WAIT signal is input at a low level and the hexadecimal counter starts counting until the count value reaches # 6.

FIG. 7 is a time chart when the WAIT signal is generated in the control signal generating electric circuit shown in FIG. The value of the address signals Axx to A0 is # 00.
At 10, the control signal BWAIT is output at a low level. Next, the hexadecimal counter 171 is reset when the input RST becomes low level, and the outputs Q0 to Q2 become low level. Next, when the CLK signal is input to the clock input CLK of the hexadecimal counter 171, counting is started, and the count value is output to the outputs Q0 to Q2. Output Q1
~ If at least one of Q2 goes low, W
The AIT signal goes low and the GATE signal 12 goes high. This state is maintained until the count value of the hexadecimal counter 171 becomes # 6. WA shown in FIG.
When the IT signal 29 is input to the CPU 1 at low level,
The CPU 1 is in the standby state and continues until the WAIT signal 29 becomes high level. Also, GATE signal 1
When 2 becomes high level, the latch circuit 8 is activated and the address signal Axx to A0 latches the DATA 200 read from the data memory 3 in # 0010. The latched value is held while the GATE signal 12 is at low level. If the function of the CPU 1 is normal, the values of the address signals Axx to A0 are fixed while the WAIT signal 29 is at a low level, so that the DATA 201 output from the code memory 2 is constant. Therefore, the DATA 200 of the data memory 3 and the DATA 201 of the code memory 2 both have the same address and are the same. As a result, the RES of the comparison circuit 5
The output of the ULT signal 33 becomes low level. But C
If the function of PU1 is not normal and the standby state does not occur even when the WAIT signal 29 is at the low level, reference numeral 2
When the CLK signal in the state of 05 is input, the program counter is incremented. In that case, the CPU 1 reads the instruction code 202 stored at the next address from the code memory 2. Therefore, since the data 200 of the data memory 3 and the output data 202 of the code memory 2 in this case are different, the RESULT signal 33 becomes high level and C
A defect in the function of PU1 can be detected. Control signals such as the INT signal 26, NMI signal 27 and BUSRQ signal 28 can also be functionally tested in this manner.

To put the CPU block 40 into an actual operating state, the TEST signal 32 is input at a high level. Thereby, the output signals R of the decoder 13 and the decoder 14
The MRD 115 and the RMRD 216 are at a high level, and the code memory 2 and the data memory 3 are inaccessible. Further, the control signal output from the control signal generation circuit 11 is also in a high impedance state, and C
The control signal 38 outside the PU block 40 is ready for input. Therefore, the CPU block 40 can be put into an actual operating state.

[0024]

As described above, according to the present invention, in the function test of the central processing unit, the function test program stored in the code memory circuit is executed to output the data output from the code memory circuit and the central processing unit. By comparing the data output from the data memory circuit and the data output from the data memory circuit, it is possible to detect the presence or absence of a failure in the central processing unit.

Therefore, in the functional test of the central processing unit, the test can be performed by using only a small number of input / output terminals of the central processing unit, and a high-performance external test device is unnecessary. Further, in a semiconductor integrated circuit having a large number of blocks including a central processing unit, the central processing unit per block is tested with a small number of input / output terminals, so that a parallel test can be easily performed on a large number of blocks. be able to. Moreover, since the test can be performed by the test program that does not depend on the system configuration of the semiconductor integrated circuit, it is possible to reduce the test cost and the development period of the test program.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic electrical configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is an electric circuit diagram of a decoder circuit 13 shown in FIG.

3 is an electric circuit diagram of a decoder circuit 14 shown in FIG.

4 is an electric circuit diagram of a comparison circuit 5 shown in FIG.

5 is an electric circuit diagram of a latch circuit 8 shown in FIG.

6 is an electric circuit diagram of a control signal generating circuit 11 shown in FIG.

7 is an electric circuit for generating a control signal shown in FIG.
It is a time chart at the time of generating a WAIT signal.

[Explanation of symbols]

 1 CPU 2 Code Memory 3 Data Memory 4 Address Bus 5 Comparison Circuit 6 Data Bus 7 Data Line 8 Latch Circuit 9 Data Line 11 Control Signal Generation Circuit 12 GATE Signal 13 Decoder Circuit 14 Decoder Circuit 15 RMRD1 Signal 16 RMRD2 Signal 20 BUSAK Signal 21 M1 signal 22 MREQ signal 23 IORQ signal 24 RD signal 25 WR signal 26 INT signal 27 NMI signal 28 BUSRQ signal 29 WAIT signal 30 CLK signal 31 RESET signal 32 TEST signal 33 RESULT signal 38 control signal 39 address block, data bus

Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI technical display location // H01L 21/66 F 8406-4M (72) Inventor Hiroshi Uemura 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Within Sharp Corporation (72) Inventor Katsuyuki Nakano 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Within Sharp Corporation (72) Nobuhiro Okano 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Sharp Corporation Within

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having a central processing circuit, a code memory circuit for storing a code for a functional test program of the central processing circuit, and an expectation that the central processing circuit outputs when operating in accordance with the functional test program. The data memory circuit that stores the data to be stored and the central processing circuit that operates according to the code for the function test program in the code memory circuit that is selected by the address signal output from the central processing circuit in response to a predetermined test input. Control for comparing the data output from the operating central processing circuit with the stored contents of the data memory selected by the address signal, and detecting the presence or absence of a failure of the central processing unit based on the comparison result. And a semiconductor integrated circuit.