JP2808985B2 - Information processing device and debug device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to a debugging apparatus used when developing an apparatus to which the information processing apparatus is applied, and a central processing unit mounted on the debugging apparatus.

[0002]

2. Description of the Related Art First, a scan path which is an inspection means in an information processing apparatus will be described. FIG. 3 schematically shows the internal structure of a general information processing device 45. In practice, the situation is further complicated by a loopback circuit or the like. The information processing device 45 is composed of a combination circuit 46 in which a unique output is determined when an input is determined, and a sequential circuit 47 in which an internal state is retained and an output is not determined only by determining an input. The combinational circuit 46 includes an AND gate and the like, and the sequential circuit 47 includes a latch circuit.

In order to perform an operation test on an information processing apparatus, a test pattern is input from an input terminal, and a pattern output to an output terminal is compared with an expected value. As an input pattern, a pattern that basically changes all the states of the internal sequential circuit is required, but to change the state of the sequential circuit far from the input terminal, a complex input pattern sequence is input from the input terminal. Need to
It was virtually impossible.

Therefore, as shown in FIG. 4, a new test mode terminal 19 is provided, and when the terminal 19 is inactive, the original connection state of the information processing device is set. Connect to the inputs of other latches and all the clock inputs of the latches, and take out the first latch input, last latch output, and clock input to external terminals. Then, the latches are connected in series as shown in FIG. 4 to constitute a shift register.

Here, scan path clock input terminal 1
By inputting a test clock to 8, the contents of the latch are sequentially output to the output terminal 17, and it is possible to know what value has been set in each latch 48. Further, by setting a value to the scan path data input terminal 21 and inputting a pulse to the scan path clock input terminal 18, an arbitrary value can be set to the latch 48, and the inspection can be easily performed. Such an inspection means is called a scan path method.

Next, a pipeline process used as a means for improving the performance of an information processing apparatus in recent years will be described with reference to FIG. In the pipeline processing, one instruction is decomposed into several basic operations (called stages), and this is temporally processed. In the example given here, one instruction is used for five basic operations (IF, RD, AL
U, MEM, WB).

[0007] Instructions are read in the IF stage, and instruction decoding and register reading are performed in the RD stage. A
Perform operations (operations, etc.) at the LU stage and
The memory is accessed at the M stage. In the last WB stage, writing to the register is performed. By preparing hardware that executes the basic operation at the same time, five instructions are being processed in parallel at a certain point in time.

When such pipeline processing is performed, an event called a delay slot occurs. In this example, two delay slots, a load delay slot and a branch delay slot, occur. FIG.
Since the data is read from the external memory in the process of processing the load instruction (instruction 1), the value is not determined until the MEM stage of the load instruction ends. Therefore, in the next instruction (instruction 2), the value loaded by the load instruction is
Cannot be used on stage. It can be used in the next instruction (instruction 3). This part of the instruction 2 is called a load delay slot.

In FIG. 7B, the branch instruction (instruction 1) is decoded (register read) at the RD stage, and the branch address is determined. At that time, the processing of the IF stage of the next instruction (instruction 2) has already been completed. Therefore, the instruction fetch of the branch address can be performed only by the next instruction (instruction 3). The part of this instruction 2 is called a branch delay slot, and this instruction (instruction 2) is always executed regardless of branching.

In order to avoid such a delay slot, there are a method of providing a hardware control circuit and a method of processing by software. In the case of software processing, when a delay slot occurs, a method of temporarily stopping the flow of the pipeline and removing the next instruction from the delay slot is adopted. In the case of software processing, a method of changing the order of instructions so as to use delay slots effectively is used. In addition, there are various methods for avoiding this.

FIG. 8 shows an internal structure of a pipeline type microprocessor employing the above-described scan path system, mainly on a processing path. The double-lined block is a controller block that controls the processing of each stage. Although each signal / latch is represented by one line / latch for simplicity of the drawing, it is actually composed of a plurality of signal lines / latches. Although not shown in the drawing, the scan path circuit is incorporated in the latch, and only an excerpt of the data path of the scan path is shown in the drawing.

The IF stage has an IF block 1,
Data, that is, an instruction code is read from the instruction input terminal 23 and passed to the latch 2. The instruction code passed through the latch 2 is passed to the RF block 3 and the CDE block 4.

The RF block 3 determines a register referred to from the instruction code, opens a predetermined three-state buffer 13, and passes register data to the latch 6. At the same time, the DEC block 4 decodes the instruction and passes the result to the latch 5. The contents of the register and the instruction decode result passed through the latch 5 are passed to the ALU block 7, where the operation is executed, and the result is passed to the latch 8.

The operation result passed through the latch 8 is passed to the MEM block 9, where necessary, data is exchanged with the data exchange terminal 24, and the result is passed to the latch 10. The data passing through the latch 10 is transferred to the WB block 11, and the result is written to the latch 12, which is a register. The clock signal of the latch dividing each stage is connected to the clock input terminal 22 of the microprocessor.
As described above, by dividing each stage in time using the latch, a pipeline operation can be realized.

Next, a debugging device for checking whether the information processing device is operating properly will be described. Here, a microprocessor application product is taken as an information processing device.

FIG. 9 shows a microprocessor application product 39.
And a schematic configuration of a debugging device. As hardware of the microprocessor application product 39, a microprocessor 40, a RAM 42, a ROM 41, an I / O
43. The debug device is probe 2
A means for connecting the microprocessor application product 39 and the like to the debug device, and the debug microprocessor 3
3 and an event detection circuit 28 for detecting various events, and other control circuits, and has a user interface such as a console 30 for displaying debug information and inputting commands for controlling the debug device.

The microprocessor 40 is withdrawn from the microprocessor application product 39, a debug device is connected to the microprocessor 40 via the probe 26, and the microprocessor application product 39 is controlled from the debug device. Is displayed on the console 30 or changed to confirm the operation.

An important function of the debugging device is a break function. The internal configuration of the debug device will be described focusing on a method for realizing a break function. A debugging microprocessor 33 is provided in the debugging device. The debugging microprocessor 33 has a function of an ordinary microprocessor 40 and a break at the break input terminal 20 for forcibly changing the program execution similar to an interrupt signal to a predetermined program entry. Signal.

The event detection circuit 28 detects an external event 3
2 (for example, data has been written to a certain address)
A break signal is generated at the break input terminal 20. The buffer 3 connected to the probe 26
The control signal for turning off the buffer 4 and opening the buffer 35 of the internal bus 31 is also generated.

The internal bus 31 has a debug program 3
8 and I / O 29 are connected. The console 30 is connected to the I / O 29. The debug microprocessor 33 inactivates the buffer control signal during execution of the user program, and
And open the resources (R
OM41, RAM42, I / O43).

When an event is detected by the event detection circuit 28, the break signal at the break input terminal 20 is activated and the buffer control signal is activated. Then, the debug microprocessor 33 is connected to the internal bus 3
1 (debug program 38, I / O 29, event detection circuit 28).

The debug program 38 stores a program for outputting internal information (for example, the contents of a register) of the microprocessor 33 (for debugging) and performing command processing according to a command from the console 30. To execute the user program from the break operation, the register value is set under the control of the debug program 38 on the internal bus 31, the internal buffer 35 is cut off when the control is passed to the user program, and the buffer on the probe side is turned off. 34 is opened and the control is transferred to the user program on the microprocessor application product 39.

This operation is shown in FIG. As described above, by exclusively controlling the resources on the microprocessor application product and the resources on the internal bus, the program execution is interrupted when a predetermined event occurs, and debugging such as checking the state of the microprocessor is performed. Had become.

[0024]

In a debugging apparatus for an information processing apparatus (microprocessor) using the above-described pipeline processing, control is transferred to a debug program by a break operation at the time of a break, register storage is performed, and return from the break operation is performed. Sometimes, register loading was performed and control was transferred from the debug program to the user program by a branch instruction. Therefore, a load delay slot and a branch delay slot are generated, and a means for avoiding the load delay slot and the branch delay slot must be prepared, so that the debugging device is complicated.

Further, from the viewpoint of the pipeline structure, when the control is transferred to the user program, the pipeline state is not the original state. An operating program may operate abnormally.

Further, in recent information processing apparatuses, the processing speed (clock frequency) increases, and the switching between the internal bus and the probe buffer cannot be made in time, or the probe buffer reduces the AC characteristics such as the output delay time of the microprocessor (for debugging). As a result, a gap has arisen between the operation of the actual microprocessor application product and the operation of connecting the debugger, which has been a problem.

An object of the present invention is to provide an information processing apparatus and a debugging apparatus which avoid problems caused by a change in pipeline state.

[0028]

In order to achieve the above object, an information processing apparatus according to the present invention divides one instruction into a plurality of basic operations, and temporally divides the basic operations to advance processing. In a pipeline processing type information processing apparatus, a means for temporarily stopping a pipeline operation in response to an external request and a method for temporarily stopping the pipeline operation are provided.
At the same time, the pipeline is set to the test mode, and the test is performed.
By inputting a clock, the pipeline
Test output or test input of sequential circuit information
And a scan path circuit for one of the pipeline
The scan path operation is performed in a stopped state .

Moreover, debugging device according to the present invention, the
Operation of an application product of the information processing device using the information processing device
Confirm / change the status where the
In a debugging device to confirm the operation of the application product.
Te, operates the scan path circuit, and has a means for setting / displaying the internal state of the information processing apparatus from the information.

[0030]

In the information processing device, the pipeline operation is temporarily stopped at the time of a break, and the internal state of the information processing device is read out from the debug device or set by the scan path method while the pipeline operation is stopped.

In a debug device using such an information processing device, the pipeline is stopped at the time of a break operation, and debug information is taken out or set using the scan path method.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a diagram mainly showing a pipeline state of an information processing apparatus (microprocessor) according to an embodiment of the present invention.

In this embodiment, in the present embodiment, a signal obtained by inverting a break signal from a break input terminal 20 by an inverter gate 15 and an A signal to a clock input terminal 22 are different from the pipeline flow chart of the conventional microprocessor shown in FIG.
An ND gate 16 is added, and a break input terminal 20 and a scan path mode setting input terminal (TEST terminal) 19
Has an OR gate 14 added.

When a break request is received in such a microprocessor, the clock to the latch is stopped, so that the microprocessor stops with the pipeline held. Also,
At the same time, the scan path test mode signal becomes active, and all the latches are connected to the scan path data input terminal (T
A shift register having an IN terminal 21 as an input and a scan path data output terminal (TOUT terminal) 17 as an output is constituted, and a pulse is applied to a scan path clock input terminal (TCK) 18 to sequentially extract or set contents. Or be able to.

In such a microprocessor,
To display the contents of a register in the break state, use TOU
Since the data string output first from the T terminal 17 represents the contents of the register, this can be realized by displaying this serial data as parallel data of the register width.

To change the contents of the register, the register data (parallel data) to be set is changed to serial data, input from the TIN terminal 21, and the TCK 18
Can be set by inputting a pulse a predetermined number of times.

In addition, the data of each stage can be changed. For example, the instruction in the pipeline can be changed by changing the value of the latch 2 of the IF block, and the operation result can be corrected by changing the value of the latch 8 of the ALU block.

When the control is returned to the user program, the pipeline state is restored by inputting the data taken out of the TIN 21 at the time of the break, and the break signal at the break input terminal 20 is released to include the pipeline state. To return to the user program.

As a second embodiment of the present invention, FIG. 2 shows a configuration diagram of a debugging device using the above-mentioned microprocessor. The debug microprocessor 25 is directly connected to the probe 26, and the scan path control signal of the debug microprocessor 25 is connected to the scan path control circuit 27.

A break signal from the break input terminal 20 of the event detection circuit 28 is connected to the scan path control circuit 27 so that it is possible to detect whether or not a break state has occurred.

Further, it is also connected to the internal bus 31 to transfer the microprocessor internal information described in the first embodiment to the I / O 29.
Display on the console 30 through the
A route that can be changed in accordance with an instruction from is configured. The buffer switching signal output from the event detection circuit 28 is unnecessary.

[0042]

As described above, the present invention changes the pipeline flow by suspending the pipeline operation when a break request is received and reading / writing the internal state of the information processing device via the scan path. The result is that the internal state can be changed without having to do so. As a result, it is possible to avoid a malfunction due to the delay slot, which is a problem in the conventional debugging device.

Further, as shown in the second embodiment, the buffer for switching between the probe and the internal bus is not required, the delay in processing speed and the change in AC characteristics due to the buffer are eliminated, and the difference between the operation of the debugging device and the actual operation of the microprocessor is eliminated. There is an advantage that can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a microprocessor according to the present invention.

FIG. 2 is a diagram showing a debugging device according to the present invention.

FIG. 3 is a diagram illustrating an internal structure of the information processing apparatus.

FIG. 4 is a diagram illustrating a scan path method.

FIG. 5 is a diagram showing a pipeline processing method.

FIG. 6 is a diagram illustrating a load delay slot operation.

FIG. 7 is a diagram illustrating a branch delay slot operation.

FIG. 8 is a configuration diagram showing a conventional pipeline processing microprocessor.

FIG. 9 is a diagram showing a relationship between a microprocessor application product and a debugging device.

FIG. 10 is a diagram showing a user program / debug program control flow in a conventional debug device.

[Explanation of symbols]

Reference Signs List 1 IF block (instruction fetch operation control) 2 Latch (for IF block) 3 RF block (register fetch operation control) 4 DEC block (instruction decode operation control) 5 Latch (for DEC block) 6 Latch (for RF block) 7 ALU Block (arithmetic operation control) 8 Latch (for ALU block) 9 MEM block (memory access control) 10 Latch (for MEM block) 11 WB block (write-back operation control) 12 Latch (register) 13 3-state buffer (for register output) 14 OR gate 15 Inverter gate 16 AND gate 17 Scan path data output terminal 18 Scan path clock input terminal 19 Scan path mode setting input terminal 20 Break input terminal 21 Scan path data input terminal 22 Clock Input Terminal 23 Command Input Terminal 24 Data Exchange Terminal 25 Debug Microprocessor 26 Probe 27 Scan Path Control Circuit 28 Event Detection Circuit 29 I / O (for Debug Device) 30 Console 31 Internal Bus 32 External Event 33 For Conventional Debugging Microprocessor 34 buffer (microprocessor bus for debugging ←
→ Probe 35 buffer (microprocessor bus for debugging)
→ Internal bus) 36 Inverter 37 Debug microprocessor bus 38 Debug program 39 Microprocessor application product 40 Microprocessor 41 ROM 42 RAM 43 I / O 44 Microprocessor bus 45 Information processor 46 Combination circuit 47 Sequential circuit 48 Latch

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/38 G06F 11/22 G06F 11/28

Claims (2)

(57) [Claims] 1. An instruction is divided into a plurality of basic operations.
In the pipeline processing-type information processing apparatus proceed by dividing the basic operation time, in response to a request from an outside, and means for temporarily stopping the pipeline operation, the pipeline operation with temporarily stopping, the path
Set the pipeline to test mode and set the test clock
By inputting, the internal sequential circuit of the pipeline
The test output or the test input
A scan circuit in a state where the pipeline is temporarily stopped.
An information processing device for performing a pass operation . 2. The information processing apparatus according to claim 1, wherein
A state in which the operation of an information processing device application product was forcibly interrupted.
Confirm / change the status to confirm the operation of the application product.
A debug apparatus for operating the scan path circuit and setting / displaying an internal state of the information processing apparatus based on information of the scan path circuit.