JPH06119258A - Trace marking circuit of common bus - Google Patents

Abstract

PURPOSE:To embody the trace marking circuit for writing a fact that valid data which coincide with a trigger condition is written in a free bit of a trace RAM, with regard to the trace marking circuit for collecting the data which coincide with a prescribed trigger condition out of the data on a common bus of a multi-processor system constituted of plural processors. CONSTITUTION:The circuit is provided with a trace random access memory 10, a trigger condition deciding part 20, a valid data display generating part 30, a trace pointer counter 40, and a processor 50, and constituted so that in the case it is decided that data on a common bus 100 coincide with a prescribed trigger condition, a signal of a '1' level is outputted from the valid data display generating part 30, the data of the common bus 100 is written in the trace random access memory 10, and simultaneously, the data of a '1' level is written in a free bit of the same address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trace marking circuit which collects, from among data on a common bus of a multiprocessor system composed of a plurality of processors, data which matches a predetermined trigger condition.

FIG. 5 is a diagram illustrating an example of a multiprocessor system. The figure is an example of a mobile communication system,
The host controller 1 houses a plurality of controllers 2, and the controller 2 houses a plurality of mobile units 3.

Since such a mobile radio system is required to have high reliability, the host controller 1 is a multiprocessor system using a plurality of processors (hereinafter referred to as CPUs) 51 to 5n, and a plurality of CPUs 51.
.About.5n are connected by a common bus 100, and various data, addresses, control signals, etc. are transmitted and received to control.

In the figure, 10 is a random access memory for trace (hereinafter referred to as RAM), 80 is a memory for system control, and 90 is an interface for I / O.

Such a multiprocessor system is
For example, even if one CPU fails, the load is shared by the other CPUs, so that the function of the entire system is not impaired even if the processing speed may be slightly reduced. .

In such a multiprocessor system, data on the common bus is collected in a trace RAM under a certain trigger condition and analyzed to detect normal / abnormal operation of the system.

For example, when the system is connected to a plurality of I / Os, it is possible to check the normality of the specified I / O by specifying the I / O address and collecting the data.

[0008]

2. Description of the Related Art FIG. 6 is a block diagram for explaining a conventional example. In the figure, 100 is a common bus for connecting a CPU (not shown) of the multiprocessor system, 10 is a trace RAM for writing trace data, and 20 is a trigger for determining that the data on the common bus 100 matches a specified trigger condition. A condition determination unit, 40 is a trace pointer counter that generates an address for writing data that matches a specified trigger condition on the common bus 100, 50 is a CPU that fetches trace data and executes various processes, 70 is a trace pointer counter 40 This is a trace pointer register for writing the address generated by.

In this configuration, the trigger condition judging section 20
Constantly monitors the data on the common bus 100, and if the data wants to check the specified trigger condition, for example, the normality of the specified I / O, the specified I The data designating the / O address is collected in the trace RAM 10 as trace marking data.

The CPU 50 polls the trace pointer register 70 to check the contents, and when the pointer value of the trace pointer register 70 is increased and new data is taken in the trace RAM 10,
The CPU 50 reads the data in the trace RAM 10 and analyzes the data.

[0011]

In the above conventional example, the contents of the trace pointer register 70 are stored in the CPU 5
By checking from 0, it is determined whether or not new data has been fetched.

Therefore, it is necessary for the trace pointer register 70 to be able to see all the bits of the trace pointer counter 40, and the trace RA
When the capacity of M10 increases, the number of bits of the trace pointer counter 40 also increases, so that the number of parts such as an integrated circuit for configuring the trace pointer register 70 also increases.

Since the operation of the CPU 50 and the operation of the trace pointer counter 40 are not synchronized, the CPU
The counter 50 for trace pointer may count up while 50 is reading the register 70 for trace pointer, the value of the register 70 for trace pointer may change, and the value of the register 70 for trace pointer may not be read correctly. Therefore, it is necessary for the CPU 50 to read twice and compare and check.

According to the present invention, when the data on the common bus matches the specified trigger condition, and when the data is written to the trace RAM, the fact that the data matches the trigger condition and valid data is written is set in the trace RAM. An attempt is made to realize a common bus trace marking circuit having a simple configuration in which a free bit is written and a check is made to determine whether valid data has been written.

[0015]

FIG. 1 is a block diagram for explaining the principle of the present invention. In the figure, 100 is a common bus of a multiprocessor system including a plurality of processors, 10 is a trace RAM for writing data of the common bus 100 that matches a predetermined trigger condition, and 2
Reference numeral 0 is a trigger condition determination unit that determines whether or not the data on the common bus 100 matches a predetermined trigger condition, and reference numeral 30 is a trigger condition determination unit 20 that determines that the data on the common bus 100 matches the trigger condition. At this time, it is a valid data display generation unit that generates a "1" level signal indicating that the data written in the trace random access memory 10 is valid data.

Reference numeral 40 is a trace pointer counter for generating a data write address of the trace RAM 10, and reference numeral 50 is a processing device for reading the data written in the trace RAM 10, by the trigger condition judging section 20. When it is determined that the data on the common bus 100 matches the predetermined trigger condition, the valid data display generation unit 30 outputs a signal of "1" level and the data of the common bus 100 is written in the trace RAM 10 at the same time. , Write "1" level data to empty bits at the same address.

[0017]

The trigger condition judging section 20 constantly monitors the data on the common bus 100, and outputs a write signal (indicated by WRITE in the figure) when a predetermined predetermined trigger condition is met and outputs valid data. The unit 30 is activated to generate a "1" level signal indicating that the trigger condition is met.

The write signal is used to write the data on the common path 100 to the address of the trace RAM 10 generated by the trace pointer counter 40, and the "1" level signal generated by the valid data display generation unit 30 is applied to the empty bit at the same address. Write. At this time, since the clock signal (indicated by CLK in the figure) is input to the trace pointer counter 40, the count value is increased, and the address for the next information acquisition is generated.

The CPU 50 searches for an empty bit in the trace RAM 10 and, if "1" is written, determines that valid data matching the trigger condition has been written, and reads the data.

[0020]

FIG. 2 is a block diagram illustrating an embodiment of the present invention. In the figure, 100 is a common bus connecting a processor (not shown) of the multiprocessor system, 10 is a trace RAM, and 20 is a trigger condition determination unit that determines that the data of the common bus 100 matches a specified trigger condition.
R is a resistance as the effective data display generation unit 30, and
It is pulled up to 5V.

Further, 40 is a counter for a trace pointer that generates an address for writing data that matches the trigger condition specified by the common bus 100, 50 is a CPU that fetches trace data and executes various processes, and B1 to B4 are buffers. .

The trigger condition judging unit 20 monitors the data on the common bus 100, generates a write signal when the trigger condition is met, and outputs the data from D0 to D0 of the trace RAM 10.
Write to D6 bit. At this time, at the same time, "1" is written in the free bit D7 of the same address.

A clock signal is input to the trace pointer counter 40, and the counter is incremented to indicate the write address of the next data. CPU50 is trace R
Search AM10 and set "1" to D7 bit of empty bit.
The information of the pointer with "" is processed as valid data that matches the trigger condition, and after processing, "0" is written to the empty bit D7 to indicate that processing has been completed.

In this way, it is possible to determine that the pointer data whose empty bit D7 contains "0" is invalid or has been processed. FIG. 3 shows a block diagram (1) for explaining another embodiment of the present invention. FIG. 3 shows that in the configuration of FIG. 2, the trigger condition generator 40 writes "1", which is output when it detects that the trigger condition is met, into the empty bit D7 of the trace RAM 10 as a signal for displaying valid data. It is configured in.

Operation of writing data matching the trigger condition on the common bus 100 into the trace RAM 10, CPU
Processing such as search from 50 is the same as that in the embodiment of FIG. FIG. 4 shows a block diagram (2) for explaining another embodiment of the present invention. 4 has a configuration in which a flip-flop circuit (hereinafter referred to as an FF circuit) 60 is provided in the configuration of FIG.

In FIG. 4, empty bits are represented by D6 and D7.
2 bits, D7 bit is pulled up through a resistor R, and D6 is a trace pointer counter 4
A signal that is inverted every time 0 is rotated is input.

The input terminal D of the FF circuit 60 is connected to the inverting output terminal × Q, and the trace pointer counter 40
Invert operation is performed each time a Count Up signal that is output every one cycle is input.

With this configuration, when the trace RAM 10 is used cyclically, if D1 bit is set to "1", it is determined that valid data is written at the address indicated by the pointer. , If the D6 bit is written with "0", the first write data is determined, and if the D6 bit is written with "1", the data is determined to be overwritten data and the data processing is performed.

[0029]

According to the present invention, data indicating that the data on the common bus matches the specified trace condition is written in the empty bit of the trace RAM, and the empty bit data is searched when the CPU searches. By checking, it is possible to determine whether or not valid data has been written, so that the hardware configuration becomes simple, and the double reading from the CPU, which has been necessary in the past, is not necessary and the processing becomes simple.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram illustrating an embodiment of the present invention.

FIG. 3 is a block diagram (1) explaining another embodiment of the present invention.

FIG. 4 is a block diagram (2) illustrating another embodiment of the present invention.

FIG. 5 illustrates an example of a multiprocessor system.

FIG. 6 is a block diagram illustrating a conventional example.

[Explanation of symbols]

 100 Common Bus 10 Trace RAM 20 Trigger Condition Judgment Unit 30 Effective Data Display Generation Unit 40 Trace Pointer Counter 50-5n CPU 60 FF Circuit 70 Trace Pointer Register 80 Memory 90 Interface B1-B4 Buffer R Resistance 1 Upper Control Device 2 Control device 3 Mobile unit

Claims (2)

[Claims] 1. A trace marking circuit that collects, from data on a common bus (100) of a multiprocessor system including a plurality of processors, data that matches a predetermined trigger condition. A trace random access memory (10) for writing the matched data of the common bus (100), and a trigger condition determination unit (20) for determining whether or not the data of the common bus (100) matches a predetermined trigger condition. )
When the trigger condition determination unit (20) determines that the data on the common bus (100) matches the trigger condition, the trace random access memory (1
A valid data display generation unit (30) that generates a signal of "1" level indicating that the data written in 0) is valid data, and a write address of the data of the trace random access memory (10). A trace pointer counter (40) and a processing device (50) for reading data written in the trace random access memory (10), and the trigger condition determination unit (20) allows the common bus ( 100), when it is determined that the above data matches a predetermined trigger condition, the valid data display generation unit (30) outputs a signal of “1” level, and the trace random access memory (10) is set to the above At the same time as writing the data on the common bus (100), write "1" level data to the empty bit at the same address. Trace marking circuit common bus, characterized in that. 2. The trace marking circuit for a common bus according to claim 1, further comprising a flip-flop circuit (60) for outputting a signal indicating that the random access memory for tracing (10) is cyclically used, At the same time that the data of the common bus (100) is written to the random access memory (10), the "1" level signal output from the valid data display generation unit (30) is written to the first empty bit of the same address. 2. The common according to claim 1, wherein "0" indicating the first write data generated by the flip-flop circuit (60) or "1" indicating overwrite data is written in the second empty bit of the same address. Bus trace marking circuit.