JP2000224174A - Atm communication controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ATM communication controller with which a microprocessor can access a plurality of PHY devices, without provision of an external circuit. SOLUTION: A management interface 5 conducts control and acquisition of a status of a line fault and performance detailed causes of PHY devices 3a-3c by read/write of internal registers of the PHY devices 3a-3c, detection of interrupt signals from the PHY devices, and reset to each PHY device. Thus, a chip select signal to the PHY devices generated by an address decoder is outputted. Or a PHY device ID is outputted, and the PHY device decords an address to individually access a plurality of the PHY devices.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM communication control device, and more particularly to an ATM communication control device having a management interface for performing register access to individual PHY devices, resetting, and detecting interrupts from individual PHY devices. .

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing an example of a conventional ATM communication control device. In FIG. 1, a microprocessor 1 is connected to an ATM (Asynchronous Transfer Model) layer device 2 via a bidirectional bus. The ATM device 2 is connected to a plurality of (here, three as an example) PHY devices 3a to 3c. The interface between the ATM layer device 2 and the PHY devices 3a to 3c has a UTOPIA (Universal Test) for transferring transmitted and received cell data.
& Operations PHY Interface for ATM) Level2
Interface 4 is used. The microprocessor 1 and the ATM layer device 2 are connected to the PHY devices 3a to 3c via the address decoder 6.

In this conventional ATM communication control device, the PH
In order to control or read the status of the internal registers of the Y devices 3a to 3c by reading / writing,
From the microprocessor 1, register addresses and data of the PHY devices 3a to 3c, and other information such as "RW_B" and "C
S_B ”and“ OE_B ”are driven.These signals are valid for all the PHY devices 3a to 3c, so that the PHY devices 3a to 3c cannot be individually controlled. Device 3
a to 3c are individually controlled by an address decoder 6 for decoding an address from the microprocessor 1.
And it is necessary to access one PHY device.

[0004] In addition, resetting of the plurality of PHY devices 3a to 3c cannot be performed individually because the signal "RST_B" is a signal common to all the PHY devices 3a to 3c on the bus. , All the PHY devices 3a to 3c are reset at the same time.

When an interrupt signal is raised from a plurality of PHY devices 3a to 3c, the individual PHY devices 3a to 3c are sequentially used by an address decoder 6 in order to know which PHY device the interrupt is from. 3c
Must be accessed.

[0006]

As described above, in the above-described conventional ATM communication control apparatus, in order for the microprocessor 1 to access the plurality of PHY devices 3a to 3c, the address decoder 6 for decoding the address is used. is necessary. Further, there is a problem that the PHY device cannot be reset individually. Further, in order to recognize from which of the PHY devices 3a to 3b the interrupt signal is output, it is necessary to check the register of each PHY device, and therefore, it takes a long time to recognize the interrupt signal. is there.

[0007] The present invention has been made in view of the above points,
It is an object of the present invention to provide an ATM communication control device capable of accessing a plurality of PHY devices from a microprocessor without providing an external circuit.

Another object of the present invention is to provide a plurality of PHYs.
Interrupt signals from devices can be detected individually,
An object of the present invention is to provide an ATM communication control device capable of individually resetting a plurality of PHY devices.

[0009]

In order to achieve the above object, the present invention provides a plurality of PHY devices each having at least an internal register, individual control and status acquisition of the plurality of PHY devices, and a plurality of PHY devices. In order to individually detect an interrupt signal and reset a desired PHY device among a plurality of PHY devices,
The address input from the microprocessor is decoded to output a common address signal for the plurality of PHY devices and an individual chip select signal for the plurality of PHY devices, and to individually reset the read / write signal and the plurality of PHY devices. Signal, multiple PHYs
An ATM layer device including a management interface provided between the plurality of PHY devices and the ATM layer device, each of which outputs a signal for activating an output line of the device and detects an interrupt signal from the plurality of PHY devices; , A function of outputting an address signal to an ATM layer device, a function of identifying which PHY device is an interrupt signal among a plurality of PHY devices based on a signal from the ATM layer device, and reading of a plurality of PHY devices. / A microprocessor having at least a function of controlling the light.

Further, in order to achieve the above object, the present invention provides a plurality of PHY devices each having at least an internal register and an address decoder, individual control of a plurality of PHY devices and acquisition of status, and a plurality of PHY devices. In order to individually detect an interrupt signal and reset a desired PHY device among a plurality of PHY devices, a common address signal for a plurality of PHY devices, a chip select signal common to a plurality of PHY devices, a read / write signal, and a plurality of Reset signal, a signal for commonly activating output lines of a plurality of PHY devices, and a selection signal for individually selecting a plurality of PHY devices, and an interrupt signal from the plurality of PHY devices. Multiple PHYs to detect ATM device including a management interface provided between the device and the ATM layer device, a function of outputting an address signal to the ATM layer device, and a plurality of PHY devices based on signals from the ATM layer device. PH
The configuration has a function of identifying whether an interrupt signal is received from a Y device and a microprocessor including at least a function of controlling read / write of a plurality of PHY devices.

According to the present invention, control of a PHY device, acquisition of status information by register read / write, acquisition of P information between an ATM layer device and a plurality of PHY devices are performed.
Since it has a management interface for detecting an interrupt signal from the HY device and resetting the PHY device, it outputs a chip select signal to the PHY device generated by the address decoder or outputs a PHY device ID Then, by performing address decoding on the PHY device side, a plurality of PHY devices can be individually accessed.

[0012]

FIG. 1 is a block diagram showing a first embodiment of an ATM communication control apparatus according to the present invention. As shown in FIG. 1, this embodiment is a microprocessor 1
Are connected to the ATM layer device 2 via a bidirectional bus. In addition, a plurality of ATM devices 2 (here,
For example, three (3) PHY devices 3a to 3c are connected. ATM layer device 2 and PHY device 3
UTOPIA Level 2 interface 4 for transferring transmitted / received cell data is used as an interface with a to 3c.

The above configuration is the same as that of the conventional ATM communication control device.
Control of the PHY devices 3a to 3c by reading / writing the internal registers of the HY devices 3a to 3c, status of line failure, acquisition of detailed performance factors, individual P
Management for detecting interrupt signals from HY devices and resetting individual PHY devices
An interface 5 is included in the ATM layer device 2.

Note that UTOPIA Level 2 is
An interface capable of transferring cell data to a maximum of 31 PHY devices, which is specified by the ATM Forum. In FIG. 1, the management interface 5 is illustrated outside the ATM layer device 2 for convenience of illustration, but is included in the ATM layer device 2.

FIG. 2 is a circuit diagram of the ATM communication control device of FIG. 1 showing the management interface in detail. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. In the signal shown in FIG. 2, the signal with "B" is active low. The management interface 5 includes internal registers 8a to 8c of the PHY devices 3a to 3c.
8c to access PHY devices 3a-3c
"AD" indicating the address of the internal registers 8a to 8c
DR ", the value written to the internal registers 8a to 8c,
Alternatively, the read value “DATA” and each P generated by the address decoder 9 in the ATM layer device 2 are read.
The chip select signal “CS” to the HY devices 3a to 3c
0_B ”to“ CS30_B ”, PHY devices 3a to 3
"RW_B", P for reading / writing to c
A signal “OE_B” for activating the output lines of the HY devices 3a to 3c, interrupt signals “INT0_B” to “INT30_B” from the respective PHY devices 3a to 3c,
The reset signals “RST0_B” to “RST30_B” for the PHY devices 3a to 3c generated by the RST_B generation unit 10 in the ATM layer device 2 and the functions enabled by those signals.

In this embodiment, these signals are used to read / write the internal registers 8a to 8c of the PHY devices 3a to 3c for a maximum of 31 PHY devices connected to the ATM layer device 2.
Control of the devices 3a to 3c, or acquisition of the status of the line failure and the status of the detailed performance factor, and reset from the ATM layer device 2 to all the PHY devices 3a to 3c or reset to the individual PHY devices 3a to 3c Thus, interrupt signals from the plurality of PHY devices 3a to 3c can be detected, and the interrupt source PHY device can be recognized.

Next, the operation of this embodiment will be described with reference to timing charts for reading / writing registers from / to the PHY device 3a shown in FIGS. One PHY from ATM layer device 2
Device (here, PHY device 3a of # 0)
On the other hand, when reading / writing the internal register 8a of the PHY device 3a for controlling the PHY device or acquiring the status of the line fault or the detailed performance factor, the address decoder 9 in the ATM layer device 2 performs , Decodes the address from the microprocessor 1, and activates only the chip select signal “CS0_B” to the PHY device 3a to be accessed. Thereby, a plurality of PHY devices 3
It is possible to access one desired PHY device 3a among the devices a to 3c.

The operation during the write operation will be described with reference to FIG.
Is the read / write signal “RW_B” at time t1 in FIG.
Is activated (“L” at the time of writing), and the address signal “ADDR” and the write value “DATA” are driven. Subsequently, at time t2 in FIG. 3, the address decoder 9 in the ATM layer device 2 activates the chip select signal “CS0_B” for the PHY device 3a.

As a result, the PHY device 3a latches "ADDR" and "DATA" at the time t2,
Write to the built-in register 8a. Then ATM
The address decoder 9 in the layer device 2 makes the chip select signal “CS0_B” for the PHY device 3a inactive at time t3 in FIG. continue,
At time t4 in FIG. 3, the address signal “ADDR”, the write value “DATA”, and the read / write signal “RW_B”
Inactive.

Next, the operation at the time of a read operation will be described with reference to FIG. 4. The ATM layer device 2 reads the read / write signal "R" at time t11 in FIG.
W_B ”is activated (“ H ”at the time of reading) to drive the address signal“ ADDR. ”Subsequently, at time t12 in FIG. 4, the address decoder 9 in the ATM layer device 2 sends the chip select signal to the PHY device 3a. Activate “CS0_B”, thereby
The PHY device 3a latches the address signal “ADDR” at the time t12.

Next, at time t13 in FIG. 4, the ATM layer device 2 activates "OE_B" which is a signal for activating the output lines of the PHY devices 3a to 3c. The PHY device 3a drives the read data of the built-in register 8a when detecting the activation of the "OE_B". This read data is held until the signals “CS0_B” and “OE_B” are made inactive at time t14 in FIG.

Next, a PHY is sent from the ATM layer device 2.
The operation when resetting the devices 3a to 3c will be described. For an address A0 in the RST_B generation unit 10 in the ATM layer device 2,
The microprocessor 1 writes 31-bit data.

Each bit of the data corresponds to each reset signal “RST0_
B ”to“ RST30_B ”, and when“ 1 ”is written to the 31-bit data,“ RST0_B ”to“ R
A reset signal corresponding to a bit in which “1” is written in ST30_B ”is active (“ 30 ”) as shown in FIG.
L ").

Therefore, for example, when "1" is written to all the bits of the 31-bit data (when the 31-bit data of all 31 bits is "1" to the address A0 in the RST_B generating unit 10), the PHY device 3
The reset signals are simultaneously output to all the PHY devices including a to 3c, and 1 bit of 31-bit data is output.
When "1" is written only to the bit, the PHY device 3
a of the 31-bit data such that only the reset signal “RST0_B” for “a” becomes active.
The PHY device to be reset can be individually selected by selecting a bit for writing 1 ".

Next, an operation for an interrupt signal from the PHY devices 3a to 3c will be described. An INT_B detection unit provided in the ATM layer device 2 for detecting an interrupt signal includes a 31-bit INT_B register 11 of the address address A1 and the INT_B register 1
1 31-bit output signals are input in parallel, respectively.
And a one-input NAND circuit 12. The interrupt signals INT0_B to INT30_B input in parallel to the 31-bit INT_B register 11 have a maximum of 31 P
An interrupt signal corresponding to the HY device on a one-to-one basis.
An interrupt signal INT0 is sent from the PHY devices 3a to 3c.
_B to INT2_B can be input to the INT_B register 11, respectively.

In this case, there are three PHY devices 3a to 3c, and there are no remaining 28 connectable PHY devices.
3_B to INT30_B are always “H” and the corresponding IN
"1" is written in each of the 28 bits of the T_B register 11.

The NAND circuit 12 has an INT_B register 1
When all the 31-bit output signals of "1" are "H",
That is, when no interrupt signal is output from any of the PHY devices, an “L” level signal is output and INT is output.
One of the 31-bit output signals of the _B register 11 is "
When the signal is at "L", that is, when an interrupt signal is output from one or more PHY devices, the microprocessor 1 outputs a signal at "H" level.
When the signal input from the D circuit 12 is at the “H” level, it is determined that an interrupt signal is being output, and the INT_B register 11 at the address A1 is read to determine which PHY device the interrupt is from. Recognize.

The value of the INT_B register 11 is cleared by reading from the microprocessor 1. Then, the PHY device 3a of the interrupt source
By reading the internal registers 8a to 8c of .about.3c, it is possible to know what cause the interrupt signal. For example, when the INT_B register 11 at the address A1 is read and the value of the first bit is “0”, it is determined that the interrupt source PHY device is 3a, and the internal register 8a of the PHY device 3a is read. By doing so, it is possible to know what cause the interrupt signal.

Next, a second embodiment of the present invention will be described. FIG. 6 is a circuit diagram showing in detail the management interface of the second embodiment of the ATM communication control device according to the present invention. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 6, "ADDR" indicating the address of the internal registers 16a-16c of the PHY devices 3a-3c is provided in the management interface to access the internal registers 16a-16c of the PHY devices 3a-3c. "DAT" which is a write value or a read value to the internal registers 8a to 8c.
“A”, “ID” which is a 5-bit width selection signal for identifying 31 PHY devices, and PHY devices 3 a to 3
3c, the chip select signal “CS_B”, PH
"RW_B" which is a signal for reading / writing the Y devices 3a to 3c, "OE_B" which is a signal for activating the output lines of the PHY devices 3a to 3c, P
“INT0_B” to “INT30_B”, which are interrupt request signals from the HY devices 3a to 3c, and “RST0_,” which is a reset signal for the PHY devices 3a to 3c.
B "to" RST30_B ".

The PHY devices 3a to 3c are connected to the "I
Address decoders 16a to 16c for identifying D "
Having. Note that ID = 0 is the first (# 0) PHY device 3a, ID = 1 is the second (# 1) PHY device 3b, and ID = 2 is the third (# 2) PHY device 3
c, and similarly, ID = 30 is the 31st (#
30) PHY device (not shown). Note that up to 31 PHY devices can be connected to the ATM layer device 2, but it is assumed here that three PHY devices 3a to 3c are connected.

In this embodiment, these signals are used to control the PHY devices 3a to 3c by reading / writing the internal registers 8a to 8c of the PHY devices 3a to 3c connected to the ATM layer device 2, or Acquisition of the status of the line failure and the status of the detailed performance factor, resetting of all the PHY devices 3a to 3c from the ATM layer device 2, resetting of the individual PHY devices 3a to 3c, and resetting of the plurality of PHY devices 3a to 3c. The interrupt signal can be detected, and the interrupt source PHY device can be recognized.

Next, the operation of this embodiment will be described with reference to the timing chart of register read / write for the PHY device 3a in FIGS. 7 and 8. Any one PH from ATM layer device 2
When reading / writing the internal register of the Y device (here, 3a is described as an example) to control the PHY device or to obtain the status of the line failure and the status of the detailed performance factor, A
The TM layer device 2 outputs an ID (here, ID = 0) corresponding to the PHY device 3a.

Each of the PHY devices 3a to 3c has 5
The above-mentioned ID input via the bit-width bus is decoded by the built-in address decoders 16a to 16c, respectively, and a response is made only when the decoded value matches the own ID. Here, the address decoder 16
a to 16c, the response output is taken out only from the address decoder 16a.
3c can be accessed only for one arbitrary PHY device 3a.

Next, the operation at the time of the write operation will be described with reference to FIG. 7. The ATM layer device 2 reads the read / write signal "RW" at time t21 in FIG.
_B ”is activated (at the time of writing = 0), and“ ADD
R "," DATA ", and" ID ", respectively.
At 22, the chip select signal “CS_B” of the PHY devices 3a to 3c is activated.

Thus, the PHY devices 3a to 3c
Converts the “ID” at the time t22 into the address decoder 16.
a to 16c, and the value obtained by the decoding coincides with its own ID only in the address decoder 16a. Therefore, only the PHY device 3a having the address decoder 16a writes the input address signal "ADDR" and The value “DATA” is latched and written to the internal register 8a.

Thereafter, the ATM layer device 2
At time t23, the chip select signal “CS_B” is made inactive, and at time t24, “ADDR”, “DAT”
A, “ID”, and “RW_B”, respectively, and thus the ATM layer device 2
Data can be written only to any one of the PHY devices 3a to 3c.

Next, the operation at the time of the read operation will be described with reference to FIG. 8. The ATM layer device 2 activates the read / write signal "RW_B" at time t31 in FIG. Then, the address signal “ADDR” and the bus “ID” are driven. Subsequently, the ATM layer device 2 operates at time t in FIG.
32, the PHY device chip select signal “CS_
B "is activated.

Thus, the PHY devices 3a to 3c
Converts the “ID” at the time t32 into the address decoder 16.
a to 16c, and the decoded value matches the own ID only in the address decoder 16a. Therefore, only the PHY device 3a having the address decoder 16a latches the input address signal "ADDR". I do.

Next, the ATM layer device 2 activates "OE_B" which is a signal for activating the output lines of the PHY devices 3a to 3c at time t33 in FIG. When detecting the activation of the signal “OE_B” at the time t33, the PHY device 3a drives the read data from the address “ADDR” latched in the internal register 8a. This read data is shown in FIG.
At time t34, “CS0_B” and “OE_B” are held until inactive.

Operation when resetting the PHY devices 3a to 3c from the ATM layer device 2,
The operation with respect to the interrupt signal from the PHY devices 3a to 3c to the ATM layer device 2 is the same as that of the first embodiment, and the description is omitted.

As described above, in the second embodiment, in addition to the effects of the first embodiment, 31 “CS_
When the “B” signal becomes “ID” having a 5-bit width, the first
There is an effect that the number of wirings is reduced as compared with the embodiment.

[0043]

As described above, according to the present invention,
There is a management interface between the ATM layer device and a plurality of PHY devices for controlling the PHY device by register read / write, acquiring status information, detecting an interrupt signal from the PHY device, and resetting the PHY device. Therefore, an external circuit for decoding addresses for accessing a plurality of PHY devices from the microprocessor can be eliminated, and the P generated by the address decoder can be eliminated.
By outputting a chip select signal to the HY device or outputting a PHY device ID and performing address decoding on the PHY device side, a plurality of PHY devices can be individually accessed and reset individually.

Further, according to the present invention, the ATM layer device has an interrupt signal detecting section having a register for holding interrupt signals from a plurality of PHY devices at bit positions allocated in advance for each PHY device. And multiple Ps via the management interface
Since an interrupt signal from the HY device is input to the ATM layer device, interrupt signals from a plurality of PHY devices can be individually detected.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of the first embodiment of the present invention.

FIG. 3 is a timing chart at the time of a write operation in the first embodiment of FIG. 2;

FIG. 4 is a timing chart at the time of a read operation in the first embodiment of FIG. 2;

FIG. 5 is a diagram of a reset signal for a PHY device according to the first embodiment of FIG. 2;

FIG. 6 is a circuit diagram of a second embodiment of the present invention.

FIG. 7 is a timing chart at the time of a write operation in the second embodiment of FIG. 6;

FIG. 8 is a timing chart at the time of a read operation in the second embodiment of FIG. 6;

FIG. 9 is a block diagram of an example of the related art.

[Explanation of symbols]

 Reference Signs List 1 microprocessor 2 ATM layer device 3a to 3c PHY device 4 UTOPIA Level 2 interface 5 management interface 8a to 8c internal register 9, 16a to 16c address decoder 10 RST_B generation unit 11 31-bit INT_B register 12 NAND circuit 16a ~ 16c Address decoder

Claims (6)

[Claims] 1. A plurality of PHY devices each having at least an internal register; individual control and status acquisition of the plurality of PHY devices; individual detection of interrupt signals from the plurality of PHY devices; Desired PHY
Decoding the address input from the microprocessor to perform a reset on the device, and a common address signal for the plurality of PHY devices;
Outputting individual chip select signals for the plurality of PHY devices, outputting read / write signals, individual reset signals to the plurality of PHY devices, and signals for activating output lines of the plurality of PHY devices, respectively; An ATM layer device including a management interface provided between the plurality of PHY devices and the ATM layer device, for detecting an interrupt signal from the plurality of PHY devices; and outputting an address signal to the ATM layer device. A function of identifying which of the plurality of PHY devices the interrupt signal is based on a signal from the ATM layer device, and a function of controlling read / write of the plurality of PHY devices. At least including my An ATM communication control device comprising a microprocessor. 2. The management interface according to claim 1, wherein: during a write operation based on an active write signal output from said ATM layer device, a desired one of said plurality of PHY devices is accessed based on an address signal from said address decoder. PHY
After activating only the chip select signal for the device, the address signal and data from the ATM layer device are latched in the desired one PHY device, and written into the internal register of the desired one PHY device, At the time of a read operation by an active read signal output from the ATM layer device, only the chip select signal for a desired one of the plurality of PHY devices to be accessed is activated based on an address signal from the address decoder. After the address signal from the ATM layer device is latched by the desired one PHY device, the desired signal is output after the signal for activating the output line of the desired one PHY device is output from the ATM layer device. ATM communication control device according to claim 1, characterized in that read data corresponding to the address signal of the internal registers of one PHY device. 3. A plurality of PHY devices each having at least an internal register and an address decoder, individual control and status acquisition of the plurality of PHY devices, individual detection of interrupt signals from the plurality of PHY devices, and the plurality of PHY devices. The desired PHY of the device
To perform a reset on the device, the plurality of Ps
A common address signal for the HY device; a chip select signal common to the plurality of PHY devices;
Outputting a write signal and an individual reset signal for the plurality of PHY devices, a signal for commonly activating output lines of the plurality of PHY devices, and a selection signal for individually selecting the plurality of PHY devices, An ATM layer device including a management interface provided between the plurality of PHY devices and the ATM layer device for detecting an interrupt signal from the plurality of PHY devices; and a function of outputting an address signal to the ATM layer device A function of identifying which of the plurality of PHY devices the interrupt signal is based on a signal from the ATM layer device, and a function of controlling read / write of the plurality of PHY devices. Including microprocessor and An ATM communication control device comprising: 4. The management interface according to claim 1, wherein at the time of a write operation by an active write signal output from said ATM layer device, said management interface is configured to output said A based on an address signal from said microprocessor.
The plurality of PHYs extracted from a TM layer device
After driving a bus of the selection signal specifying one desired PHY device to be accessed among the devices and activating the chip select signal, the selection signals are respectively decoded by address decoders in the plurality of PHY devices. The address signal and data from the ATM layer device are latched only by the desired one PHY device which matches the value of the ATM layer and the ID of the ATM layer device, and the internal layer register of the desired one PHY device is written. At the time of a read operation by an active read signal output from the device, the ATM layer device accesses a desired one of the plurality of PHY devices based on a chip select signal and a selection signal from the ATM layer device. Address of After the latch signal, the ATM
The data corresponding to the address signal in an internal register of the desired PHY device is output after a signal for activating the output line of the desired PHY device is output from the layer device. Item 4. The ATM communication control device according to item 3. 5. The ATM layer device has a bit number corresponding to a maximum number of PHY devices connectable to the ATM layer device via the management interface, and a bit previously allocated to the PHY device. A reset signal generating unit for writing data having a predetermined value from the microprocessor when the PHY device is reset, the reset signal generating unit corresponding to a bit whose written data is the predetermined value; 4. A according to claim 1, wherein a reset signal is output only to the PHY device.
TM communication control device. 6. The ATM layer device, comprising: a register in which interrupt signals of a predetermined value output from the plurality of PHY devices are respectively input to bit positions allocated in advance; and a register of at least one bit of the register. An interrupt signal detection unit including a gate circuit that outputs an interrupt detection signal when the output signal has the predetermined value; the microprocessor reads a register of the interrupt signal detection unit when the interrupt detection signal is input; 4. The ATM communication control device according to claim 1, wherein the ATM communication control device recognizes an interrupt from which PHY device.