JPH02214958A - Device combined with processor for extending port of said processor - Google Patents

Abstract

PURPOSE: To couple an external memory to a micro controller without reducing the number of I/O ports of the controller by transferring data between the micro controller and an EPROM of a port expander or between the micro controller and an external device passing the port expander. CONSTITUTION: A port expander 20 is coupled to ports 0 and 2 of a micro controller 12a through busses 13a and 14a, and a control signal is connected between the micro controller 123 and the port expander 20 through a control line 15a. When the EPROM 21 or ports B and A are selected so as to be operated by busses 13a and 14a, ports 0 and 2 of the micro controller 12a can access the external memory in a mode of the EPROM 21 or acces an I/O device through ports B and A. Thus, the external memory restores ports lost at the time of coupling to the same ports of the micro controller.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the field of memory devices 1, and in particular to external memories constituted by microcontrollers.

[Conventional technology]

In the semiconductor memory field, the design and manufacture of erasable programmable read only memories (EPROMs) is well known. These EPROM devices are formed on semiconductor chips and are typically configured as standardized capacity memories, such as 32K or 64K. These memory chips are typically placed in standard packages. Semiconductor memory devices, such as gPROMs, are coupled for operation with other semiconductor devices. In most cases, the EPROM is coupled to a processor that controls the transfer of data between the EPROM and the memory device.

In the basic configuration, a memory location in a gPROM is accessed by a processor when the processor generates an address signal on an address line coupled to the memory. Depending on control signals provided by the processor, data is written or programmed to or read from the memory. Data transfer is accomplished by placing appropriate information on a data bus coupled to the memory. If the EPROM is not part of a larger structure such as a programmable logic array device, the E
FROM does not contain any processing circuitry other than the circuitry necessary to perform addressing and data transfer.

One group of processors used to work with gPROMs is known as a microcontroller. Microcontrollers are specialized processors used to serve special applications, including custom applications. These controllers include all necessary for operation and may typically include a processor, logic circuits, timing circuits, control circuits, buffers, latches, and on-chip memory. In most cases, specific application software is embedded in the controller chip. These controllers have inputs/outputs (I) for exchanging information.
/O) Also includes ports.

However, when external memory, such as the EFROM described above, is coupled to a given controller, it is always coupled to one or more ports of the controller.

That is, if a given microcontroller requires off-chip memory for a given function of the controller, the off-chip memory is coupled to one or more ports of the controller. Those ports are lost to use Ilo. Without separate off-chip circuitry, coupling external memory to the microcontroller imposes severe constraints on its I/O performance. The reason is that the external memory monopolizes one or more ports of the microcontroller.

[Problem to be solved by the invention]

What is needed is a technique for coupling external memory to a microcontroller without reducing the number of I/O ports on the controller.

[Means to solve the problem]

The present invention provides external memory to be coupled to the microcontroller, but also includes a photo-expander to bring back into use those ports that are no longer in use due to the coupling of the port expander to the microcontroller. This is what we provide. In short, the photoextender increases the total number of ports from the microcontroller and also couples external memory to the microcontroller. The port expander of the present invention is manufactured in a single semiconductor device and requires the use of a special adhesive circuit.

The port expander of the preferred embodiment is coupled to two ports of the microcontroller. Each port is an 8-bit port. A 16-bit address signal and an 8-bit data signal are multiplexed on a bus that couples the port expander to the two ports of the microcontroller. Port expander is 32 pi)
It includes an EPROM, non-volatile configuration registers, and special function register/port controllers that provide the microcontroller with external memory and port expansion capabilities. The port expander's EPROM provides external memory to the microcontroller. However, data transfer between the I/O device and the occupied port occurs through the expansion port of the port expander.

The port expander essentially acts as a data transfer point between the I/O device and the microcontroller. Therefore, data transfer can be performed between the microcontroller and the gPROM 0 of the photoextender or between the microcontroller and an external device via the port expander. The configuration registers constitute a programmable register set for directing and addressing pliEPROM t or special function registers by the microcontroller. The port expander of the present invention also includes special test activation circuitry that prevents accidental entry into test mode. To enter test mode, a valid test mode code must be written to one of the port latches coupled to the microcontroller. As a second condition, a valid test mode enable code must be written to the other port latches coupled to the microcontroller.

Next, the read signal, whose voltage is approximately 12 volts, must be sustained for a sufficiently long time. If all three conditions are met, the port expander enters its test mode. The duration of the read signal is measured by a pulse width detector to ensure that short pulses such as glitches and noise pulses do not unintentionally activate the test mode. Having three requirements that must be met provides sufficient security to prevent unintentional entry into test mode.

In the following description, a device that performs port expansion and provides memory outside the chip will be described. In the following description, numerous details are set forth, such as specific memory capacities, signal lines, etc., in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the invention may be practiced without these specific details. In other instances, peripheral structures and processes are not described in detail in order not to obscure the invention in unnecessary detail.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

Referring now to FIG. 1, a conventional technique for coupling external memory to a microcontroller is shown. Microcontroller 1
EPROM 11 is shown as external memory coupled to 2. Microcontroller 12 communicates with external devices via multiple ports. The particular example shown in FIG. 1 shows a microcontroller 12 having four ports 0-3. A specific example is shown in Figure 1, where the input/power (
Various types of microcontrollers having I/O ports are well known in the art. A specific example of a conventional microcontroller is
Intel Corporation located in Santa C1ara
) 8051 and 8096 are manufactured by Nyoshi.

Includes devices related to the goiss microcontroller family.

In the example shown in FIG. 1, two of the ports of microcontroller 12, ports 1-0 and 2, are connected to bus 13.
14 to the external memory EPROM 11. Bus 13.14 is a bidirectional bus, EPItOMll
and the bidirectional port (0.2) of the microcontroller 12. Various conventional techniques are known for coupling address and data signals to buses 13 and 14. Furthermore, a given bus 13 or 14 carries address information from the microcontroller 12 to EPRO.
If used only to couple to M 11, these buses need not be bidirectional buses. Also,
A control line 15 is connected between the microcontroller 12 and the F and PROM 11 for transmitting control signals.

In typical operation, microcontroller 12 generates address signals. Their address signals are EPRO
It is coupled to EPROM 11 via at least one of buses 13 and 14 for accessing the address locations of M11. Data is then written to EPROM 11 via at least one of buses 13 and 14, or
Read from M11. It should be appreciated that the address and data signals can be multiplexed so that they can be combined onto a given bus.

To use external memory like EPROM 11,
In the example shown in FIG. 1, it is necessary to dedicate two ports. The microcontroller 12 has its I
Only ports 1 and 3 are left for /O communication. Ilo
Buses 16 and 17 are coupled to ports 1 and 3, respectively, for data transfer. As shown in FIG.
With one port, the microcontroller 12 can only utilize the other two ports 1 and 3. I using a specialized "glue" circuit to restore ports O and 2
It is necessary to make the necessary connections of lo and EPROM 11 to ports O and 2.

Reference is now made to FIG. 2, in which a port expander 20 of the present invention is shown coupled to a four-port microcontroller 12a, which is equivalent to microcontroller 12 of FIG. Port expander 20 includes EPROM 21 . This EPROM
21 is equivalent to EPROM 11 shown in FIG.

Port expander 20 is coupled to ports 0 and 2 of microcontroller 12a via buses 13a, 14a. Control signals are coupled between microcontroller 12a and port expander 20 via control line 15a. Ports 1 and 3 are bus 16
a.

17a, respectively, to various I/O devices. In order to indicate in other figures the same parts as shown in FIG. 1, the reference numbers denoting the parts shown in FIG. I'll decide.

Address and data information is provided from ports O and 2 of microcontroller 12a, and EPROM 21 is accessed as described with reference to FIG. EPRO
In addition to M 21, port expander 20 includes ports A and B. The purpose of having ports A and B is to restore the use of ports 0 and 2 for Ilo when external memory 21 is coupled to ports O and 2. To do this, port expander 20 of the present invention receives signals from ports O and 2 and selects the destination of those signals.

Port 0.2 of microcontroller 12a and EPROM 21
When transferring data between external memories in the form of
Port expander 20 causes signals to be sent to and from EPROM 21 via buses 13a, 14a. However, assuming ports 0 and 2 are used for Ilo, the signals are coupled to ports A and B of port expander 20 via buses 13a and 14a. Buses 18,19 coupled to ports A and B, respectively, allow data transfer between I/O devices and bauds A and H. EP to work on buses 13a, 14a
By selecting ports 0 and 8 of the microcontroller 12a, the ports 0 and 2 of the microcontroller 12a are
21 modes of external memory, or can access I/O devices via baud) B and A. Thus, the port expander of the present invention recovers ports lost when external memory is coupled to those same ports of the microcontroller.

Reference is now made to FIG. 3, in which the port expander 20 of the present invention is shown in detail. Port 2 of microcontroller 12a is coupled to address buffer 25 of port expander 20 via bus 14m. The address buffer 25 is coupled to an address latch 27. Microcontroller 12a
port O of is coupled via bus 13a to address buffer 26 of port expander 20, which address buffer 26 is coupled to address latch 28. The output terminals of address latches 27 and 28 are coupled to special function register/photo control (SFR, /PC) unit 31.

Although a variety of techniques can be used to accomplish addressing and data transfer, the preferred embodiment of the present invention utilizes the following techniques that are primarily suited to the microcontrollers described above.

During the first period, address bits AQ-7 from microcontroller 12a are provided on bus 13a and address bits A8-15 are provided on bus 14a. Sixteen address bits are then provided to the address latches 27,28 for output from those latches. During the second period, data bits DQ~7 are provided via bus 13a and I/O buffer 32 to internal bidirectional data bus 39. The data bus 39 is connected to the data bus multiplexer 3.
Combined into 3. This data bus multiplexer is E'
FROM 21, configuration register 30 or S FR/
Select the PC 31, connect it to the bus 39, and perform data transfer. The output terminal of address latch 2T is EPROM21
In addition, it is also coupled to main control circuit 36 . To address signal 8~. 5 is compared with pre-programmed bits in configuration register 30 and EPROM 21
, the configuration register 3°, and the SFR/PC 31 to be accessed. In the preferred embodiment, the upper five bits are used, but the number of bits used is a matter of design choice. In addition, the microcontroller 12a
A control signal from the main control circuit 36 is also applied to the main control circuit 36 via line 15a. The main control circuit 36 sends control signals to v, x,
Rack f27.28, I/O buffer 32, and EPRO
M21, configuration register 30, SFvPc31,
multiplexer 33 and port buffers 34.35. Pot buffers 34 and 35 are coupled to boards A and B, respectively. Port buffer 734.35 is SF
R/PC31 and port A.

It is also bi-directionally coupled to 8FR/PC31 for transferring data between B and B. Port buffers 34-35 are also coupled to bidirectional bus 19.18. I/O buffer 32 and port buffers 34, 35 to hold signals
Other well-known circuits, such as latches coupled to the latches, are not shown.

Although a variety of control signals may be used, a representative example of the control signals used by the port expander 20 of the preferred embodiment is shown in FIG. Chip enable signal CE/(symbol/
(will be used to indicate a low activated state)
enables the master when asserted. If the signal CE/ is not asserted, the port expander 21 is in a standby state and cannot be accessed for a long time. However, the port retains its current activated state. S F R/P C unit 3
RD/ is used to indicate the state of reading from 1.

(WR/CPGM/) is used to write to, or program, the port expander 21. The ALE signal is used to allow the address to flow through the latches 27,28. VPP (R8T) is
Program supply voltage during programming and reset during other modes. The program storage enable signal PSEN/ is used to indicate the status of a read from the configuration register 30 of the EPROM 21 , and that signal is used under certain conditions in conjunction with the RD/ signal to cause the port expander 21 to perform a read operation. Have them do it.

Next, the operation will be explained. Port expander 20 allows three memory planes to be accessed by 16-bit address signals from microcontroller 12a.

Port expander 20 is mapped to the appropriate unit 21.
To select 304 or 31, memory mapping is actually performed by the microcontroller 12a. The three memory planes correspond to EPROM 21, configuration register 30, and SFR/PC unit 31. The three planes that are mapped are shown in FIG. Those three memory planes are EPROM plane 40, SFR/
Each is configured by a RAM plane 41 and a configuration plane 42.

When SFR/RAM plane is selected, SFR/PC
The instruction of device 31 can occupy two byte planes within the plane. In a preferred embodiment, SFR/P
Only 5 bytes are actually used for C machine instructions.

The unused portion can be used for RAM. Other address locations are available for accessing RAM located within or external to the microcontroller 12a. In FIG. 4 address locations are shown in hexadecimal notation.

Additionally, an identifier is used at plain address 0000 to provide information about the port expander 20, such as manufacturer name, product model, etc.

Configuration plane 42 is inaccessible in normal operating modes. EPROM plane 40 and SFR/RAM
Only plane 41 can be accessed.

However, during programming/verification mode, EPROM plane 40 and configuration plane 42 are accessible. The preferred embodiment EPROM 21 is a 32K x 8 byte device. Since a 16 pit address can access 64 bytes, the 32 bytes of the preferred embodiment can be mapped to various locations on EPROM plane 40. One of the configuration registers 30, shown as a non-volatile register, provides the starting address for mapping EPROM 21 within plane 40. Default location is EPROM plane 4
It is shown in the lower half of 0, indicated by address 0000-7 FET. EPROM plane 4
0 can map two 32 bytes FJPROM.

In the preferred embodiment, a special function register (8FR)
is provided at the byte location 2 of the SFR/RAM plane 41. The default location is the top two byte locations of the SFR/RAM plane. Another configuration register 30 determines the location of the two byte SFR blocks. port expander 2
0 ports) A and B are accessed by reading or writing to the SFR. SFR/PC device 31 is connected to port A.

The transfer of information between B and B is controlled according to SFH.

First, the port expander 20 of the present invention is connected to the microcontroller 1.
2a, configuration register 3° is programmed to configure the operation of port expander 20. In this embodiment, three non-volatile registers make up configuration register 30.

The first register contains byte EPR 32 in brane 40.
Used to map OM21. The default location is at address location oooo. In this embodiment, this first register combines the EPROM plane and SFR by internally combining the PSgN/signal and RD/signal.
Also used to combine /RAM branes. The second configuration register is also used to provide base addresses for special function registers. As mentioned earlier, this embodiment uses byte boundaries at two so that any two of the SFR/RAM branes 41 can have SFRs at byte boundaries. Default old address is F800
It is in. A third configuration register is used to configure each baud (A and B) for a level of I/O performance compatible with Transistor-Transistor Logic (TTL) or Complementary Metal-Oxide-Semiconductor (0MO8). It will be done. Additionally, this third register also allows supplementing the polarity of R8T to perform a programmable bit.

Once the configuration registers are programmed, the addresses for accessing EPROM 21 and special function registers 31 are programmed. If microcontroller 12a wishes to access the EPROM, microcontroller 1
The address signal from 2a must match the mapped address. For example, if the EPROM is in its default location, 0000-7FFF
address can access gPROM 21. Alternatively, if at least one of A and B performs data transfer, the microcontroller 12a is connected to the SFR/RA
An address corresponding to SFH in M-brane 41 is supplied. If the SFR is in the SFR/RAM plane 41, it exists between F2O3 and FFFF. Data transfer between microcontroller 12a and at least one of ports A and B is performed by accessing SFR locations and storing data in the SFR. The port is bidirectional and can be read and written.

Other address locations in SFR/RAM plane 41 are used to address RAM locations in microcontroller 12a or other memory mapped devices. Therefore, the port expander 20 of the present invention can provide external EPROM memory to the associated microcontroller, while at the same time special function registers transfer data between the microcontroller and the two expanded bauds A and B. It can be so.

A configuration program 30 is programmed to allow special function registers and BPROM 21 to be mapped to various locations. This programmed mapping technique allows υ, gP
Flexibility in addressing the ROM 21 and expanded port A2Be can be increased.

Although one mapping technique has been described in this preferred embodiment, gPROM 21 and SFR/PC device 31
It should be understood that mapping techniques for each leakage can be used to improve the performance of the equipment. For example, overlay techniques can be used so that SFR registers can be mapped onto unused portions of the EPROM plane, or EPROM and SFR registers can be placed on top of each other. Furthermore, in a 4-port microcontroller device shown in FIG.
operates on the second port expander to extend ports O and 2 L
, E: connects the second port expander to buses 13a and 14 to form a byte through 64 of FROM.
It should be understood that it can be combined with a. In that case, KM2 (7) EPRO is accessed by the address signal between address 8000 and FFFF0 in Figure 4.
The two mapping techniques can be combined to map M.

By using a 32-byte EPROM, two such iROMs can be accessed with 16-bit address sync technology.

It should be understood that the various mapping techniques described above are for illustrative purposes only and are not intended to limit the invention. Various other techniques can be easily implemented without departing from the spirit of the invention.

Furthermore, other units can be easily used in place of existing devices, such as using a static RAM in place of EPROM 21, without departing from the spirit of the invention. In addition, preferred embodiments have been described in which the gPROM capacity and the number of bits of address lines and data lines are set to specific values; however, these examples are for illustrative purposes only, and the actual values are a design choice. This is a problem.

Test mode enablement Test mode is a non-user mode that is generally used to apply stress to components or to determine margins of components. Since test mode is used strictly to test manufactured parts, care should be taken that the user of the part does not place the part in the test moto. Use of a part in a test moto, whether intended or not, may cause damage to equipment associated with the part. Some test mode enablement techniques utilize high voltage detectors to place parts into specific test modes. In some cases, noisy conditions may cause the device to be placed in test mode, thereby damaging itself or associated equipment, causing it to read inaccurate information, or causing it to read inaccurate information. Sometimes they are forced to write.

To prevent unintentional entry into test mode, the port expander 20 of the present invention utilizes special circuitry to prevent this. Special test activation circuitry is provided in port expander 20 to generate a test mode enable signal to enable test mode. Reference is now made to FIG. Two photo latches 51 and 52 are I/O buffers 32
are combined to receive the output of An output terminal of latch 52 is coupled to test mode enable circuit 55, and latch 51
The output terminals of are coupled to various circuits that require a test mode code to perform a particular test. Read signal RD/ is coupled as an input to high voltage detector circuit 53. High voltage detector circuit 53 detects the presence of high voltage necessary to enter test mode. A high voltage detection signal is applied to filter 54, and a signal subjected to JJF waveforming by the filter is applied to test mode enabling circuit 55. In operation, the port expander 20 of the preferred embodiment has its test module
-Three conditions must exist before entering the mode. The first condition is that the proper test mode (TM) code must be written to latch 51 to perform a particular test. The second condition is that test mode is possible.
E) The code must be written to another latch 52.

The inputs to the port latches 51, 52 are connected to buses 14a, 13a by a microcontroller or other signal generator (for testing).
Supplied via. In the preferred force example, latches 51 and 52 are driven by the latches for bows A and B, respectively. However, it should be understood that launches 51 and 52 are not limited to use with port latches.

The circuit 55 is preprogrammed so that the test mode enable path 55 is activated only when the appropriate TME code is provided by the latch 52.

The third condition is that a high voltage must be supplied to the high voltage detector circuit 53. A high voltage is present when the RD/signal goes to a high voltage state, such as a voltage higher than the power supply voltage CC. In the preferred embodiment, 12V DC is used. When the RD/ signal is 12 volts, the RD/ signal causes the high voltage detector circuit 53 to generate a detection signal. The detection signal is coupled through filter 54 to test mode enable circuit 55. Whenever a high voltage detection signal is applied to the test mode enable circuit 55 and the appropriate TM code is present, the test mode enable circuit generates a test mode enable signal to enable the test mode.

Filter circuit 54 includes a pulse width detector 56 made up of a series of series coupled inverters (only two inverters 57,58 are shown in FIG. 5) and a Nandt gate 59. The input terminal of the Nant gate 59 is the input terminal of the first inverter 5, and the output terminal of the Nant gate 59 is the output terminal of the last inverter 58. To prevent unintentional high voltage from being generated,
Norx width detector 56 operates to eliminate short pulses such as glitches. In other words, the signal RD/ becomes higher than the power supply voltage vCC due to voltage leakage,
When the power supply voltage CC becomes low and a high voltage detection signal is generated from the high voltage detection circuit 53, the pulse width detector 56 that is present so as not to pass a pulse narrower than a predetermined pulse width causes The high voltage detection signal cannot be coupled through filter 54. The minimum pulse width that can pass through pulse width detector 56 is determined by the delay in the series inverter string. The pulse width of the signal that can pass through the pulse width detector 56 is wide enough so that, after undergoing the delay of the inverter string represented by inverters 57 and 58, the pulse is still present at the input terminal of the inverter 5T. Must.

Therefore, three conditions must exist in order to enter test mode to perform a correct test. That is, port expander 20 receives a valid test mode code to perform a particular test, receives a valid test mode enable code that matches a preprogrammed code, and receives a 12V read signal. That is to have for a long time. Only when those three conditions exist can this port expander perform a correct test. In another embodiment, test mode enabling circuit 55
The TM code can be held in latch 51 using the test mode enable signal from . That is, latch 5
1 cannot receive the 7M code until the test mode enable signal is generated.

Although the test mode enabling technique of the present invention has been described in terms of a port expander, it can easily be implemented in other devices such as nuclear technology. For example, memory such as EPROM or static RAM can be It can be put into test mode by requiring its latches to engage, and then a control signal, such as a read signal, can be transitioned to a predetermined level for a sufficient period of time. Only when conditions are met will the port expander perform the desired test.Furthermore, other devices can be used in place of the latch to implement the "enable hold" technique of the present invention.

What has been described above is a port expander that has internal memory and special protection circuitry that prevents unintentional entry into test mode. Providing external memory to the associated device couples the port expander to operate with the associated processor or device, but also restores the use of ports lost by coupling to the external memory. No separate adhesive circuit is required. Although the port expander of the present invention is manufactured on a single semiconductor chip, doing so is not critical to the practice of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram illustrating how two ports are lost when external memory is coupled to the microcontroller; FIG. A schematic diagram illustrating how a port that is lost when coupled to two ports is made available again; FIG. 3 is a block diagram showing the port expander of the present invention; FIG. 4 is a block diagram showing the port expander of the present invention; FIG. 5 is a block diagram illustrating activation of the test mode of the port expander of the present invention. 20/111 port expander, 25.26---φ address buffer, 27.28---address latch, 3
0.Φe-configuration register, 31.--Special function register and port controller, 32..-I/O buffer,
34, 35...Photobuffer, 36...Main control circuit, 51°52-...Port latch, 53...
High voltage detector 54**s conflict filter, 55...-E
test mode enabling circuit, 56...pulse width detector;

Claims (3)

[Claims] (1) a first port coupled to a port of a processor for transferring information to and from the processor; a memory coupled to the first port for providing external memory to the processor; and a first port coupled to the memory. a second port coupled to the first port and the second port to provide an open port when the port of the processor is occupied; a configuration register coupled to the first port and configuring a mapping address for accessing the memory and the function register; The external memory is characterized in that when an address is provided, the processor accesses the memory, and when a first predetermined address is provided, the processor accesses the second port for data transfer. An apparatus coupled to a processor for expanding a port of the processor when coupled to the first port of the processor. (2) a port expander coupled to the processor for providing an open port to the processor when the processor port is occupied by having a processor port coupled to external memory; a first port for transferring information to and from the processor; an address bus coupled to the first port; and a memory coupled to the address bus for supplying the external memory to the processor; an input/output (I/O) port for providing an open port to the processor; and a data bus coupled to the first port, the memory, and the I/O port for transferring data. , the data bus addresses the memory for data transfer between the processor and the memory, and the processor addresses the I/O port for data transfer between the processor and the I/O port. A port extender coupled to a processor characterized in that it has access to a processor. (3) a port expander coupled to a processor for providing at least one open port to the processor when the processor port is occupied by having a processor port coupled to external memory; a first port coupled to a support for transferring information to and from the processor; a second port coupled to a second processor support for transferring information to and from the processor; an address bus coupled to a port of the processor; a data bus coupled to the second port; a memory coupled to the address bus and the data bus to supply the external memory to the processor; /output (I/O) port, a second I/O port, the address bus, the data bus, and the first I/O port.
a /O port; and a function register coupled to the second I/O port to transfer information between the I/O port and the data bus; addressing the memory for data transfer between the processor and the I/O port, the processor accessing the I/O port for data transfer between the processor and the I/O port; port expander.