JPS6086642A - Setting system of memory control information - Google Patents

Abstract

PURPOSE:To perform check beforehand to set memory control information accurately by storing control information of a memory unit of every memory card in an ROM preliminarily and managing this control information with a CPU. CONSTITUTION:Before initialization, a card number 2 of a memory card 2 is set to a card address information register 28. A CPU1 sends the card number 2 and transmits it to a comparing circuit 27 through an address bus 100 for the purpose of reading out required control information from an ROM24 of the card 2, and coincidence is attained, and therefore, control information are read out successively from the ROM24 by the following transmitted address. A parity bit is added to control information, and the parity bit is checked by a checking part 11 of the CPU1, and it is checked whether the capacity of memory units 20 and 21 is between preliminarily entered maximum and minimum values of memory units or not. Thus, the normalcy is confirmed.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a memory control information setting method, and in particular, when the memory is configured with a plurality of memory cards having memory units of arbitrary capacity, each memory -Relates to a memory control information setting method that enables accurate setting of memory control information in a card.

[Prior art and problems]

When constructing a large-sized memory, it is often constructed from a plurality of memory units rather than from a single memory chip.

For example, as shown in Figure 1, 16-byte memory units U1 and U2 are constructed using eight 16K x 1-bit memory chips, and 32-byte memory units U1 and U2 are constructed using eight 32K x 1-bit memory chips. bytes of memory
The unit U3 is used to configure a memory with a capacity of 64 KB or more. At this time, memory units U1 and Ul are installed in the memory card C1, and memory units U3, . . . are installed in the memory card C2. Therefore, when accessing memory with a certain address, it is necessary to identify in which memory unit that address exists.

For this reason, in the past, the memory unit capacity value was set for each memory card using a switch, etc.
Address assignment information for each memory unit was generated by adding these values using an adder or the like provided for each memory card.

In addition, memory requires read/write timing information and strobe timing information in order to operate accurately. Moreover, in dynamic RAM, due to the limited number of pins, the row address and column address are sent out twice, for example, 8 bits each, and control information indicating which address information is present and the strobe timing is required.

And high-speed dynamic RAM-C? Well, this is it.
The timing relationship of each of these control information is determined within a + level range, and it is necessary to perform various controls based on these control information.

However, conventionally, this control information has also been set using switches for each memory card.

Therefore, with conventional data processing equipment, ■ memory
In order to manually set the control information value for each card, a force S of operating means such as a switch was required.

■ A means (such as an adder) is required to generate address allocation information, that is, a start address for that memory unit, from the memory unit capacity value for each memory card. To increase.

■ Control information value for each memory card, 191j(zu adder' error, etc.) If there is an error in the start/IJ controller, or if there is an error in the control information due to a manual operation error, it is not checked. Therefore, it is difficult to detect it at the initial stage.

There were drawbacks such as.

[Purpose of the invention]

An object of the present invention, in order to improve such drawbacks, is to store the control information of the memory unit for each memory card in the ROM in advance, and have the ePtJ manage this information so that it can be checked in advance. It is an object of the present invention to provide a memory control information setting method that performs the following steps.

[Structure of the invention]

In order to achieve this object, the memory control information setting method of the present invention provides a memory system consisting of a plurality of memory cards each having a memory unit of an arbitrary capacity. , each memory card has a volatile storage means for storing memory card control information values unique to the memory card and its check data, and at the time of initial setting, the CPU stores the non-volatile storage means. The memory card control information and check data are read out to check their normality, and for the address information value, after creating memory allocation information, these data are written into the data holding means, and based on this written data, the memory is It is characterized by being controlled.

[Embodiments of the invention]

An embodiment of the present invention will be described with reference to FIG.

In FIG. 2, 1 is a CPU, and 2 to fL are memory cards. Since each memory card has the same configuration except for the size and number of memory units, memory card 2 will be representatively explained.

The CPU is provided with a check section 11, an addition section 12, etc., and a data bus 20 is provided with a receiver 13 and a driver 14.
Connected to 0.

Memory card 2 includes memory unit 20 .

21, comparison circuits 2 2 , 2 2 ′, address assignment information registers 2 3 , 2 3 ′, ROM 24 , timing information register 25 , timing signal generation circuit 25 .
5, a multiplexer 26, a comparison circuit 27, a card address information setting register 28, etc. are provided.

The ROM 24 stores control information specific to the memory card 2, such as the capacity (address capacity) of the memory unit 20.21, the read/write timing signal of the memory unit 20.21, and the row address/column address. Control information such as a strobe timing signal is stored, and a parity bit, for example, is added to this control information to check whether the data read from the ROM 24 is correct or not.

At the time of initial setup of the data processing system, the card must be
The address information setting register 28 contains the memory card number (for example "2") from the back panel etc.
is set.

Then, at the time of initial setup, the CPUI will
In order to read necessary control information from the OM 24, the first memory card number "2" is sent. This number is transmitted to the comparison circuit 27 via the address bus 100 and a match is obtained, so that the ROM 24 of the memory card 2 sequentially reads control information according to the transmitted address.

Since a parity bit is added to this control information, the parity is checked by the CPU checker 11, and when reading the capacity of the memory unit 20, 21, the capacity is written in advance. Its normality is confirmed by checking whether it is outside the maximum and minimum ranges of the memory units in the system, and whether it is outside the same range in the case of timing information.

As for address information, a start address roo, . For memory unit 21, 16 is the start address of memory unit 20 plus the capacity of 16K of memory unit 20.
The first two bits "01" of K are set in the address assignment information register 23'.

For timing-based breeding, these are set in the timing information register 25.

Next, the CPU outputs the next number "3" of the memory card 2, reads out similar control information from the ROM of the memory card 3 (not shown), and checks these. Then, the upper bits of the value obtained by adding the capacities of memory units 20 and 21 are written in the start address register for the first memory unit. In this way, the same control information is read and checked for all memory cards up to the memory card, and the system is operated after the necessary data is set in the address assignment information register and timing information register. Become a coward.

Therefore, when memory access is performed during data processing, the higher bits are transferred to the comparison circuits 22 and 22'.
...and if they match, the memory of the access destination
The unit can be detected and the necessary timing information is stored in its memory fist card's timing information register 2
5, the timing generation circuit 25. ．．
5 can control the generation of these.

Note that the addressing of the ROM and registers in each memory card shares the normal address information thread 100, and
Reading of OM data is performed by using multiplexer 26 to share common data bus 200.

In the case of writing data to a register, the overbus 200 is similarly shared.

A second embodiment of the present invention will be described with reference to FIGS. 3 and 4.

In FIG. 3, the same reference numerals as in other figures indicate the same parts. 29
Ha l! i”-P'fLOM(Fi1gctr*c Er
asahle Prog-ramalrlg ROM
), and is a non-volatile PROM that can be written to, for example, by a 5V normal source. Therefore, even if the power is cut off, the stored data will not be erased. Control information for the memory unit 20.21 of the memory card, such as timing value and capacity information, is stored in this g*-paoM 29 along with check bits.

When initializing the system, the CPU first reads the timing information value from the g"-FROM 29 of the memory card 2, performs a normality check such as a security check in the check section 11, and then restores the original memory. Write to another address ADRI of B''-FROM 29 of card 2. In this way, the CPUI
After reading out the necessary timing information from M29 and checking it, 11! After rewriting the above address ADRI of t”-FROM29, the CPU then writes E”-
From 280M29, this time Memory Units 1-20.21
After reading the capacity value of the memory unit and confirming its normality in the same way as the timing information value, the adder 12 adds the capacity of the memory unit to the address assignment information of the previous memory unit, and the memory... Generate address assignment information for the unit and use the original memory card 2's E"-FRO
Write to address AD几2 of Iya in M29. These operations are then performed for all memory cards 2-rL.

However, the above address ADRI is an ff prepared for storing the timing information value checked by the CPUI.
”-This is the address of FROM29. Also, the address AD
R2 is E'-F prepared for storing the address assignment information value of the memory unit generated within the CPU1.
This is the address of the ROM 29, and there are as many memory units as there are memory units in the memory card. That is, if there are two sets of memory units, AD 2-1. AI) There are two, 几2-2.

30 is a B'-FROM read address sending circuit (hereinafter referred to as address sending circuit), gl-280M2
It generates 9 addresses ADR1, AD 2, etc. and sends them out. This generation and transmission timing will be explained with reference to FIG. Assuming that the memory cycle is T, the first half is the period during which address information is required, and the address AD2 is output during this period. The following period Il
1 is a period that requires timing, during which the address AJ) 1 is output.

A timing generation circuit 31 receives the timing information value outputted from the E''-280M29 and generates a timing signal corresponding thereto, and corresponds to the timing generation circuits 25..5 in FIG.

Next, the operation of the second embodiment will be explained.

During system operation, each memory card, e.g.
In the card 2, the address ADR2 of the E''-FROM 29 is outputted from the address sending circuit 30 at the timing T when address information is required, and transmitted to the B''-FROM 29 via the multiplexer 26'. As a result, the address assignment information of the memory write unit 20 is output from the B"-FROM 29, and the upper bits of the sending address sent from the CP'UI are compared in the comparison circuit 22. If they match, the memory write unit 20 unit 2
0 is selected. As shown in Figure 3, the memory card 2
If there are multiple memory units in one memory card, as in ``E''-FROM 29, which stores address assignment information for multiple memory units.
Address AD 几2-1. By time-divisionally outputting the AD 2-2 from the address sending circuit 30, the memory
Comparisons between the address assignment information of the units 20 and 21 and the upper bits of the sending address are performed in a time-division manner in the comparison circuits 22 and 22'. ' Thus, at the selected timing of the memory unit, the address ADRI is sent from the address sending circuit 30, and F! ! -280M29 outputs timing information, and based on this, timing signals such as row address and column address, read strobe and write enable are input to the selected memory unit by the timing generation circuit 31. Read/write control is performed for the unit.

Note that the art writing from the CPU of the E"-FROM in each memory card shares the normal address bus 100, and reading of the E"-P OM data to the CPU uses the multiplexer 26. This is done by sharing the bus 200.

The data bus 200 is also shared for write data from the CPU to the E''-FROM.

〔Effect of the invention〕

According to the present invention, no hardware such as a switch or an adder is required in the memory card. According to the first embodiment, R.O.
Although registers are required, ROMs do not require as much space as switches, and registers can be built into the LSL. According to the second embodiment, the E''-ROM also does not require space for switches, and the circuit that controls the address sending of the g''-p OM in a time-sharing manner can be incorporated into an LSI. However, space saving can be realized.

In addition, errors in memory card control information can be detected during initial setup, and the CPU can manage memory card capacity information, address assignment information for each unit in each memory card, and the entire memory system. Capacity is C
PU can be understood.

Therefore, if a certain memory card fails during system operation, the card can be disconnected and address assignment information can be reset.

Furthermore, there are no switches or the like that require manual settings, and all settings can be made automatically. If you want to change the settings, you can change the contents of 30M (or GA-F ROM), or change the contents of 30M (or GA-F ROM), or change the ROM (or E'-
FROM).

[Brief explanation of drawings]

Figure 1 shows a memory unit and memory card. FIG. 2 is a diagram illustrating the configuration of one embodiment of the present invention, FIG. 3 is a diagram illustrating the configuration of another embodiment of the present invention, and FIG. 4 is a diagram illustrating address information and timing information. In the figure, 1 is a CPU, 2 to rL are memory cards, 11 is a check section, 12 is an addition section, 13 is a receiver, 14 is a driver, 20.21 is a memory unit, 22, 22
' is a comparison circuit, 23.23' is an address assignment information register, 24 is R, OM, 25 is a timing information register,
25.5 is a timing signal generation circuit, 26 and 26' are multiplexers, 27 is a comparison circuit, 28 is a card address information setting register, 29 is ff"-FROM, 3
0 is an address sending circuit, 31 is a timing generation circuit, 1
00 indicates the address bus and 2oo indicates the data bus. Patent applicant Fujitsu Ltd. agent Patent attorney Akira Yamatani

Claims (1)

[Claims] 1. In a memory system composed of a plurality of memory cards having memory units of arbitrary capacity,
A CPU having a check section and an addition section, and each of the above memories.
Each card has a non-volatile storage means for storing the memory card control information value unique to that memory card and its check data, and at the time of initial setting, the CPU controls the memory card from the first half non-volatile storage means. The information and check data are read and their normality is checked, and memory allocation information is created for the address information value, and then these data are written into the data holding means, and memory control is performed based on this written data. A memory control information setting method characterized by the following. 2. The memory control information setting method according to claim 1, wherein a register is used as the data holding means. 3. B"-FROM is used as the non-volatile storage means, and the E"-PI'LOM is used as the data retention means.
The memory control information setting method according to claim 1, characterized in that the method uses: