JPS63135442U - - Google Patents

Info

Publication number
JPS63135442U
JPS63135442U JP2551087U JP2551087U JPS63135442U JP S63135442 U JPS63135442 U JP S63135442U JP 2551087 U JP2551087 U JP 2551087U JP 2551087 U JP2551087 U JP 2551087U JP S63135442 U JPS63135442 U JP S63135442U
Authority
JP
Japan
Prior art keywords
memory
range data
address range
priority
setting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2551087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2551087U priority Critical patent/JPS63135442U/ja
Publication of JPS63135442U publication Critical patent/JPS63135442U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の機能ブロツク図、第2図およ
び第3図は本考案を日本語ワードプロセツサに適
用した一実施例を示し、第2図はそのメモリ選択
回路等の回路構成図、第3図はメモリ選択回路1
7,18,19,20の詳細回路図である。 11〜14……メモリ、17〜20……メモリ
選択回路、21,22……アンドゲート、31…
…開始アドレスレジスタ、32……終了アドレス
レジスタ、33……一致検出回路、34……アン
ドゲート、35……インバータ。
FIG. 1 is a functional block diagram of the present invention, FIGS. 2 and 3 show an embodiment in which the present invention is applied to a Japanese word processor, and FIG. 2 is a circuit diagram of the memory selection circuit, etc. Figure 3 shows memory selection circuit 1.
7, 18, 19, and 20 are detailed circuit diagrams. 11-14...Memory, 17-20...Memory selection circuit, 21, 22...And gate, 31...
...Start address register, 32...End address register, 33...Coincidence detection circuit, 34...AND gate, 35...Inverter.

Claims (1)

【実用新案登録請求の範囲】 複数のメモリの選択を、シリアルなアドレスを
各メモリに対し割当てて行うメモリ選択装置にお
いて、 各メモリに割当てられるべきアドレス範囲デー
タを設定する設定手段と、 この設定手段による各メリに対するアドレス範
囲データを記憶する記憶手段と、 上記複数のメモリのアドレス指定に優先順位を
つけるメモリ優先順位付与手段と、 アドレス指定の際、上記記憶手段内のアドレス
範囲データおよびメモリ優先順位付与手段による
優先順位にしたがつて1つのメモリを選択する選
択手段と を有することを特徴とするメモリ選択装置。
[Claim for Utility Model Registration] In a memory selection device that selects a plurality of memories by allocating serial addresses to each memory, a setting means for setting address range data to be allocated to each memory, and this setting means a storage means for storing address range data for each memory according to the above; a memory priority assigning means for prioritizing addressing of the plurality of memories; and address range data and memory priority within the storage means when specifying an address. 1. A memory selection device comprising: selection means for selecting one memory according to the priority given by the assignment means.
JP2551087U 1987-02-25 1987-02-25 Pending JPS63135442U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2551087U JPS63135442U (en) 1987-02-25 1987-02-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2551087U JPS63135442U (en) 1987-02-25 1987-02-25

Publications (1)

Publication Number Publication Date
JPS63135442U true JPS63135442U (en) 1988-09-06

Family

ID=30825732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2551087U Pending JPS63135442U (en) 1987-02-25 1987-02-25

Country Status (1)

Country Link
JP (1) JPS63135442U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06149667A (en) * 1992-11-10 1994-05-31 Oki Farm Wear Syst:Kk Method for increasing memories

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56103748A (en) * 1980-01-23 1981-08-19 Toshiba Corp Memory system
JPS6086642A (en) * 1983-10-18 1985-05-16 Fujitsu Ltd Setting system of memory control information

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56103748A (en) * 1980-01-23 1981-08-19 Toshiba Corp Memory system
JPS6086642A (en) * 1983-10-18 1985-05-16 Fujitsu Ltd Setting system of memory control information

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06149667A (en) * 1992-11-10 1994-05-31 Oki Farm Wear Syst:Kk Method for increasing memories

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