JPS6218758U

JPS6218758U -

Info

Publication number: JPS6218758U
Application number: JP8219986U
Authority: JP
Priority date: 1986-05-30
Filing date: 1986-05-30
Publication date: 1987-02-04
Also published as: JPS6349772Y2

Description

[Brief explanation of the drawing]

図は本考案の１実施例を示す回路図である。図において、１……仮想アドレスレジスタ、２
……アドレス生成回路、３……アドレスデコーダ
、４……比較回路、５……実アドレスレジスタ、
６……記憶アレイ。 The figure is a circuit diagram showing one embodiment of the present invention. In the figure, 1...virtual address register, 2
... Address generation circuit, 3 ... Address decoder, 4 ... Comparison circuit, 5 ... Real address register,
6...Memory array.

補正昭６１．５．３０考案の名称を次のように補正する。考案の名称アドレス変換装置実用新案登録請求の範囲、図面の簡単な説明を
次のように補正する。Amendment May 30, 1986 The name of the invention is amended as follows. Name of the invention: Address conversion device The scope of the claims for utility model registration and the brief description of the drawings are amended as follows.

【実用新案登録請求の範囲】仮想アドレスを実アドレスに変換するアドレス
変換装置において、複数の仮想アドレスを記憶す
る領域と複数の実アドレスを記憶する領域とが異
なるアドレスで指定される構成を有する記憶アレ
イと、外部から与えられた仮想アドレスを示すビ
ツト群の一部のビツトに基づいて、第１および第
２のアドレスを生成し該第１および第２のアドレ
ンに応答して、前記記憶アレイ中の仮想アドレス
および実アドレスを順次読み出す読出し手段と、
前記外部から与えられた仮想アドレスを示すビツ
ト群の残りのビツトの内容と前記記憶アレイから
読み出される仮想アドレスとを比較手段と、この
比較手段の比較結果により一致が示されたとき前
記記憶アレイから読み出される実アドレスを格納
する実アドレスレジスタとから構成したことを特
徴とするアドレス変換装置。[Claims for Utility Model Registration] An address conversion device that converts a virtual address into a real address, in which an area for storing a plurality of virtual addresses and an area for storing a plurality of real addresses are specified by different addresses. generates first and second addresses based on the array and some bits of a group of bits indicating an externally applied virtual address; reading means for sequentially reading virtual addresses and real addresses of
means for comparing the contents of the remaining bits of the bit group indicating the virtual address given from the outside with the virtual address read from the storage array; An address translation device comprising: a real address register that stores a real address to be read.

【図面の簡単な説明】図は本考案の一実施例を示す回路図である。図において、１……仮想アドレスレジスタ、２
……アドレス生成回路、３……アドレスデコーダ
、４……記憶アレイ、５……比較回路、６……比
較結果レジスタ、７……実アドレスレジスタ。BRIEF DESCRIPTION OF THE DRAWINGS The figure is a circuit diagram showing an embodiment of the present invention. In the figure, 1...virtual address register, 2
... Address generation circuit, 3 ... Address decoder, 4 ... Memory array, 5 ... Comparison circuit, 6 ... Comparison result register, 7 ... Real address register.

Claims

[Scope of utility model registration request]

In an address translation device that converts a virtual address into a real address, there is provided a storage array having a configuration in which an area for storing a plurality of pairs of virtual addresses and real addresses and an area for storing page table entry addresses are specified by different addresses. , generates first and second addresses based on some bits of a bit group indicating an externally applied virtual address, and generates a virtual address in the storage array in response to the first and second addresses. and a reading means for sequentially reading page table entry addresses; a comparing means for comparing the contents of the remaining bits of the bit group indicating the externally given virtual address with the virtual address read from the storage array; When the comparison result of the means indicates a match, the real address read from the storage array is stored in an address register, and when the comparison result does not indicate a match, the real address is stored in the page table entry address. An address translation device characterized in that: is stored in the address register.