KR950000495B1 - Node memory system for parallel processing system - Google Patents

Abstract

The interface of node memory and MBUS consists of a special controller chip and a multiple control module for data read/write operation in parallel processing system. The multiple control module comprises a type/size module for deciding the type/size of transaction, a 64 bit latch module for controlling the difference of data width at data input/output, a transmission module for controlling latch, a parity generation/check module for checking the effectiveness of input/output data a burst module for having 32 bit counter for burst transmission from 1byte to 128 byte, a module for generating self-address continuously without designating new address.

Description

Node Memory System for Parallel Processing System

1 is a diagram of the present invention for interfacing to node memory.

2 is a diagram of the present invention for a control module.

3 is a flowchart of data and control signals related to input and output of data.

4 is a diagram of a node memory structure.

The present invention relates to a node memory system for a parallel processing system. The parallel processing system is composed of a set of nodes including a processor, a memory, and a controller. The parallel processing system improves the performance of the overall system by dividing one process into several processors.

Looking at a node structure constituting a conventional parallel processing system, a general-purpose processor for general arithmetic calculation and control, and image processing, graphics, signal processing for specific application processing, for example It consists of a node processor divided into dedicated processors for signal processing, a node memory for storing data processed by the processor, and a controller for communicating with neighboring nodes.

Node memory in a parallel processing system is accessed by neighboring nodes and processors in the node via a bus.

The present invention relates to an interface between a node memory providing a work area for a node processor and a specific bus (MBUS) in an internal structure of a node constituting a parallel processing system. In this way, burst transmission can be performed efficiently.

The node memory interface is, as shown in FIG. 1, a large bus MBUS, a commercially available controller chip that controls DRAM constituting the node memory, for example, DP8422A (b), a node memory (16 MB), and a control module ( D).

Of the information transmitted to the specific bus (MBUS) by the master (master) who wants to use the node memory, the control signal is first decoded by the control module (d) and supplied to each section of the interface.

As shown in Fig. 2, the control module includes the Ecas module (A), the burst module (C), the latch module (D), the transfer module (E), the type module (B), It consists of a size module (bar), a parity generation / checking module, and a datalatch module (e). Then, each of the modules constituting the control module of the present invention will be described.

The Ecas module ((a) of FIG. 2) is a module for generating a signal for selecting a bank to be used in a node memory composed of four banks. Generates the bank select signal.

In addition, the generated signals support burst operations of 32 bits or more in the burst module (C), and may be used for addressing for data input and output.

This module is implemented as a state machine and operates according to the change of input condition. The type module (b) is a part for determining the type of transaction. The burst operation continues until the value of the counter set by the transaction size becomes "0". When the value reaches "0", a new transaction is started.

This module uses only two bits to distinguish between write and read transactions. However, the burst module (C) allows data transfer from 1 byte up to 128 bytes to be continuously input and output without new addressing.

It has a 32-bit counter and generates a signal to give it a new column address. The 32-bit counter is then set by the result decoded by the size module (bar).

The operation sends the final response signal once every two clocks according to the 64-bit width that the bus can transmit once the response signal from the node memory controller when transmitting and receiving data based on the maximum 32 bits.

The latch module D controls the flow of 64-bit data during input / output between the node memory and the specific bus (MBUS).

The latch module D uses eight 8-bit latches for 64-bit data input and output.

And, depending on the size of the transaction, the latch may operate. However, since the node memory can input and output only 32 bits at a time, the first four latches are operated first, and after receiving the response signal, the next four latches are operated to transmit data. In contrast, the output is latched twice and output at one time. As such, signals for controlling the operation of the latch are generated and input to the transmission module (e) according to the type of transaction.

The transmission module (e) directly controls the latch with an output signal representing the size of a transaction in the magnitude module (bar) of the output control signal of the latch module (d).

The size module (bar) is a module that determines the size of a transaction. The size module 1 generates an input signal for controlling the burst transmission by decoding the size of the actual transaction. The size module (bar) controls latches when data is input and output according to the size of the transaction. It consists of a size module 2 for generating a signal for. The size of a transaction decoded by this module is from 1 byte up to 128 bytes.

At this time, a transaction size of 32 bits or more is regarded as burst mode transmission and operates the burst module (C).

The output signal of this module is input to the transmission module (e) for the purpose of controlling the latch, and when it is 32 bits or more, it generates an input signal for notifying the start of burst transmission to the burst module (C).

The parity generation / check module checks whether the data is valid at the time of input / output of the data.

If the data is wrong, the I / O of the data is canceled and an error occurrence signal is sent to the master.

It is also processed in the function control block of the bus to start a new transaction. Refresh, one of the important elements of node memory, is handled using the DP8422A chip, a specific commercial controller chip that controls the DRAM already mentioned.

The refresh type supported by the DP8422A includes automatic internal refresh, externally controlled / burst refresh, and refresh request / acknowledge.

This part is an inherent area of the DP8422A DRAM controller chip and will be omitted here. As shown in Fig. 4, the node memory is composed of four memory chips (Fig. 4 (a)) of 4M bytes and four DRAMs for parity of data. Up to 32 bits can be input / output in one clock with one addressing. So far we have looked at the elements that make up an interface.

Next, an operation process according to input and output of actual data will be described with reference to the flowchart of FIG. 3.

The master first sends information on the bus to indicate the type of transaction and the address in node memory.

The transmitted addresses and other control information operate the control module and the node memory controller to make the node memory input and output. After sending the address, the master sends as much data as it wants to send continuously. In the process of inputting data, the address of the node memory is loaded on the bus together with a signal indicating that an address is generated.

The address information is decoded to generate a signal (RAS, CAS) (see FIG. 4) for selecting an address in the corresponding node memory, and a signal WE indicating the type of transaction.

First, as the RAS signal is activated, a row address is output, and as the next CAS signal is activated, a column address is output to determine an address in the node memory to which data is input.

After a certain node memory data setup time, data is then latched into the node memory and parity is generated and stored in the parity's corresponding memory.

In this case, when the burst input is 32 bits or more, the corresponding RAS and CAS signals are simultaneously activated to continuously input by 32 bits.

After a single 32-bit input to the node memory, the corresponding signal from the node memory controller is activated to obtain a new open dress, allowing the burst transmission by continuously creating a new open dress for the duration of this ecology.

Next, let's look at the process of outputting data.

When 64-bit data is output in the node memory, the size of data that the node memory can export in one clock is 32 bits, so the data is exported on the bus once every two clocks.

As in the input process, the decoding process of the address information is the same and only indicates that the write signal WE goes high to output data. Burst outputs are the same as burst inputs, with slight differences in the latch control.

If an error occurs while parity check is performed on data output, data output is stopped and an error signal is sent to the bus.

As described above, in the present invention, a parallel processing system uses a DP8422A chip, which is a specific commercial controller that controls DRAM in node memory, as an interface between a specific bus (MBUS) and node memory, and controls a read and write operation of actual data. With a control module of, one process can be divided into several processes to improve the performance of the overall system. In addition, while synchronizing to the bus clock, the data transfer can be efficiently performed by making the most of the 64-bit data width.

Claims (1)

In a parallel processing system comprising a plurality of dedicated and general purpose processors, a node memory for storing data processed by the processors and a specific bus (MBUS), an interface between the node memory and the specific bus is the node memory. It consists of a specific commercial controller chip (trade name: DP8422A) for controlling a plurality of DRAMs in the memory, and a plurality of control modules for reading and writing actual data, and the plurality of control modules determine the type and size of a transaction. Type and size modules; A 64-bit latch module for controlling the difference in data width during data input and output and a transmission module for controlling the latch; A parity generation / checking module for checking whether data is valid when inputting / outputting data; Burst module with 32-bit counter for burst transfer from 1 byte to 128 bytes; And a module configured to continuously generate its own address without designating a new address and performing data input and output while synchronizing to a specific bus (MBUS) clock.