JPS63205751A - Bus controller - Google Patents

Abstract

PURPOSE:To realize the titled controller without necessitating an additional circuit or by providing only a few additional circuits, by providing a common data bus and an address bus between a data processing means and each access object means, and also, providing a control signal line corresponding to the kind of respective access object means. CONSTITUTION:A data processing means (processor) 11 supplies an access control signal to plural timing signal generating circuits 13A-13C. On the other hand, the processor 11 supplies access object discriminating information to a memory kind deciding circuit 12. The timing signal generating circuits 13A-13C which have been started by the memory kind deciding circuit 12 converts the access control signal to a control signal conforming to its access object means (memory ICs) 20A-20C. In prescribed memory ICs 20A-20C to which this control signal is supplied, an address signal and data are sent and received to and from the processor 11 through an address bus 21 and a data bus 22. In such a way, in case of connecting plural memory ICs 20A-20C whose kinds are different to the processor 11, it can be realized without necessitating an additional circuit at all or by providing only a fed additional circuits.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention connects a data processing device and a storage device, peripheral device, or other data processing device that is accessed by this data processing device. Regarding bus control devices that control data buses, address buses, and various control signal buses, in particular, additional circuits required for bus connection even if the access control methods of the devices to be accessed are different for each device. It is designed to simplify the .

(Prior Art) In conventional data devices, such as processors, when connecting external memory, peripheral devices, or other processors of different types, a unique bus signal that does not depend on the type of the device to be accessed is used as a bus signal between the two. Techniques have been adopted, such as determining a general-purpose control method, or, in the case of a memory in particular, determining a signal and control method suitable only for that memory. The latter method is particularly preferred in very specific applications because it minimizes the additional circuitry required for connection.

By the way, in network control devices etc., ROM
When programs stored in the ROM coexist with large amounts of writing and reading data, or when only the initialization program is stored in the ROM.
For example, when a program that should be executed is read from another device using an initialization program, etc.
Multiple types of memory, e.g. ROM, static type R
AM, dynamic RAM, etc. may be mixed. In such applications, it is not possible to use a control method suitable only for a specific memory as described above.

Therefore, in this case, it is necessary to use a processor with a general-purpose control method and add a circuit on the memory side to create a control signal suitable for the memory. This additional circuit has a complex configuration and is provided on the memory side, which not only increases the number of parts and mounting area when configuring the network control device, but also increases the speed due to the operation delay time of the additional circuit. There is a problem that memory access cannot be realized.

Furthermore, if a control method for a specific memory is used, a large number of bus control signal lines will be required because the address signal output method and control signals will differ depending on the type of target memory. Therefore, such a method cannot be used in a processor IC that has a limited number of external terminals. Broadly speaking, similar problems arise with connections to peripherals and other processors.

(Problems to be Solved by the Invention) Conventionally, when connecting a plurality of access target devices of different types to a data processing device, the configuration of the circuit to be added becomes complicated, and the configuration of the entire device becomes complicated. However, the disadvantage is that the number of components and mounting area increase, and fast memory access cannot be achieved.

This invention has been made in consideration of the above circumstances, and its purpose is to eliminate the need for additional circuits or to require only a small amount of additional circuitry when connecting multiple access target devices of different types to a data processing device. It is an object of the present invention to provide a bus-based w+i device which can be realized by providing an additional circuit and which can realize high-speed access.

[Structure of the Invention] (Means for Solving the Problems) A bus control device of the present invention includes a data processing means, a plurality of access target means having different types of access targets of the data processing means, and a bus control device of the present invention. A common data bus and an address bus are provided between the data processing means and each of the access target means, and an i control signal line corresponding to the type of each of the access target means, and A plurality of control signal generating means converting and supplying the access control signal into a control signal suitable for the corresponding access target means when the III signal is input, and access target identification information output from the data processing means. and object type determining means for determining the access target means to be accessed based on the access target means and selectively activating the control signal generating means corresponding to the access target means.

(Operation) When the data processing means accesses a specific access target means, the data processing means supplies access control signals to the plurality of control signal generation means. On the other hand, the data processing means supplies the access object identification information to the object type determination means. The target type determining means determines the access target means to be accessed based on the access target identification information, and selectively activates the control signal generating means corresponding to the access target means. The control signal generation means activated by the object type determining means converts the access control signal into a control signal suitable for the access object means. A specific access target means to which this control signal is supplied exchanges address signals and data with the data processing means via an address bus and a data bus.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention, particularly when a plurality of memories of different types are used as access targets.

In the figure, 10 is a processor IC, 20A.

20B and 20C are external memory ICs that are accessed by this processor IC and are of different types. The processor IC 10 includes a processor 11, a memory type determination circuit 12, and the three memory ICs 20A.

It is composed of timing signal generation circuits 13A, 13B, and 13C provided corresponding to 20B and 20C.

The processor 11 has memory ICs 20A, 208,
This is a device that accesses 20G, processes the data read from these memory ICs, and writes the processed data to the memory IC. This processor 11 creates an address signal to be accessed and outputs it to the outside, and also outputs memory identification information for specifying the access target to the memory type determination circuit 12. Furthermore, the processor 11 sends access control signals to three timing generation circuits 13A, 13.
8. Output at 130. The processor 11 ends the memory access operation in response to the access end signal output from each timing generation circuit 13. Furthermore, before starting the access, the processor 11
2, set memory type information and identification information of the memory to be accessed.

The memory type determination circuit 12 holds memory type information set by the processor 11, and the memory type determination circuit 12 retains memory type information set by the processor 11.
The type of the memory to be accessed is determined by comparing it with the memory identification information output by the memory IC 20.
selectively activates the timing control signal generation circuit 13 of. The activated timing control signal generation circuit 13 converts the access control signal from the processor 11 into a control signal suitable for each memory IC and outputs it at an appropriate timing.

The memory ICs 20A, 208.200 are connected to the processor IC10 by one system of address bus 21 and one data bus 22, respectively, and the timing control signal generation circuits 13A, 13B, 13C are connected to each control signal. They are connected by wires 23A, 23B, and 23C.

In such a configuration, the processor 11 is a memory IC.
Based on the memory identification information output when accessing 20, the memory type determination circuit 12 activates the corresponding timing signal generation circuit 13, and the activated timing signal generation circuit 13 responds to the access control signal output from the processor 11. The control signal is converted into a control signal suitable for the memory KC20 and output to the control signal line 23. The operation of the memory IC 20 is controlled based on this control signal, and addresses are specified based on the address signal output to the address bus 21, and the memory IC 20 is connected to the processor 1 via the data bus 22.
Data is exchanged with 1. When the operation of the memory IC 20 is completed, the timing signal generation circuit 13 that has been outputting the control signal outputs the completion signal to the processor 11.
Return to. This completes the memory access operation of the processor 11.

According to the above embodiment device, when opening and opening access to the memory,
Since the memory type determination circuit 12 determines the type of memory to be accessed, the processor 11 can read and write data regardless of the type of memory being accessed.

Furthermore, it is only necessary to provide the memory type determination circuit 12 and the number of timing signal generation circuits 13 corresponding to the memory ICs 20 to be accessed only on the processor IC 10 side.
There is no need to provide an additional circuit on the C20 side. For this reason,
A conventional general-purpose memory IC can be directly connected to the processor IC 10 as each memory IC 20, and no additional circuits are required other than the processor 1c10 and the memory 1c20. Furthermore, since there is no unnecessary circuit behind both ICs, high-speed access is achieved.

Furthermore, since a common address bus 21 can be used for multiple memories l020 of different types and there is no need to provide an independent address bus for each memory IC, the number of external terminals of the processor ICl0 can be reduced. It will not cause an increase.

In order to explain the first embodiment more specifically, an example in which the present invention is implemented in a bus control device particularly suited for a specific application will be explained with reference to the block diagram of FIG. 2. In this second embodiment device, as the memory IC 20 to be accessed, a dynamic RAM RAM>20a and a static type R
Two memory ICs, AM (SRAM) 20b, are used, and an address signal output from the processor 11 is used as memory type information.

The processor IC 10 includes a processor 11, a memory type determination circuit 12, a DRAM timing signal generation circuit 13a, and an SRAM timing signal generation circuit 13b. Here, the PAO is inside the processor ICl0.
- A 21-bit internal address bus 14 consisting of a PA 20 is provided, and this internal address bus 14 is connected to an external address bus 21 via an address multiplexer 15 provided inside the processor IC 10. . Here, 16 bits of AO to A15 are provided as the external address bus 21, and the DRA
Of these, only 10 bits Ao to A9 are connected to M20a.

The processor 11 outputs an address signal to the 21-bit internal address bus 14, and also outputs an RW times signal indicating data read or write as an access control signal.

Here, the memory area accessible by the processor 11 is ro expressed in hexadecimal as shown in FIG.
From address 00000J to NFFFFFFJ address FF, of which ro0000
Area 1 of 64 bytes from address 0J to address r0OFFFFJ corresponds to SRAM20b, and rloo
It is assumed that a 1 Mbyte area 2 on the FF from address ooOJ to address rIFFFFFJ corresponds to the DRAM 20a.

In this case, from the processor 11 to the memory type determination circuit 12
The most significant bit signal PA20 of the internal address bus 14 is used as the identification information of the memory to be accessed which is input to the
is used. Furthermore, in the memory type determination circuit 12, the memory type information set by the processor 11 has an address relationship as shown in FIG. Then, the memory type determination circuit 12 determines the type of the target memory by comparing the address relationship shown in FIG. Based on this, either the DRAM timing signal generation circuit 13a or the SRAM timing signal generation circuit 13b is selectively activated, and a mode signal MODE is outputted to the address multiplexer 15 to indicate the target memory distinction determined by type.

After activation, the DRAM timing signal generation circuit 13a converts the RW signal and outputs various control signals suitable for the DRAM 20a to the control line 23a consisting of a plurality of lines, and also outputs the row address to the external address bus 21. , ROWOUT signals to the address multiplexer 15. The control signals output to the control line 23a include a DRD signal that is “L” when writing data and “H” when reading data, a DRAS signal that indicates that the row address is being output to the external address bus 21, and This is a DCAS signal indicating that a column address is being output to external address bus 21.

These control signals are write control signals to the DRAM 20a,
Row address strobe signal, column address
Supplied as a strobe signal. Further, an RDY signal indicating the end of the operation is returned to the processor 11.

After startup, the SRAM timing signal generation circuit 13b performs the RW multiplication signal conversion and outputs various control signals suitable for the SRAM 20b to a plurality of control lines 23b. These control signals are an SRD signal that is "L" when writing data and "H" when reading data, and an RWT signal that is a timing signal for writing and reading. These control signals are supplied to the SRAM 20b as a write control signal and a chip select signal. Further, an RDY signal indicating the end of the operation is returned to the processor 11.

The address multiplexer 15 uses the M output from the memory type determination circuit 12 to enable both the DRAM 20a and the SRAM 20b, which have different address input methods, to use the same external address bus 21.
ODE signal and DRAM timing signal generation circuit 13a
The address PAO-PA20 on the internal address bus 14 is set to the fourth
It is output to the external address bus 21 under the relationship shown in the figure.

That is, the MODE signal is the most significant bit signal of the internal address, and when MODE-"L It, the memory type determination circuit 12 determines that the SRAM 20b is the access target. In this case, the address multiplexer 15 The lower 10 bits of the address PAO to PA9 and the higher 6 bits of the address PAIO to PA15 of the internal address bus 14 are directly transferred to the external address bus 2.
The lower 10 bits of 1 are output as addresses AO-A9 and the upper 6 bits are output as addresses A10 to A15.

When MODE is “H”, the memory type determination circuit 12 is D.
This is when the RAM 20a is determined to be accessed, and in this case, the output method differs depending on the ROWOUT signal from the DRAM timing signal generation circuit 13a. First, when ROWOUT is "H", the address multiplexer 15 transfers the upper 10 bits of addresses PA10 to PA19 of the internal address bus 14 to the lower 10 bits of the address AO-A9 of the external address bus 21.
Output as . At this time, no valid address is output to the upper six bits of the external address bus 21.

When ROWOUT is "ON", the address multiplexer 15 outputs the address PAOO-PA9 of the upper 10 bits of the internal address bus 14 as the address input method of the lower 10 bits of the external address bus 21. At this time, no valid address is output to the upper six bits of the external address bus 21.

The operation of the bus control device having the above configuration is shown in Figures 5 to 8.
This is shown in timing chart 1- in the figure. Here, FIGS. 5 and 6 show the case where the processor 11 selects the area 1 shown in FIG. 3, that is, the SRAM 20b, as an access target, and FIGS. This is a case where the area 1a2 shown in FIG. 3, ie, the DRAM 20a, is selected as the access target.

First, the operation shown in the timing chart of FIG. 5 will be explained. This means that the processor 11 is the SRAM 20b
When accessing and reading the stored data,
First, in order to access the SRAM 20b, the processor 11 sends, for example, ro01000 to the internal address bus 14.
Outputs Jl ground and outputs RW double signal “H” to indicate reading.
”.

The memory type determination circuit 12 receives the input address PA20.
is L', and the memory to be accessed is SR.
It is determined that it is AM20b. Based on this determination result, “L I
A MODE signal of I is output, and the SRAM timing signal generation circuit 13b is activated.

Address multiplexer 15 outputs PAO to PA15 of internal address bus 14 as is to external address bus 21, since the address area distinguished by the MODE signal is area 1. That is, the address r1000J is output to the external address bus 21.

The activated SRAM timing signal generation circuit 13b is
Since the RW double signal is “H”, the SRD signal is “HII”.
and R according to the operation timing of SRAM20b.
The WT signal is set to H''. Thereafter, the SRAM timing signal generation circuit 13b notifies the processor 11 that the data read operation of the SRAM 20b has been completed by setting the RDY signal to H''. On the other hand, the SRAM 20b reads data from address "1000" a predetermined time after both the SRD signal and the RWT signal are set to "HII". This read data is sent to processor 11 via data bus 22.

The operation shown in the timing chart of FIG. 6 is when the processor 11 writes data to the SRAM 20t). In this case as well, the processor 11 outputs rhol 000J address to the internal address bus 14 in order to access the SRAM 20b, sets the write data in a data buffer (not shown), and sets the RW double signal "L" to indicate writing. Make it.

At this time, since the address PA20 of the most significant bit of the internal address bus 14 is "L11," the SRAM timing signal generation circuit 13b is activated and the address multiplexer 15 is activated to output the internal address signal. PAO to PA15 on bus 14 are output as they are to external address bus 21. Therefore, external address bus 2
1, the address rlo00J is output.

The activated SRAM timing signal generation circuit 13b is
Since the RW double signal is “L II”, the SRD signal is “L”.
11, and sets the RWT signal to "Hl+" in accordance with the operation timing of the SRAM 20b.After this, the SRAM timing signal generation circuit 13b sets the RDY signal to "H" to indicate that the data writing operation to the SRAM 20b has been completed.
+e to notify the processor 11. On the other hand, in the SRAM 20b, the SRD signal is
r1 after a predetermined time after the WT signal becomes “HIT”
Write 1 data on the data bus 22 to address 000J.

Next, the operation shown in the timing chart of FIG. 7 will be explained. This is a case where the processor 11 accesses the DRAM 20a and reads the stored data. First, in order to access the SRAM 20b, the processor 11 outputs address NF1000J to the internal address bus 14, and doubles RW to indicate reading. Set the signal to ``H''.

The memory type determination circuit 12 receives the input address PA20.
detects that “HIT” and determines that the memory to be accessed is the DRAM 20a. Based on this determination result, “HIT” is sent to the address multiplexer 15.
It outputs the IT MODE signal and activates the DRAM timing signal generation circuit 13a.

The activated DRAM timing signal generation circuit 13a is
First, in order to output the row address, the DRAM 20a
The ROWOtJT signal is set to H°' in accordance with the operation timing of
Then, in order to output the column address, the ROWOUT signal is set to "L" and the DCAS signal is set to "L" in accordance with the operation timing of the DRAM 20a. At this time, the processor Since the RW signal from 11 is set to °°H°°, DRA
M timing signal generation circuit 13a1. tDRD signal “
Set to “H”.

In the address multiplexer 15, the MODE signal is
”, the DRAM timing signal generation circuit 1
ROWOUT signal from 3a is “H” 17) Toki 1. −
G, tPA 10 to PA 11, ROWOUT - When “L”, PAO to PA9 are respectively external addresses.
Output to bus 21. That is, row addresses and column addresses are supplied to the DRAM 20a in a time-division manner.

After this, the DRAM timing signal generation circuit 13a
RD indicates that the data read operation of AM20a is completed.
The processor 11 is notified by setting the Y signal to "H". On the other hand, the DRAM 20b receives the DRAS signal and the DCA signal.
Data is read from address rF1000J a predetermined time after both the S signals are set to "L" and the DRD signal is set to "H".

This read data is sent to processor 11 via data bus 22.

The operation shown in the timing chart of FIG. 8 is when the processor 11 writes data to the DRAM 20a. At this time, the process is the same as in FIG. 7 except that the DRAM timing signal generation circuit 13a sets the DRD signal to "°[", and the DRAM 20aG (tD
The data on the data bus 22 output from the processor 11 is written to address rF1000J after a predetermined time since the RD signal is "L" from IC6tlJ:I.

In this embodiment as well, since the memory type determination circuit 12 determines the type of memory to be accessed at the start of memory access, the processor 11 can read and write data regardless of the type of memory being accessed. . Furthermore, it is only necessary to provide the memory type determination circuit 12 and the number of timing signal generation circuits 13 and address multiplexers 15 corresponding to the memory ICs 20 to be accessed on the processor 1c10 side, and there is no need to provide an additional circuit on the memory IC 20 side. , high-speed access is achieved.

Furthermore, a common address bus 21 can be used for a plurality of memory ICs 20 of different types.

Next, various modifications of this invention will be explained.

[Modification 1] In the device of the second embodiment, the memory address space of the processor 11 was simply divided into DRAM and SRAM, but this is divided into three or more address spaces and each address space is Memories of different types may be selected.

[Modification 2] In order to connect memories of the same type but with different operating speeds, a necessary number of timing signal generation circuits 13 that generate 11 control signals matched to the operating speeds of the memories are provided to determine the memory type. The circuit 12 may be configured to determine the type of memory corresponding to the access address, that is, the operating speed, and activate the timing signal generation circuit 13 based on this result. In this case, for example, high speed S
RAM and low speed SRAM can be connected to processor IC 10 without using additional circuitry.

[Modification 3] In the device of the first embodiment, the address bus 21 and the data bus 22 are shared by a plurality of memories 1c20, and each memory I
Controllll1!12 that transmits a control signal to C20
3 are provided independently.

However, the result determined by the memory type determination circuit 12 is output to the outside of the processor Icl0, and the control signals that are not output simultaneously are multiplexed and output, and an additional circuit provided externally converts the multiplexed control signal into the determination result. - may be selected based on the selected memory and supplied to the corresponding memory.

The configuration of the embodiment device to which such a modification has been made is shown in the block diagram of FIG. In this modified example device, N types of external memories IC20A to 2ON are provided, and Nil timing signal generation circuits 13A to 13N are also provided in the processor ICl0 correspondingly.

Further, the control signals outputted from these timing signal light main circuits 13A to 13N are outputted to the outside of the processor IC 10 via only one control line 23.

Furthermore, the determination result of the memory type determination circuit 12 is the control a line 2.
4 is output directly.

On the other hand, gate circuits 25A to 25N are provided corresponding to the memories 1020A to 2ON, and signals from the control lines 23 and 24 are supplied in parallel to each of these gate circuits 25A to 25N.

Here, in each of the gate circuits 25A to 25N, one of them is connected to the signal line 2 based on the judgment result of the memory type judgment circuit 12.
3 control signals are selectively output.

According to such a configuration, by providing a small number of additional circuits (gate circuits 25), the control signal line 23 can be shared even when a large number of memory ICs are connected.
It is possible to prevent an increase in the number of external terminals of the processor ICl0.

[Modification 4] When a large number of memories of the same type are provided, the judgment result of the memory type judgment circuit 12 is outputted to the outside, and on the other hand, the logical sum of the judgment results is taken, and only one memory of the same type is provided.
The number of timing signal generation circuits 13 can be reduced by providing two timing signal generation circuits and activating the timing signal generation circuits based on the logical sum signal.

[Variation 5] In the device of the first embodiment, the memory type determination circuit 12 determines the memory to be accessed based on the address signal output by the processor 11, but this is based on information other than the address, such as The memory to be accessed may be determined based on a signal for distinguishing between an instruction fetch period and a data access period of the processor 11. In this case, during the instruction fetch period, SR
AM becomes the access target, and DRAM becomes the access target during the data access period.

[Variation 6] In each of the above embodiments, the processor 11 sets the memory type information as a criterion for the memory type determination circuit 12, but this may also be configured to be set from outside the processor IC 10. If the memory to be used is often determined or the memory to be used is determined in advance, the determination criteria may be fixedly held in the memory type determination circuit 12.

[Modification 7] Although the timing signal generation circuit 13 is provided independently for each different memory IC 20, the operation mode of one timing signal generation circuit 13 can be switched based on the determination result of the memory type determination circuit 12. It may also be something that has the ability to do something.

In particular, as in Modification 2 above, when the memory is of the same type but has different operating speeds, the type of control signal used is the same and only the timing is different, so this configuration reduces the circuit scale. can do.

[Modification 8] As a result of the determination in the memory type determination circuit 12, different timing signal generation circuits 13 may be activated, while the memories 1020 to be accessed may be overlapped. That is, in the embodiment shown in FIG. 2, the addresses output by the address multiplexer 15 may be limited to a portion of the addresses output by the processor 11.

The configuration of this embodiment is shown in the block diagram of FIG.

In the embodiment device of FIG. 10, the processor 11 is a PA
Outputs a 22-bit extended address consisting of O to PA21.

Also, as an access target memory IC A DRAM 20a and an SRAM 20b are provided.

Furthermore, this embodiment uses page mode, static column, and expanded high-speed access methods for DRAM.
An area where special access methods such as mode and nibble mode can be used is set in the DRAM 2Oa. That is, the memory area accessible by the processor 11 is the first memory area.
ro00 expressed in hexadecimal as shown in Figure 1
The area is from address 000J to address r2FFFFFJ, of which area 1 from address ro00000J to address roOFFFFJ corresponds to the SRAM 20b. Also, N
The area from address 0OOOOJ to address r2FFFFFJ corresponds to the DRAM 20a, of which N0
Area 2 from address OOOOJ to address rlFFFFFFJ is DRAM20a
Corresponds to the normal access mode of r20000oJ number f
[2FFFFFFJl area 3 is DRAM20
It is assumed that the high-speed access mode of a is supported.

Corresponding to the fact that the DRAM 20a is divided into two areas, the processor IC 10 includes a DRAM timing signal generation circuit 13a1 for speed, a DRAM timing signal generation circuit 13a2 for low speed, and an SRAM timing signal generation circuit 13b. It is provided.

In this case, from the processor 11 to the memory type determination circuit 12
The upper two bits of the signal PA2 of the internal address bus 14 are used as the identification information of the memory to be accessed which is input to the
0 and PA21 are supplied to the memory type determination circuit 12. The memory type determination circuit 12 determines the type of target memory by comparing type information preset by the processor 11 and address signals (PA20 and PA21) as identification information outputted by the processor 11.

The address actually output to the external address bus 21 is 20 bits of PAO-PA19. Therefore, even if address NFFFFFJ is accessed from address N0OOOOJ or address r2FFFFFJ is accessed from address r200000J, r2FFFFFJ of the same DRAM 20a is actually accessed.
Address rOFFFFFFJ will be accessed from address oooooOJ.

According to such a configuration, when the address space for storing data is set from address N0OOOOJ to address rIFFFFFJ, and the address space for storing instruction code of processor 11 is set from address r200000J to address r2FFFFFJ, processor 11 stores instructions. When pre-fetching or the like is performed, instructions stored in consecutive address spaces are read out, so the high-speed access of the DRAM can be effectively used, and the processing speed of the processor 11 can be improved. In other words, the remaining area in which instruction codes are stored can be used as a data space in the same DRAM, resulting in effective use of the DRAM.

[Modification 9] The timing signal generation circuit 13 may be configured to change the output timing of the Ill tll signal and end signal for memory control based on a control signal input from the outside. For example, timing signal generation circuit 1
If a memory whose operating speed is even slower than the target memory in step 3 is connected, a wait signal is input from the outside to delay the end of access. This has the effect of further increasing the types of memory that can be connected.

In the above embodiments, various explanations have been given regarding the case where the access target of the processor as the data processing yI device is the memory, but this also applies when the access target is not only the memory but also a data processing device such as a peripheral device or another processor. It is clear that the present invention is applicable to any case.

[Effects of the Invention] As explained above, according to the present invention, when connecting a plurality of access target devices of different types to a data processing device, no additional circuit is required or only a small amount of additional circuit is provided. Accordingly, it is possible to provide a bus control device that can realize high-speed access.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the invention, FIG. 2 is a block diagram of a second embodiment of the invention, and FIG. 3 shows a memory area according to the second embodiment. 4 is a diagram showing the relationship between internal and external addresses according to the second embodiment, FIGS. 5 to 8 are timing charts of the second embodiment gw, and FIGS. 9 and 10 are timing charts of the second embodiment gw. FIG. 11 is a block diagram showing a configuration according to another embodiment of the present invention, and FIG. 11 is a diagram showing a memory area of the embodiment device of FIG. 10. 10... Processor Ic, 11... Processor, 1
2...Memory type determination circuit, 13...Timing signal generation circuit, 14...Internal address bus, 15...
・Address φ multiplexer, 20...Memory IC,
21... External address bus, 22... Data bus, 23.24... Control signal line, 25... Gate circuit. Applicant's representative Patent attorney Takehiko Suzue 21st! il Figure 3 Figure 4 Processor address bus 001000 External address bus 1000WT Rt)Y Figure 5 RW (Write) External address bus 1000WT DY Figure 6 External address bus PAlo-PA19
PAO~PA9ROWOLIT DY Figure 7 External address bus PA10~PA19
PAO-PA9 Figure 8 Figure 9

Claims (11)

[Claims] (1) a data processing means and a plurality of access target means of different types to be accessed by the data processing means;
A common data bus and address bus provided between the data processing means and each of the access target means;
It has a control signal line corresponding to the type of each access target means, and when an access control signal is input from the data processing means, it converts this access control signal into a control signal suitable for the corresponding access target means. Determine the access target means to be accessed based on the plurality of control signal generation means supplied and the access target identification information output from the data processing means, and selectively select the control signal generation means corresponding to the access target means. 1. A bus control device comprising: means for determining the type of object to be activated. (2) The bus control device according to claim 1, wherein each of the plurality of control signal generating means is configured to supply an end signal to the data processing means after outputting the control signal. (3) The bus control device according to claim 2, wherein the output timing of the end signal output from each of the plurality of control signal generating means is controlled from the outside. (4) A common control signal line is provided to the plurality of control signal generating means, and a control signal from this control signal line is supplied in parallel to a gate circuit provided corresponding to each of the access target means, The bus according to claim 1, wherein the control signal from the control signal generating means is supplied to the corresponding access target means by selecting one of these gate circuits based on the determination result of the target type determining means. Control device. (5) The bus control device according to claim 1, wherein the object type determining means holds type information to be compared with the access object identification information output from the data processing means. (6) The bus control device according to claim 5, wherein the type information held by the object type determining means is set by the data processing means. (7) Claim 1, wherein the access target identification information is an address signal output from the data processing means.
The bus control device described in section. (8) The bus control device according to claim 1, wherein control signals output from the same control signal generating means are supplied to the plurality of access target means. (9) Address converting means for converting the address signal output from the data processing means into an address signal suitable for the plurality of access target means is provided, and the address converting means serves as the target type determining means and the control signal generating means. The bus control device according to claim 1, which is controlled by the output of. (10) The bus control device according to claim 1, wherein the control signals output from the plurality of control signal generating means are supplied to the same access target means. (11) The bus control device according to claim 1, wherein the access target means is a memory device.