JPH02150936A - Extension memory access system - Google Patents

Abstract

PURPOSE:To mount an extension memory having various access timings with difference types onto a slot exclusive for the extension memory by adding a memory type-based information holding means and an access timing information holding means to the extension memory. CONSTITUTION:An information processor has an exclusive slot for mounting an extension memory 110, and the memory 110 contains a memory type-based information holding means 111 and an access timing information holding means 113. When the memory 110 is mounted onto the exclusive slot of the information processor, the memory type-based information and the access timing information held by the means 111 and 113 respectively are fetched by a memory control circuit 120. Thus an interface means 121 of the circuit 120 switches the signal definition of the exclusive slot in accordance with the memory type-based information and produces the prescribed access timing in response to the access timing information. Thus it is possible to improve the reliability and to reduce the cost in an extension memory access system with use of an extension memory (memory card) having various access timings with different types.

Description

[Detailed Description of the Invention] [Summary] Regarding an extended memory access method for an information processing device in which extended memory can be mounted, it is possible to implement extended memory having different types of access timings on a dedicated slot for extended memory. In an information processing device that has a dedicated slot in which an expansion memory can be installed and a memory control circuit that controls writing to or reading from the expansion memory, the expansion memory includes a memory that holds memory type information. The memory control circuit includes a type information holding means and an access timing information holding means for holding the access timing information.
The device includes an interface means for taking in memory type information and access timing information from the installed expansion memory, switching the signal definition of the dedicated slot according to the memory type information, and generating a predetermined access timing according to the access timing information.

[Industrial application field]

The present invention relates to an extended memory access method for an information processing device that can be equipped with an extended memory.

[Conventional technology]

In conventional information processing devices, expansion memory dedicated slots provided to expand memory capacity usually have a bin assignment corresponding to one type of memory, and are optimized for the access timing of that memory.

Therefore, for example, dynamic R
It was impossible to install an expansion memory of a type different from the setting type, such as installing a memory card using static RAM as a backup application in a dedicated slot whose access timing is optimized for AM.

In addition, the system timing of an information processing device is designed to include the access timing of the expansion memory installed on the dedicated slot, so if the access timing of the expansion memory is slow, the throughput of the entire information processing device will decrease. There was a drawback.

On the other hand, a method has already been put into practical use that avoids the above-mentioned drawbacks by constructing an expanded memory system on a general-purpose bus and determining the optimal waiting time and control signal timing for each memory on each memory card.

[Problem to be solved by the invention]

However, this method of expanding memory on a general-purpose bus makes it possible to implement a wide variety of expansion memories, but the signals on the general-purpose bus are converted for memory access, and timing and other matters are all handled by the expansion memory (memory card). ) The control was complicated because it had to be controlled by the operator.

Therefore, as the number of installed memory cards increases, the control becomes more complex, and the cost of each memory card increases, further causing problems in reliability.

As described above, each method of memory expansion has its own problems, but in recent years, as information processing devices have become smaller, memory expansion is being replaced from using general-purpose buses to using built-in dedicated slots. Therefore, there is a need for a system that can accommodate a wide variety of memory cards in this dedicated slot and that can cope with the diversification of usage patterns of memory cards.

The present invention is in response to such demands, and an object of the present invention is to provide an expansion memory access method that makes it possible to mount expansion memories (memory cards) of different types with access timings on expansion memory dedicated slots. do.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, the information processing device has a dedicated slot in which an expansion memory 110 can be mounted, and a memory control circuit 120 that controls writing to or reading from the expansion memory.
Equipped with

The expanded memory 110 includes a memory type information holding unit 111 that holds the memory type information, and an access timing information holding unit 11 that holds the access timing information.
3.

The memory control circuit 120 is an interface that takes in memory type information and access timing information from the installed expanded memory, switches the signal definition of the dedicated slot according to the memory type information, and generates a predetermined access timing according to the access timing information. Means 121 is provided.

[For production]

When the expansion memory 110 is installed in the dedicated slot of the information processing device, each information held in the memory type information holding means 111 and the access timing information holding means 113 of the expansion memory (memory element) is transferred to the memory control circuit 120.
be taken in.

The interface means 121 of the memory control circuit 120 includes:
The signal definition of the dedicated slot can be switched according to the memory type information, and a predetermined access timing can be generated according to the access timing information.

That is, in the system of the present invention, the interface conditions are selected and set on the memory control circuit side in accordance with the various types of expansion memories to be installed, so that it is possible to mount various types of expansion memories in the same slot.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of an extended memory (memory card) according to the present invention.

In the figure, the memory card includes a memory type information holding unit 211 that holds memory type information, a register 212 that holds access timing information, a memory element 213,
It has a flip-flop 214 and gate circuits 215 and 216 for switching the chip selection signal C3-CARD from the register 212 to the memory element 213.

Chip selection signal C5-CARD is applied to flip-flop 2.
14, one input terminal of a gate circuit (OR) 215, and one inverting input terminal of a gate circuit (NAND) 216. flip flop 214
The output Q of is connected to the other input terminal of the gate circuit 215, and its output G is connected to the output enable terminal OE of the register 212.

Further, the output d is connected to the other inverting input terminal of the gate circuit 216, and the output d2 thereof is connected to the chip selection signal input terminal C3 of the memory element 213.

The memory type information holding unit 211 sends out a memory type signal a, and the register 212 sends out a signal indicating access timing information to the card data bus CDB. Note that the memory element 213 has the same configuration as the conventional one, so there is a card data bus CDB for data signals, a card address bus CAB for address signals, and a card address bus CAB for timing control signals (strobe signal 5TB) except for the chip selection signal C5-CARD. Details regarding the control bus will be omitted.

The operation of the extended memory (memory card) will be described below with reference to the time chart shown in FIG.

When the memory card is mounted, the memory type signal a is taken out and the chip selection signal C3-CAR is output at the first access.
D becomes active (“L (low level)”). At this time, the output d of the flip-flop 214 is rH (high level), and the chip selection signal C5-CARD is not sent to the memory element 213.

On the other hand, the output Q is "L" and the output enable terminal 0E (Gl) of the register 212 changes from "rH" to "L", so the contents of the register 212 (access timing information)
is output to the card data bus CDB.

After this access is completed, the chip selection signal C5-CARD
The flip-flop 214 is set at the rising edge of
The direction is rl, J, and Q is "HJ. Therefore, in the second and subsequent accesses, the output of register 212 is disabled, and the chip selection signal C3-CARD (Gz)
is input to the memory element 213, and the memory element 213 is accessed.

In this way, the register 212 of the memory card is configured such that the output becomes valid only when the chip selection signal C5-CARD is accessed for the first time.

FIG. 4 is a block diagram showing the configuration of an embodiment of a memory control circuit according to the present invention. Note that this embodiment shows an interface section of a memory control circuit, and here, a static ROM and a dynamic RAM (DRAM) are shown.
The configuration is compatible with the implementation of two types of memory cards.

In the figure, the DRAM control section (Min) 421
, ROM control unit (M!,) 422, decoder 423 for chip selection signal, shift register 424 for memory card register access, gate circuit 425,4
26, 427 and a flip-flop 428, gate circuits 431, 432 for selecting each control section, a card interface circuit 433 for assigning bins to dedicated slots in which memory cards are mounted, and decoders 434, 435 for memory type signals a.

In this embodiment, the memory type signal a is 1 bit) (rH
J or “L”) is sufficient, so the decoder 434
is configured to take out two outputs of different logic, and the decoder 435 is configured to pass the memory type signal a as is.

System address bus SAB and card data bus C
The system data bus SDB corresponding to DB has DRA
M control section 421 and ROM control section 4
22 is connected to the system address bus SAB, and a decoder 423 is further connected to the system address bus SAB.

The output of the decoder 423 is the gate circuit (OR) 425
One inverting input terminal and gate circuit (AND) 43
1,432 negative inverting input terminals. The output G of the gate circuit 425 is connected to the input terminal of the shift register 424, and its output Q1 is connected to the gate circuit (NAND
) 426. 427, the output d4 is connected to the other input terminal of the gate circuit 426 and the other inverting input terminal of the gate circuit 425, and the output d is connected to the other input terminal of the gate circuit 427. Connected.

The output d4 of the gate circuit 426 is connected to the card interface circuit 433 and each control section 421, 422. Output d of gate circuit 427.

is connected to the control terminal of the flip-flop 428, and its output d is connected to the second inverting input terminal of the card interface circuit 433 and the gate circuits 431 and 432. Clock signal CLK is connected to the shift register 424 and the clock terminal of each control section 421, 422.

The memory type signal a is connected to each third inverting input terminal of the gate circuits 431 and 432 via the decoder 434,
The respective outputs Gb and G'r are the respective control sections 421 and 4.
22.

For each address and strobe signal output from the DRAM control section 421 and ROM control section 422, the signal from the corresponding control section is selected by the card interface circuit 433, and the predetermined chip selection signal C3-CARD and strobe signal They are connected to the control bus and card address bus CAB as STB and address signals, respectively.

The operation of the interface section of the memory control circuit will be described below with reference to the time chart shown in FIG.

When the memory card is mounted and the first access is made, when the output of the decoder 423 becomes "L", the gate circuit 425
The output G3 of the shift register 424 and the output Q1 of the shift register 424 are sequentially r
Then, the output Qa+65 becomes "L", and Q
The output d of the gate circuit 426 is the NAND of l and d4.
4 is the memory card register access signal Reg-C
5 and is sent out as a chip selection signal C3-CARD via the card interface circuit 433.

When the output d4 of the shift register 424 becomes "L" and the register access signal Reg-CS rises to complete the first access, the output direction is fed back to the output G of the gate circuit 425.

(input of shift register 424) is always “H”,
Register access signal Reg-C5 does not become active ('LJ) in subsequent accesses.

On the other hand, when the register access signal Reg-C5 is active, the output d of the gate circuit 427 is "L" and the output d of the flip 10 tube 428 is rH.

Therefore, the output of the decoder 423 is not sent to each control section 421, 422.

Furthermore, when the access to the register 212 of the memory card is completed, the flip-flop 428 is set at the rising edge of the output Gs of the gate circuit 427, and the output d becomes "L".
The output of the decoder 423 is 100 each control section 4.
The inputs to 21 and 422 are enabled. Therefore, the outputs that become active from the next time onwards will be sent to each control unit 421, 42 as a card selection signal CARD-set.
2 is entered. Note that the memory type signal a is input to the gate circuits 431 and 432 via the decoder 434, and this card selection signal CARD-sel is sent to the DRAM control unit 421 when the memory type signal a is "L". , rH, the ROM control section 422
are input respectively.

By the way, the access timing information sent to the card data bus CDB when the register 212 of the memory card is accessed is transmitted to the system data bus S of the memory control circuit.
It is taken into each control unit via the DB and becomes valid in the control unit according to the memory type signal a.
Its output is taken out via card interface circuit 433. Note that the chip selection signal C3-CARD is
According to the output d of the flip-flop 428, the DRAM control unit 4 receives the register access signal Reg-CS.
21 RAS signal or ROM control section 422
The signal is switched to the C3 signal.

In this way, the corresponding DRAM control section 421 or ROM control section 422 is selected depending on the memory type of the memory card to be mounted, and its output becomes an address signal in accordance with the access timing information sent from the memory card side. and each strobe signal, and the timing for outputting the memory access end signal ACK is set.

FIG. 6 is a block diagram showing the configuration of one embodiment of the DRAM control section.

In the figure, the DRAM control unit (MID) includes a flip-flop 6 that latches access timing information.
01. Depending on the latched access timing, the RAS signal is used as the strobe signal used for reading the row address, and the CA signal is used as the strobe signal used for reading the column address.
Flip-flops 611 and 612 that generate the S signal and the memory access end signal ACK, a gate circuit 613,
shift register 614 and selectors 615, 616,
It includes latch circuits 621 and 622 that latch address information on the system address bus SAB, and others.

The register access signal Reg-C5 is connected to the control terminal of the flip-flop 601, the system data bus SDB is connected to the input terminal, and the output Q is connected to the selector 6.
15,616 selection control terminals.

Card selection signal CAI? D-scl is connected to the input terminal of the flip-flop 611, the input terminal S of the shift register 614, and the latch enable terminals LE of latch circuits 621 and 622 connected to the system address bus SAB. The output Q of the flip-flop 611 is connected to one input terminal of a gate circuit (NAND) 613 and the input terminal of the flip-flop 612, and the output d of the flip-flop 612 is connected to the other input terminal of the gate circuit 613. The output (clear signal) CLR is connected to the clear terminal C of the shift register 614. Clock signal CLK is connected to each clock terminal of flip-flop processors 11 and 612 and shift register 614.

The output Q of the shift register 614 is taken out as a RAS signal, the output Qb and its inverted signal are sent to the output enable terminals OE of the latch circuits 622 and 621, respectively, and the outputs Qc and Q are sent to the A and B terminals of the selector 615. Outputs Q, ,Q, are connected to the A and B terminals of selector 616. The output Y of the selector 615 is taken out as a CAS signal, and the inverted output ■ of the selector 616 is taken out as a memory access end signal ACK. Each output of the latch circuits '621 and 622 is an address signal MPXA.
is extracted as.

The operation of the DRAM control section will be described below with reference to the time chart shown in FIG.

Here, the access timing information of the mounted memory card is taken in from the card data bus CDB via the system data bus SDB at the time of first access (read time). The flip-flop 601 receives a register access signal R for accessing the register 212 of the memory card.
The system data bus SDB is latched at the rising edge of eg-CS, and its output becomes a selection control signal for selectors 615 and 616.

On the other hand, each time the card selection signal CARD-set becomes active after the register 212 is accessed, the shift register 614 outputs the RAS signal and the output enable signals MPX and CA of the latch circuits 621 and 622 at a predetermined timing.
Generates S signal and memory access end signal ACK. Note that the two CAS signals and the memory access end signal ACK, which have different timings, are sent to the selectors 615 and 6.
16 are selected according to the output of the flip-flop 601, respectively. Here, when the output of the flip-flop 601 is "L", the input A appears at the output Y (Y), and r
Suppose that when H, input B appears at output Y (Y).

Therefore, when the system data bus SDB is "H", the output Qc of the shift register 614 is selectively output from the selector 615 as a CAS signal, and the selector 616
The output Q of the shift register 614 is selectively outputted as the memory access end signal ACK.

FIG. 7(1) shows a case where 5 DB=rHJ and is suitable for a DRAM with fast access timing. Note that the card selection signal CARD-sel is reset in response to the memory access end signal ACK delayed by 5 clocks from the RAS signal, and the RAS signal and CA
The S signal, memory access end signal ACK, and latch enable signal MPX are reset.

FIG. 7(2) shows a case where 5DB=rLJ and is suitable for a DRAM with slow access timing.

That is, when the system data bus SDB is "L", the output Q of the shift register 614 is output from the selector 615.
, is selectively outputted as a CAS signal delayed by one clock, and the output Q of the shift register 614 is outputted from the selector 616 by 2.
It is selectively outputted as a slow clock memory access end signal ACK.

Note that each signal is similarly reset in response to the memory access end signal ACK delayed by a macro clock from the RAS signal.

In this way, the DRAM control section can perform timing control corresponding to the access timing information (SDB) obtained from the memory card. Also, R.O.
The same applies to the M control section.

〔Effect of the invention〕

As described above, according to the present invention, the memory control device (system) side that controls the extended memory (memory card) according to the memory type and access timing information sent out when the extended memory (memory card) is mounted. Since the corresponding interface conditions are set, it becomes possible to implement extended memories of different types and access timings.

In other words, the extended memory only needs to be configured so that it can hold its memory type information and access timing information and send them out at the time of implementation, and there is no need for a complicated control system. cost can be realized.

In addition, since differences between expansion memories are automatically absorbed on the memory control device side, it is possible to install many types of expansion memories in the same slot, making it easy to flexibly respond to diversifying usage patterns. Therefore, it is extremely useful in practice.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing the configuration of an embodiment of an extended memory, Fig. 3 is a time chart explaining the operation of the extended memory (memory card), and Fig. 4 is a memory FIG. 5 is a block diagram showing the configuration of an embodiment of the control circuit (interface section); FIG. 5 is a time chart illustrating the operation of the main parts of the interface section; FIG. FIG. 7 is a time chart explaining the operation of the DRAM control section. In the figure, 110 is an expansion memory, 111 is a memory type information holding means, 113 is an access timing information holding means, 120 is a memory control circuit, 121 is an interface means, 211 is a memory type information holding unit, 212 is a register, and 213 is a memory. 214 is a flip-flop, 215.216 is a gate circuit, 421 is a DRAM control section (MID), 422 is a ROM control section (Mll), 423.434, 4
35 is a decoder, 424 is a shift register, 425, 426, 427, 431, 432 are gate circuits, 428 is a flip-flop, and 433 is a card interface circuit. Embodiment block diagram of expansion memory Figure 2 Time chart explaining the operation of expansion memory 5iR3 Figure Block diagram of the principle of the present invention Figure 1 Interface part 1! Fig. 5 Time chart explaining the operation of the DRAM control section Example block national policy diagram of the DRAM control section LK]Llf''L Time chart explaining the operation of the DRAM control section Fig. 5

Claims (1)

[Claims] (1) In an information processing device that has a dedicated slot in which an expansion memory (110) can be mounted and is equipped with a memory control circuit (120) that controls writing to or reading from the expansion memory, the expansion memory (110) , a memory type information holding means (111) for holding the memory type information, and an access timing information holding means (113) for holding the access timing information, the memory control circuit (1)
20), an interface that takes in the memory type information and access timing information from the installed expanded memory, switches the signal definition of the dedicated slot according to the memory type information, and generates a predetermined access timing according to the access timing information. An extended memory access method characterized by comprising means (121).