JPS5856276A - Controlling system of storage device - Google Patents

Abstract

PURPOSE:To obtain a storage device having the desired performance, by providing N types of control circuits into a memory access controller in accordance with N types of main storage main bodies and selecting the corresponding control circuit with the performance informing signal given from the storage main body. CONSTITUTION:The memory access signals TO given from an external device are distributed within a memory access controller U1 to control circuits C1-Cn. Thus signals T1-TN are produced to control N types of main storage main bodies having different types of time properties and storage capacities. A control signal selecting circuit CS selects exclusively a suited one of the signals T1- T2 with the performance recognizig signal I1 given from a main storage main body U2 and supplies it to the main body U2. In such way, a storage device which can have different types of performance in response to the desire is obtained with just one memory access controller.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an 1ljU starvation method for a storage device, and in particular, to a 1ljU starvation method for a storage device, and in particular to a 1ljU starvation method for a storage device, N types of main if self-memory tree-dependent dd1 storage devices with different access time-cycle time and/or m11ft response amount are used. The controller is configured to have one memory access control device for one main memory main body, and the main memory main body that can be controlled by the memory access controller a is It was limited to one. The above-mentioned NjlJ system has the drawback that the main memory main body has only one performance such as access time and cycle time.

An object of the present invention is to provide a control method that enables a single memory access control device to control the main body of N types of devices with different performances such as access time and cycle time. It is on offer.

To this end, the present invention provides a memory access system that controls a main body section used for storing processing programs and data in an information processing system, and memory access from an external processing device to the main body section. In a storage device consisting of a control device, temporal characteristics such as access time and cycle time and /'l! ! In the memory access control device, N types of control circuits configured to be able to control the respective main storage main units corresponding to the N types of main storage main units having different storage capacities t or t are provided in the memory access control device. The Lord, liL, which has been implemented in reality as well as profiting from it! The unique main unit sends a signal to the memory access control device to notify the temporal characteristics and/or capacity of the main memory main unit, thereby causing the memory access control device to correspond to the main memory main unit. The present invention will be explained with reference to the drawings. , l is the memory access control device f[J□, 2 is the main memory main unit U, , a-1-1-N&''1: Control circuits 01 to 081 are the control I4I double number selection circuit OS, S is the input information Conversion circuit A., 6 is an output information conversion circuit Al that includes a starting data register, To is a memory access signal from an external device, Tl~'rN is the main 6 Hakurei main body control number, and i engineering is the main control number. Memory main unit identification signal, 12 is the main memory main unit control signal selected by the control number selection circuit 1, M8
is the input information conversion circuit control signal, i4 is the output information conversion circuit control signal, DI is the write data and address from the external device, D is the write data and address that has been converted into the input information conversion circuit 5, and D8 is the main The bladder evacuation data D from the storage main unit 2 is output data from the indulgence data register in the output information conversion circuit 6.

Controls 1mM8-1 to B-N are provided corresponding to N types of main memory main units, and the main memory main unit U shown in the figure is one of the N types of main memory main units mounted. Q. The operation of the embodiment is as follows: 0. Memory access signal T from an external device. is distributed among the control circuits 01 to ON in the memory access control device U0,
Double M T 1-T for controlling N main memory main units
N i' M control cycle '18 C1~ON "" is created. The control signal selection circuit O8 selects a control signal from T to TN to control the main memory main body U2 to the main memory main body identification signal (performance recognition signal) 11 sent out from the main memory main body C8. It is uniquely selected and sent to the main memory unit U as a control signal i. In addition.

The main memory main body identification signal i1 is based on the temporal characteristics (such as access time and cycle time) of the main memory main body.
This is to notify the control signal selection circuit 4 of information such as performance (performance) and/or capacity.

In addition, the processing data and address D1 from the external device are
The input information conversion circuit signal 1. which is input to the input information conversion circuit Ao and selected by the main memory main body control signal i1. As a result, the main source is converted to match the control form of the main body part UB and sent to the main memory main body part U2 as fL,,Ds&〇Meanwhile, the bladder ejection data from the main memory main body part U is Regarding D8, since the access time generally differs depending on the main memory main body part of the Ni class, the output information conversion circuit control signal 9i4 selected in the main H white main body part d1λ separate signal i function is used to The output data D8 is set at different timings in the head-out data register (not shown) in the output information conversion circuit 6.The data set in the head-out data register (not shown) is sent to the outside of the access source as the output data D8. sent to the device.

As described above, there are N types of main memory main body sections OB, and the main memory main body section identification signal 1B indicates a different state for each type, and the control signal selection circuit O8 selects the control signals Tl-Tn.
Since any one of the signals marked with 211 is selected and supplied to the main memory main body U2, it is possible to operate satisfactorily no matter which main memory main body U2 is mounted (connected, wired). It is possible.

According to the present invention, in one memory access control device,
N types of control circuits are provided corresponding to the N types of main memory main body parts, and control circuits corresponding to the main memory main body part are selected from among the 198 types of control circuits in response to the performance notification information sent from the above-mentioned unique main body area. A circuit for selecting a circuit is provided, and any one of the N types of main memory main units can be connected, so it is possible to configure memory devices with completely different performances as required.

[Brief explanation of drawings]

The figure shows a block diagram of a storage device according to an embodiment of the present invention. In the figure, l is a memory access control device, 2 is a main memory main unit, 8-1 to 13-N are control circuits, 4 is a control signal selection circuit, 5 is an input information conversion circuit, and 6 is an output information @i conversion circuit,
l is the main memory body identification code.

Claims (1)

[Claims] A main memory main unit used for storing processing programs and data in an information processing system, and a memory access 1&1 side for accessing the main memory main unit from an external processing device. IJω of access time, cycle time, etc. in j device and h own unique device
Intermediate TP! N that differs in gender and/or 6 meaning valley foot
There are N types of 1i configured such that the corresponding main memory body is the nth on the N side, corresponding to the main memory body of the type.
The entire li1 circuit is created in the memory access control device, and the memory access 1 "1" is stored in the main memory main body which is actually implemented in the main memory main body. The temporal characteristics of the above memory access system (incorporated) can be achieved by sending out the name of the sake that notifies each company.
FIjIJ corresponding to the main unit in the device
The main feature is that the wholesale circuit can be selected.The main feature is the device control system.