JPS6353636A - Buffer controller - Google Patents

Abstract

PURPOSE:To obtain a buffer controller executing an efficient economical data transfer making suitably variable the size of a buffer memory in accordance with the input/output speed of the data. CONSTITUTION:At the time of inputting the data, the data are inputted from a communication line 1 to an address designated by an ending pointer, and it is checked whether of not the address is the final address of buffer memories 51-54. When the address is the final address and the memory of the next sequence is used, a new memory 55 is prepared, inserted to the front of a next memory 53, the leading address is set to the ending pointer and processing is completed. When the data are read and supplied to an auxiliary memory device 3, it is checked whether or not the address designated by the leading pointer and the ending pointer is equal, when the address is not equal, the data are read, supplied to the device 3, and when the address is the final address, the leading address of the memory of the next sequence is designated to the leading pointer and the processing is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides data input at a certain speed from a first device such as a communication line to a second device such as a storage device via a buffer memory. The present invention relates to a buffer control device for feeding at different speeds.

(Prior Art) When relatively long data is sequentially supplied from a first device to a second device, specifically, when data sequentially input from a communication line etc. is sequentially stored on a magnetic disk etc. There is no particular problem when the speed at which data is stored on the magnetic disk is the same as the speed at which data is input from the communication line, but the two speeds are generally different.If the two speeds are different like this, the data input from the communication line Buffer memory is used to quickly and efficiently supply data to magnetic disks.Then, data input from a communication line is stored in Batza memory and then processed according to the storage speed of the magnetic disk. Data is supplied from the buffer memory to the magnetic disk at the same speed.

In a Luhasso control device that supplies data input from a first device to a second device via a buffer memory, conventionally, the buffer memory has a fixed storage capacity. A wrap-around configuration is adopted in which the user specifies the information.

In controlling such a buffer memory, if the speed of data input from the first device is faster than the speed of data supplied to the second device, the end pointer will change as shown in FIG. 5(b). The process progresses from the end of the buffer memory past the beginning to just before the start pointer, and the buffer memory is almost occupied by data, and there is no space to input new data, so input must be stopped until the buffer memory becomes empty. It will stop happening.

Conversely, if the speed of data input from the first device is slower than the speed of data supplied to the second device,
As shown in Figure 5 (C), the first pointer advances to just before the end pointer and the buffer memory becomes almost empty, so you have to wait until data is accumulated in the buffer memory before supplying data to the second device. It will stop happening.

[Problem that the invention seeks to solve]

''As described above, in conventional devices in which the capacity of the buffer memory is fixed, the buffer memory capacity is reduced depending on the difference between the speed of data input from the first device and the speed of data supplied to the second device. If there is not enough memory, or if there is too much memory, data cannot be transferred efficiently, and if there is too much, buffer memory is wasted and uneconomical. There's a problem.

The present invention has been made in view of item 1, and its purpose is to appropriately vary the size of the buffer memory according to the data input/output speed, thereby achieving efficient and economical data transfer. An object of the present invention is to provide a buffer control device that can perform the following steps.

[Failure to solve the problem]

In order to solve the above-mentioned problems, the present invention has a plurality of buffer memories that store data supplied from the first device, are arranged in a ring in a predetermined order, and input data from the first device. When data from the first device is input to the buffer memory at the input address specified by the input address pointer, this input address is the last input address of the buffer memory. If the address is correct, set the next address to the input address pointer, and if it is the last address, check whether the buffer memory arranged in the next order is already in use. If the buffer memory is not in use, the start address of the buffer memory is set to the input address pointer, and if it is in use, a new buffer memory is set before the buffer memory in use in the circular order. , an input address pointer setting means for setting the start address of this new buffer memory as an input address pointer, and a read address pointer for specifying a read address of the buffer memory from which data stored in the buffer memory is read to a second device. When data is read from the buffer memory at the read address specified by the read address pointer and supplied to the second device, if this read address is not the last address of the buffer memory, the next address is read and the address pointer is and, if it is the last address, sets the first address of the buffer memory arranged in the next order as the read address pointer.

[Effect]

In the buffer control device of the present invention, when data is input from a first device to an input address designated by an input address pointer of a plurality of buffer memories arranged circularly in a predetermined order, this input address is the last one of the buffer memories. If the address is, it is checked whether the buffer memory arranged in the next order is already in use or not, and if it is not in use, the start address of the buffer memory is set to the input address pointer, If it is in use, a new buffer memory is added and set before the buffer memory in use in the circular order, the start address of this new buffer memory is set to the input address pointer, and the read address is set. When data is read from the buffer memory at the read address specified by the pointer and supplied to the second device, if this read address is not the last address of the buffer memory, the next address is set to the read address pointer, and the last address is set to the read address pointer. , the first address of the buffer memory arranged in the next order is set as the read address pointer.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram of a buffer control device according to an embodiment of the present invention. This embodiment uses a buffer memory device 5 to transfer data between a communication line 1 that is a first device and an auxiliary storage device 3 that is a second device, and a computer (not shown) based on a data transfer control program 7. This is carried out under the control of In this case, the auxiliary storage bag W3 is, for example, a magnetic disk, a Fronbi disk, etc., but is not limited to this, and the second device may be any other device other than the storage device. be. Similarly, the first device is not limited to the communication line 1 either.

The buffer memory device 5 is composed of a plurality of buffer memories 51, 52, 53, and 54, as shown in FIG. Buffer memories 51, 52, 53, and 54 each have a predetermined storage capacity. In addition, buffer memories 51, 52,
53, 54 are in a predetermined order, that is, the buffer memory 51 is next followed by the buffer memory 52 . Buffer memory 52 is followed by buffer memory 53 . Buffer memory 53
The buffer memories 54 are arranged in a predetermined order, and the last buffer memory 54 is followed by the first buffer memory 51, so that they are connected in a circular manner. There is.

Data is input from the communication line 1 and stored in the buffer memory device 5, which is composed of a plurality of buffer memories 51 to 54, and the stored data is read out from the buffer memory device 5 and stored in the auxiliary storage device. In FIG. 2, the address to which data is input from the communication line 1 is specified by the end pointer, and the buffer is controlled so that the data is supplied to the auxiliary storage device 3. The address from which data is read from the memory device 5 is specified by the head pointer. In the buffer memory device 5 in FIG. 2, the shaded area is the area where data input from the communication line 1 has already been stored, and the blank area that is not shaded is the area where data has not yet been stored. This is an area where there is no such thing.

Now, when I try to input data from communication line 1, the second
In the figure, the data is stored at the beginning of the blank part of the buffer memory 52 at the address specified by the end pointer. When data storage is completed, the end pointer is incremented, and the address next to the current address is set in the end pointer.

In addition, the data stored at the beginning of the diagonally shaded portion of the expansion memory 53 at the address designated by the beginning pointer in FIG. 2 is read out and stored in the auxiliary storage device 3. When data reading is completed, the start pointer is incremented, and the end pointer is set to the next address from the current address.

In this way, when the data at the address specified by the start pointer is sequentially read out and supplied to the auxiliary storage device 3, the start pointer sequentially erases the shaded areas of the buffer memory 53 in FIG. , and advances to the last address in the buffer memory 53. When this last address is also specified and read with the start pointer, the start address of the buffer memory 54 in the next order is set as the start pointer, and from then on, the start pointer is specified in this way. The data stored in the buffer memory 54 is sequentially read out from the first address.

Furthermore, when all the data in the buffer memory 54 is read out, the start address of the first buffer memory 51 in the next rank is set as the start pointer, and the data in this buffer memory 51 is read out in sequence.

Furthermore, when data is sequentially input to the address specified by the end pointer, the end pointer moves so as to sequentially change the blank part of the buffer memory 52 to the shaded part in FIG. Proceed to the address. If this last address is also specified and read with the end pointer, the end pointer will be set to the start address of the buffer memory 53 in the next order, but this next As shown in FIG. 2, if the buffer memory 53 in the order of A new buffer memory 55 is inserted in front of the buffer memory 53 inside as shown by the two-dot chain line, and the start address of this inserted new buffer memory 55 is set to the end pointer. The next data is input to the starting address of the new buffer memory 55. Furthermore, if the buffer memory 53 is not in use, the start address of this buffer memory 53 is set to the end pointer, and from then on, data is input sequentially from the start address of the buffer memory 53 specified by the end pointer. It will be done. Furthermore, when all data is input to the buffer memory 53, if the first buffer memory 54 in the next order is not in use, the start address of this buffer memory 54 is set as the end pointer, and this Data is sequentially input to the buffer memory 54.

Next, the operation will be explained according to the flowcharts shown in FIGS. 3 and 4.

First, the operation when data is input from the communication line 1 to the buffer memory device w5 will be explained with reference to FIG.

First, when inputting data, input data from communication line 1 to the address specified by the end pointer.Step 1
10) Check whether the address specified by the end pointer is the last address of the buffer memories 51 to 54 (step 120).

If it is not the last address of the buffer memory, the end pointer is advanced by one to the next address and the process ends (step 130).

If it is the last address of the buffer memory, it is checked whether the next buffer memory is in use (step 140). If it is not in use, the start address of the buffer memory that is not in use is set as the end pointer, and the process ends (step 150).

If the next buffer memory is in use, allocate memory and create a new buffer memory, and place this new buffer memory in front of the next buffer memory that is currently in use. , for example, before the buffer memory 53, such as the buffer memory 55 shown in FIG. 2 (steps 160 and 170). Then, the start address of this newly inserted buffer memory is set as the end pointer, and the process ends (step 180).

Next, the operation when reading data from the buffer memory and supplying it to the auxiliary storage device 3 will be described with reference to FIG.

First, in this process, it is checked whether the addresses specified by the start pointer and the end pointer are equal (step 210). If both addresses are equal,
An error occurs and the process ends (step 220). Note that at this time, the buffer memory device 5 is empty.

If the two addresses are not equal, the data is read from the buffer memory at the address specified by the head pointer and supplied to the auxiliary storage device 3 (step 230). Then, it is checked whether the address specified by the head pointer is the last address of the buffer memory (step 240).

If it is not the last address, the start pointer is advanced by one to the next address and the process ends (step 250).
).

If it is the last address of the buffer memory, the start address of the next buffer memory is designated as the start pointer, and the process ends (step 260).

〔Effect of the invention〕

As explained above, according to the present invention, when data is input from the first device to the input address specified by the input address pointer, if this input address is the last address of the buffer memory, the next Check whether the buffer memory arranged in the order is already in use, and if it is in use, add a new buffer memory in front of the buffer memory in use in the circular order. Since the start address of this new buffer memory is set in the input address pointer, the speed of data manually input from the first device is faster than the speed of data supplied to the second device, and the buffer When the memory is occupied by input data, a new buffer memory is added, which prevents the buffer memory from running out and allows the optimal capacity of the buffer memory to be operated according to the data input/output speed. configurable, allowing for efficient and economical data transfer.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a buffer control device according to an embodiment of the present invention, FIG. 2 is a block diagram of a buffer memory device used in the device of FIG. 1, and FIGS. 3 and 4 are A flowchart showing the operation of the device shown in FIG. 1 at the time of data input and data output, respectively. FIG. 5 is a diagram for explaining the operation of the conventional buffer control device. 1...Communication line, 3...Auxiliary storage device, 5...Buffer memory device, 7...Data transfer control program, 51-54
...Buffer memory, 55...This is a new buffer memory. Figure 3 Figure 4

Claims (1)

[Claims] Accumulating data supplied from the first device, and
a plurality of buffer memories arranged in a ring in a predetermined order; an input address pointer that designates an input address of the buffer memory into which data from a first device is input; and an input address pointer that designates an input address of the buffer memory that inputs data from a first device; When data from the first device is input to the buffer memory, if this input address is not the last address of the buffer memory, the next address is set to the input address pointer, and if it is the last address, the next address is set. It is checked whether the buffer memory arranged in the order of input address pointer setting means for additionally setting a new buffer memory before the in-use buffer memory in the circular order, and setting the start address of this new buffer memory as an input address pointer; A read address pointer that specifies the read address of the buffer memory at which data is to be read out to the second device, and when data is read from the buffer memory at the read address specified by the read address pointer and supplied to the second device. , if this read address is not the last address of the buffer memory, the next address is set to the read address pointer, and if it is the last address, the first address of the buffer memory arranged in the next order is set as the read address. A buffer control device comprising: read address pointer setting means for setting a pointer.