JPH04148241A - Microcomputer development supporting device - Google Patents

Abstract

PURPOSE:To deal with a high-speed microcomputer by providing a circuit which delays falsely the start of a control signal by the prescribed number of clocks and the circuit which inputs a selecting signal and delays an external response input signal by the prescribed number of the clocks. CONSTITUTION:A delay circuit 133 inputs the selecting signal 111 outputted from a detection circuit 102, and delays falsely the start of the control signal 134 for an external input/output device 104 by the prescribed number of the clocks. A response input signal delay circuit 151 inputs a clock signal 110 and an input/output control signal, and makes a response input signal forcedly into 0 at timing necessary for delaying the input/output operation of a CPU 101 by one clock portion. After that, it inputs the selecting signal 111, and outputs an internal response input signal 152 in the case of '0' and the external response signal 153 in the case of '1' to the response input signal 150. Thus, development can be supported in accordance with the development of the high-speed microcomputer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input/output device for a microcomputer development support device.

[Conventional technology]

Microcomputer development support equipment (hereinafter simply referred to as
In order to support the development of the software and hardware to be developed, the support device is a built-in program that is executed when the execution of the software to be developed is interrupted, and the software to be developed is temporarily transferred to an external device. The support device has an internal input/output device such as a built-in memory so that it can be executed virtually without an input/output device (hereinafter referred to as an external input/output device).

General means for selecting the internal input/output device and external input/output device in a conventional support device will be explained with reference to the block diagram of FIG. 5 and the timing diagram of FIG. 6.

In FIG. 5, 200 is the main body of the support device.

101 is a microcomputer to be developed or an emulation CPU (hereinafter simply referred to as CPU).

102 is a detection circuit that detects whether the CPU 101 selects either an external or internal input/output device, 103 is an internal input/output device within the support device, and 1.4 is an external input/output device connected to the outside of the support device. It is an output device.

111 is a selection signal output from the detection circuit 102 for selecting either an external or internal input/output device.

120 is an address signal output from CPUl0I, 1
21 is an internal address buffer that supplies the address signal 120 to the internal input/output device 103; 122 is the supplied internal address signal; 123 is the internal address buffer that supplies the address signal 120 to the internal input/output device 103;
An external address buffer 124 is a supplied external address signal.

Reference numeral 130 indicates a plurality of control signals output from CUPlol to the input/output device, and each CPU has a unique signal.
In general, reading from memory, writing to memory,
It consists of four control signals for reading from the IO device and writing to the IO device.

Here, in order to simplify the explanation, two control signals for controlling reading from the memory and writing to the memory will be explained.

231 is an internal control signal generation circuit that supplies the control signal 130 to the internal input/output device 103 when the selection signal 111 is an internal selection, and 132 is the supplied internal control signal.

233 is an external control signal generation circuit that supplies the control signal 130 to the external input/output device when the selection signal 111 is external selection, and 144 is the supplied external control signal.

140 is a data bus through which the CPtJ 101 inputs and outputs data to and from input/output devices.

141 is an internal data bus buffer that connects the internal input/output device 103 and the data bus 140 when the selection signal 111 is internal selection; 142 is an internal data bus buffer that connects the internal input/output device 103 and the data bus 140;
4 internal data bus.

143 is an external data bus buffer that connects the external input/output device 104 and the data bus 140 when the selection signal 111 is external selection; 144 is an external data bus buffer that connects the external input/output device 104
4 is an external data bus connected to the external data bus.

250 is a response input signal to the CPU 101, 251
152 is a response signal selection circuit which selects a response signal from the internal input/output device 103 when the selection signal 111 specifies internal, and selects a response signal from the external input/output device 104 when the selection signal 111 specifies external; internal response signal, 15
3 is an external response signal to be selected.

In addition, in a normal support device, the above 124.134.144.
Each signal of 153 is taken out to the outside of the support device through a probe-shaped connector having the same shape and arrangement as the target CPU package, and can be attached to the circuit board Lj[i to be developed.

FIG. 6 shows four types of timing in the configuration of FIG. 5: memory read and write operations for external input/output devices, and memory write and read operations for internal input/output devices.

301 is a memory readout for an external input/output device;
02 is writing to memory for internal input/output device, 3
03 is writing to memory for external input/output device, 3
04 is a period for reading from memory for the internal input/output device. 11° is a clock signal input to CPUl0I. 232-1 is an internal memory read control signal, and 232-2 is an internal memory write control signal.
234-1 corresponds to an external memory read control signal, 2
34-2 is an external memory write control signal and corresponds to 234.

The selection signal 111 selects the outside when the output is "1'°," and selects the inside when the output is "0".
34-1.234-2 requests an input/output operation when the output is "1", and the response input signal 250.15
2.153 assumes that the operation of the input/output device is completed when the output is "1°".

In the case of CPU10I, which is the object of the present invention, when reading the memory contents to -ffi, the address signal 120 is output, and after the time when the signal is considered stable externally, the memory read control signal 130-1 is output. Output.

It then waits until the response signal becomes valid, at which point the CP
It is determined that the contents of the U data bus have been determined, and the contents are taken into the CPU to complete the read operation.

Periods 301 and 304 in FIG. 6 are the operation portion.

Similarly, when writing to memory, the address signal 120 is output, the data to be written is further output to the data bus 140, and after the time when the signal is deemed stable externally, the memory write control signal 130-2 is output. Output.

Thereafter, it waits until the response signal becomes valid, and at that point it is assumed that writing to the memory has been completed and the write operation ends.

The periods 302 and 303 in FIG. 6 are the operation portion.

In FIG. 6, for ease of explanation, the CPU 101 will be described as a representative CPU that operates at the timing described later.

CPU101 performs one input/output operation with four clocks, and when performing a memory read operation, it outputs the address signal 120 on the first clock, outputs the memory read control signal 130-1 on the next clock, and outputs the memory read control signal 130-1 on the fourth clock. The response input signal 250 is evaluated at the rising edge of the clock, and if valid, the contents of the data bus 140 are taken into the CPU and the memory read control signal 130-1 is terminated.

The address signal 120 is held during the fourth tarok.

If the response input signal 250 is not valid, repeat the third clock state.

When memory writing is in operation, the data to be written is output to the data bus 140 at the same time as the address signal 120 is output at the first clock, and that value is held during the write operation. It is assumed that the operation is performed at the same timing as the memory read operation except for outputting the write control signal 130-1.

Next, specific operations will be explained using FIGS. 5 and 6.

First, the detection circuit 102 receives the contents of the address signal 120 and outputs it at the timing of the selection signal 111.

As shown in FIG. 6, the signal 111 is determined after a time delay required for detection from the rising edge of the first clock.

Here, the selection signal 111 needs to be determined at least earlier than the time when the control signal 130 becomes effective.

This selection signal 111 is input to the internal control signal generation circuit 231 and the external control No. 1 generation circuit 234, and when it is "0", the control signal 130 is output to the internal control signal 232.
In this case, the external control signal 234 is output.

At the same time, it is input to the internal data bus buffer 141 and the external data bus buffer 143, and in the case of "o", the data bus 140 is connected to the internal data bus 142, and "
If it is 1'°, it is connected to the external data bus 144.

Furthermore, it is simultaneously input to the response signal selection circuit 251, and "0" is input to the response signal selection circuit 251.
In the case of '', the internal response input signal 152 is converted to the response input signal 25.
If it is “1”, the external response input signal 153 is output as the response input signal 150.

In this way, by distributing the signals necessary for input/output depending on whether the target of input/output operation is internal or external, the support device can switch the input/output operation between internal and external.

This operation is shown in Figure 6 for the above four types of operations 301 and 302.
．． 303 and 304 are shown in the timing diagram as representatives.

Even in the conventional support device, the selection signal 111 is the input/output control signal 1.
30 is determined before it is output, by the time the signals necessary for the data bus 140 and the response input signal 150 need to be determined, their contents have already been connected to the corresponding devices, and the operation of the CPU 101 is Leave no obstacles.

7 is a circuit diagram of an example of the internal control signal generation circuit 231 and external control signal generation circuit 233 in FIG. 5, and FIG. 8 is a circuit diagram of the internal data bus buffer 141 and external data bus buffer 141 in FIG.
An example circuit of the buffer 143 is shown corresponding to one of each data bus.

FIG. 9 is a circuit example of the response signal selection circuit 251 shown in FIG.

130-1 in FIG. 7 is a memory read control signal, 130
-2 is a memory write control signal and corresponds to 130.

Similarly, 232-1 is an internal memory read control signal, 23
2-2 is an internal memory write control signal, which corresponds to 232, and 234-1 is an external memory read control signal, 234-
2 corresponds to 234, which is an external memory write control signal.

The inside of 231 and 233 is a simple AND as shown in the figure.
It consists of a circuit and an N07 circuit.

Reference numeral 130-1 in FIG. 8 is a memory read control signal, which corresponds to the read control signal 130 as in FIG.

140 represents one of the data buses 140, and since data may be output to both data buses when writing data, this figure shows a circuit in that case.

As you can see from Figure 8, the inside of 141.143 is N07
It consists of a circuit, an AND circuit, and a three-state buffer often used as a data bus buffer.

This buffer outputs a signal when the control signal is "1".

This response signal selection circuit 251 in FIG. 9 also includes the N07 circuit and the A
This is a simple selector circuit consisting of an ND circuit and an OR circuit.

As can be seen from the figure, these circuits can be realized using only a combination of simple basic logic circuits.

[Problem to be solved by the invention]

In the conventional microcomputer development support device described above, when inputting and outputting data with an external input/output device, as the speed of the microcomputer increases, it becomes difficult to secure enough time for comparison and judgment of the detection circuit. In that case, there was a drawback that the internal control signal and the external control signal could not be accurately generated.

Furthermore, since the generated internal and control signals pass through the internal and external control signal generation circuits, they will inevitably be delayed with respect to the timing that the microcomputer outputs, and as a result, the characteristics of the bare microcomputer will be affected. The disadvantage was that the characteristics of the device inevitably deteriorated.

An object of the present invention is to provide a development support device that is compatible with high-speed microcomputers.

[Means to solve the problem]

The microcomputer development support device of the present invention has a detection circuit that detects whether the input/output signal corresponds to a built-in input/output device or an external input/output device, inputs a tarok signal as a reference time of operation, In a microcomputer development support device that inputs an external response input signal for synchronizing signal input/output operations with an external input/output device, the selection signal outputted from the detection circuit is inputted, and the selection signal outputted from the detection circuit is inputted. a delay circuit that artificially delays activation of a control signal to an external input/output device by a predetermined number of clocks; and a response signal delay circuit which inputs the selection signal and delays the external response input signal by the predetermined number of clocks. It is composed of

〔Example〕

Next, embodiments of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

100 is a support device main body, and 101 is a CPU.

102 is a detection circuit that detects whether the CPU10I selects an external or internal input/output device, 103 is an internal input/output device in the support device, and 1.4 is an external input/output device connected to the outside of the support device. Output bag! It is.

110 is a clock signal supplied to the CPU 101.

111 is a selection signal output from the detection circuit 102 for selecting either an external or internal input/output device.

120 is an address signal output from CPUl0I, 1
21 is an internal address buffer that supplies the address signal 120 to the internal input/output device 103; 122 is the supplied internal address signal; 123 is the internal address buffer that supplies the address signal 120 to the internal input/output device 103;
Address buffer 124 is a supplied external address signal.

Reference numeral 130 indicates a plurality of control signals output from the CPU 101 to the input/output device, and here, as in the conventional example shown in FIG. Indicates when there is.

Reference numeral 131 denotes an internal control signal delay circuit that delays the control signal 130 by a certain number of locks and supplies it to the internal input/output device 103 when the selection signal 111 is an internal selection.

132 is a supplied internal control signal.

Reference numeral 133 denotes an external control signal delay circuit that delays the control signal 130 by a certain number of locks and supplies it to the external input/output device when the selection signal 111 is external selection.

134 is a supplied external control signal.

140 is a data bus through which CPU10I inputs and outputs data to and from an input/output device.

141 is an internal data bus buffer that connects the internal input/output device 103 and the data bus 140 when the selection signal 111 is internal selection; 142 is an internal data bus buffer that connects the internal input/output device 103 and the data bus 140;
4 internal data bus.

143 is an external data bus buffer that connects the external input/output device 104 and the data bus 140 when the selection signal 111 is external selection, and 144 is an external data bus connected to the external input/output device 104.

150 is a response input signal to CPU10I, and 151 is an internal input/output device 1 when the selection signal 111 specifies internal.
This is a response signal delay circuit which has the function of selecting a response signal from external input/output device 104, selecting a response signal from external input/output device 104, and simultaneously delaying the response signal by a certain number of clocks.

152 is an internal response signal, and 153 is an external response signal.

In addition, each signal of the above 124.134.144.153 is
As shown in the conventional support device shown in FIG. 5, the signal is output to the outside of the support device through a probe-shaped connector.

FIG. 2 is a timing diagram for explaining memory read and write operations for external input/output devices and memory write and read operations for internal input/output devices in the block of FIG.

201 is a period of memory read operation for an external input/output device, 202 is a write to memory for an internal input/output device, 203 is a period of write to memory for an external input/output device, and 204 is a period for reading from memory for an internal input/output device. These reading periods are each one clock longer than the corresponding conventional periods 301, 302, 303, and 304 in FIG.

Here, 130-1 is a memory read control signal, 130
-2 is a memory write control signal and corresponds to 130, 13
2'-1 is an internal memory read control signal, 132-2 is an internal memory write control signal, which corresponds to 132, and 134
-1 is an external memory read control signal, and 134-2 is an external memory write control signal, which corresponds to 134.

The selection signal 111 selects the external when the output is “1゛°.
When it is “0”, the internal is selected, and the control signal 13
0-1.130-2.132-1.132-2.134
−1.134-2 is assumed to request input/output operation when the output is “1”, and response input signal 150.152
．． 153 indicates that the operation of the input/output device is completed when the output is "1".

Next, specific operations will be explained using FIGS. 1 and 2.

First, the detection circuit 102 receives the contents of the address signal 120 and outputs the selection signal 111 at the timing 111.

111 is determined after a time delay required for detection from the rising edge of the first clock signal 110.

In the case of this embodiment, the selection signal 111 may be determined within at least the time when the control signal 130 becomes effective plus one clock, which is the number of tarocks to be delayed.

Internal control signal delay circuit 131 and external control signal delay circuit 1
34 inputs this selection signal 111 and the tarock signal 110 input to CPU101, and when it is "0", the control signal 133 is delayed by one clock and output to the internal control signal 132, and when it is "1", the control signal is outputted to 1. The signal is delayed by a clock and is output to the external control signal 134.

At the same time, the selection signal 111 is input to the internal data bus buffer 141 and the external data bus buffer 143, and when it is "0", the data bus 140 is input to the internal data bus 141.
42, and when it is "1", it is connected to the external data bus 144.

Furthermore, at the same time, the response input signal delay circuit 151 inputs the clock signal 110 and the input/output control signal, and after forcing the response input signal to "0°'" at the timing necessary to delay the input/output operation of the CPU10I by one clock, Input the above selection signal 111, and if it is “0”, the internal response input signal 15
2, and if it is "1", the external response input signal 153 is output as the response input signal 160.

As shown in Figure 2, when comparing this timing with the conventional timing shown in Figure 6, the time for each input/output operation is 1
There is an extra clock, but from the perspective of the external input/output device, the first 1 clock is considered to be inactive, and it appears to be operating in 4 clocks starting from the 2nd clock. . Here, the external control signal delay circuit 13
The delay time from clock input to output of 4 is cPUlo
If the delay time from l to I/O control signal is designed to be the same as the delay time of the input/output control signal, the data value output during write operation from the address signal and data bus can be determined by the second clock, so the output signal of the support device This has the effect of making the characteristics similar to those of the output signal of a bare microcomputer.

3 is a circuit diagram of an example of the internal control signal generation circuit 132 and external control signal generation circuit 134 of FIG. 1, and FIG. 4 is a circuit diagram of an example of the response signal selection circuit 152 of FIG. 1. 13
As shown in the figure, the internals of circuits 1 and 133 have D-type flip-flops and some basic logic circuits added compared to 231 and 233 in FIG.

This D type flip-flop is a circuit in which the signal input to (D> in the figure is output to the (Q) output when the signal input to (CK) rises and changes).

The response signal delay circuit 151 in FIG. 4 is input to a circuit using a D-type flip-flop of the same type as in FIG. The response signal delay function is realized by inputting the signal into the .

As can be seen from FIGS. 4 and 5, these circuits can also be realized by simple combinations of basic logic circuits.

〔Effect of the invention〕

As explained above, the present invention makes it possible to secure sufficient comparison time necessary for the selection circuit of a development support device for a microcomputer, and at the same time, it is possible to virtually achieve characteristics close to the microcomputer itself in input/output to an external input/output device. This has the effect of supporting the development of high-speed microcomputers.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 and 4 are timing diagrams of each signal to explain the operation of the blocks in the figure. Figure 5 is a block diagram of an example of a conventional microcomputer development support device, Figure 6 is a timing diagram of each signal to explain the operation of the blocks in Figure 1, and Figure 7 is the internal control signal generation of Figure 5. 8 is a circuit diagram of the internal data bus buffer circuit and external data bus buffer circuit of FIG. 5, and FIG. 9 is a circuit diagram of the circuit and external control signal generation circuit.
This figure is a circuit diagram of the response signal selection circuit of FIG. 5. 100... Support device main body, 101... CPU, 10
2...Detection circuit, 103...Internal input/output device, 10
4... External input/output device, 110... Clock signal,
111...Selection signal, 120...Address signal, 1
21... Internal address buffer, 122... Internal address signal, 123... External address buffer,
124...External address/signal, 130...Internal control signal, 130-1...Memory read control signal, 1
302...Memory write control signal, 131...Internal control signal delay circuit, 132...Internal control signal, 13
2-1...Internal memory read control signal/signal, 132-
2... Internal memory write control signal, 133... External control signal delay circuit, 134... External control signal, 13
41...External memory read control signal, 134-2.
. External memory write control signal, 140... Data bus, 141... Internal data bus buffer, 142...
- Internal data bus, 143... External data bus buffer, 144... External data bus, 150... Response input signal, 151... Response signal delay circuit, 152...
・Internal response signal, 153...External response signal, 154・
...Response signal delay signal, 201...External memory read operation period, 202...Internal memory write operation period, 20B...External memory write operation period, 204.
... Internal memory read operation period, 200 ... Support device main body, 231 ... Internal control signal generation circuit, 233.
...External control signal generation circuit, 251...Response signal selection circuit.

Claims (1)

[Claims] It has a detection circuit that detects whether the input/output signal corresponds to a built-in input/output device or an external input/output device. In a microcomputer development support device that inputs an external response input signal for synchronizing input/output operations, the selection signal output from the detection circuit is input to activate a control signal for the external input/output device. A microcomputer development support device comprising: a delay circuit that artificially delays a predetermined number of clocks; and a response signal delay circuit that inputs the selection signal and delays the external response input signal by the predetermined number of clocks.