JP2626112B2 - Microprocessor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor that controls a bus cycle, that is, controls the active timing of a control signal in data transfer with a storage device or an input / output device. .

[Conventional technology]

Conventionally, when a microprocessor of this type starts a bus cycle, a control signal to a storage device (hereinafter, referred to as a memory) or an input / output device (hereinafter, referred to as an I / O) has a certain (fixed) timing. Is configured to be active.

[Problems to be solved by the invention]

In the conventional microprocessor described above, since the active timing of the control signal in the bus cycle is fixed so as to become active after a certain time from the start of the bus cycle, a long write recovery time is required depending on the type of I / O. In this case, there is a drawback that software considerations are required so that the writing operation is not continued.

Further, in the conventional microprocessor, if the operating frequency is changed in terms of hardware, in order to approach an optimum bus cycle sequence, the number of dummy instructions (processing for discontinuous write cycles) is increased or decreased. There is a disadvantage that necessity arises.

An object of the present invention is to provide a microprocessor that facilitates software design of active timing in such a bus cycle and improves the bus use efficiency.

[Means for solving the problem]

The microprocessor of the present invention, when setting a plurality of internal states that transition in clock units including an empty state, determines a transition between the plurality of internal states by a combination of an access request signal and an external signal, and A state generation circuit for outputting a state signal, and an address signal and a control signal for controlling a bus for writing and reading data to and from a storage device and an input / output device by the plurality of state signals from the state generation circuit A bus control circuit for activating the control signal according to the state signal of the state generation circuit, and controlling a bus cycle when accessing the storage device and the input / output device. It is configured as follows.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a microprocessor showing a first embodiment of the present invention.

As shown in FIG. 1, the present embodiment includes a state generation circuit 2 and a bus control circuit 3 inside a microprocessor 1. The state generation circuit 2 inputs a clock (CLK) 4 of a square wave signal and an access request signal 5 for activating a bus cycle, and a REDYF signal 6 and a READYL signal 7 which are external terminals. It outputs the state S2 signal 9 and the state SI signal 10 to the bus control circuit 3. The bus control circuit 3 determines the change timing of the address bus 11 and the memory / I / O control signal bus 12 based on the signal state of the state signal group (S1, S2, SI).

FIG. 2 is a state transition diagram for explaining the operation of the state generation circuit shown in FIG.

As shown in FIG. 2, the internal state of the microprocessor 1 is one of S1, S2, and SI, and each state transits in units of one clock.

That is, A is when the READYF signal 6 is active, and B is when the READYL signal 7 is active and there is no next access request 5. Also, C, D, and G are each READYF
Signal 6 is inactive, READYL signal 7 is inactive, and there is no access request signal 5. Furthermore,
E is a state when the READYL signal 7 is active and there is a next access request signal 5, and F is an access request signal 5
It is the state when there was.

FIG. 3 is a timing chart for explaining the bus cycle operation of the microprocessor in FIG.

As shown in FIG. 3, when the access request signal 5 becomes active, the state generation circuit 2 enters the S1 state, and the state S1 signal 8 becomes "1". In this S1 state, the address information is output to the address bus 11, and the bus cycle starts. When the state generation circuit 2 is in the S1 state,
At the rising edge of the clock (CLK), the READYF signal 6 is sampled. If "1", the state transitions to the S2 state, and if "0", the state transitions to the S1 state.

Next, in the S2 state, the address information is continuously output to the address bus 11, and the memory / I / O control signal 12 is activated. In this S2 state, the clock (CL
At the rising edge of K), the READYL signal 7 is sampled,
If it is “1”, the state transits to the S1 state or the SI state, and if it is “0”, it transits to the S2 state. Further, when transitioning from the S1 state to the SI state, the memory / I / O control signal 12 is made inactive.

As described above, the write / read control signal 12 for the memory and the I / O is transmitted to the RE 1 input from the outside of the microprocessor 1.
Since the active timing can be varied according to the timing of the ADY signal, the bus use efficiency can be improved.

FIG. 4 is a block diagram of a microprocessor showing a second embodiment of the present invention.

As shown in FIG. 4, the present embodiment has a state generation circuit 2 and a bus control circuit 3 inside a microprocessor 1 in the same manner as the first embodiment described above. Is a square wave signal clock (CLK) 4 and an access request signal 5 for activating a bus cycle.
And a READY signal 13 which is an external terminal. The state control circuit 3 outputs the state S1 signal 8, the state S2 signal 9, and the state SI signal 10 output from the state generation circuit 2 to the bus control circuit 3, and the bus control circuit 3 outputs the state signal group (S1, S2, SI). The change timing of the address bus 11 and the memory / I / O control signal (bus) 12 is determined according to the signal state of the first embodiment.

In short, in this embodiment, the external signal sampled in the S1 state and the external signal sampled in the S2 state are READY
This is shared by the signal 13, which has the advantage that the number of terminals can be reduced compared to the first embodiment.

〔The invention's effect〕

As described above, the microprocessor of the present invention controls the transition from the S1 state to the S2 state by an external signal, so that the timing at which the control signals for writing and reading to the memory and the I / O become active is controlled. Because it can be made variable, the software design when incorporating I / O that requires a long recovery time into the system can be designed to the optimal bus cycle timing without considering hardware limitations, and bus use efficiency There is an effect that can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram of a microprocessor showing a first embodiment of the present invention, FIG. 2 is a state transition diagram for explaining the operation of the state generating circuit shown in FIG. 1, and FIG. 3 is FIG. And FIG. 4 is a block diagram of a microprocessor showing a second embodiment of the present invention. 1... Microprocessor, 2... State generation circuit,
3 Bus control circuit 4 Clock signal 5 Access request signal 6,7,13 External READY signal 8 S1 signal 9 S2 signal 10 SI signal 11 …… Address bus, 12 …… Memory I / O control signal bus.

Claims (1)

(57) [Claims] When setting a plurality of internal states that transition in clock units including an empty state, a transition between the plurality of internal states is determined by a combination of an access request signal and an external signal, and a plurality of state signals are set. And a bus for outputting an address signal and a control signal for controlling a bus for writing and reading data to and from a storage device and an input / output device by the plurality of state signals from the state generation circuit A control circuit, wherein the timing of activating the control signal can be changed by the state signal of the state generation circuit, and controlling a bus cycle when accessing the storage device and the input / output device. Microprocessor characterized.