JPH11126480A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a memory access optimized in access time to be performable without considering modes of a high-speed page mode and an EDO page mode by generating an access signal for accessing an external device and fetching data with the timing in accordance with the parameter designating the timing for fetching the data in clock unit. SOLUTION: A read/write request signal from a data processing means 1 controls a state machine 5 and operates a memory control circuit 4 in accordance with the parameter of a timing parameter register 3. And at the same time, it reads a DRAM 13 by operating the memory control circuit 4 in accordance with a read parameter register 2 and controlling the take-in timing of the read data. By this, just the change of the value of the read parameter register 2 enables the memory control corresponding to the high-speed page mode and the EDO page mode without considering the switching of the two modes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a high-speed page mode or an EDO (Extended Data Out) mode (hyper page mode).

[0002]

2. Description of the Related Art With the development of electronic technology in recent years, semiconductor devices such as microcomputers and memories represented by DRAMs have become widespread and used in all fields.

A microcomputer system including a microcomputer, a DRAM, and peripheral devices is mounted on all kinds of electronic devices and shows a wide range of application fields. In particular, applications to embedded fields such as portable devices are low cost and low power consumption. There is a demand for a high-performance microcomputer system.

Although microcomputers have been improved in performance by increasing their operating frequency, the operating speed of an external device connected to the microcomputer cannot follow the performance of the microcomputer. The efficiency of data transfer is the key to improving system performance.

A DRAM is provided with a high-speed page mode or an EDO mode (hyper page mode) for high-speed access. If this mode is used efficiently, high-speed data transfer becomes possible.

FIGS. 7A and 7B show operation timing charts of DRAM read access. FIG. 7A shows an address, RAS (Row Address Stro), changing at the same timing.
be) signal, CAS (Column Address Strobe) signal, R
FIG. 8 is a diagram illustrating a difference between read data output in a high-speed page mode and an EDO mode with respect to an E (Read Enable) signal. In the EDO mode, the output of the read data can be held until the next CAS cycle, and the output is extended by the CAS precharge time as compared with the high speed page mode.

When such a memory is used in a microcomputer system, in the high-speed page mode, read data is taken into the microcomputer at the rising edge of the CAS (arrow in FIG. 7A).

On the other hand, since the output of the read data is extended in the EDO mode, if the microcomputer can capture the read data after the rise of the CAS, the same CAS access time as in the high-speed page mode is guaranteed, and The CAS cycle time can be reduced. FIG.
As shown in FIG. 7B, when the microcomputer takes in the read data after the rise of the CAS (arrow in FIG. 7B), it is not necessary to satisfy the CAS access time ≦ CAS pulse width. The CAS cycle time can be reduced even with the same CAS access time.

In order to take advantage of such a memory feature, a conventional semiconductor device such as a microprocessor SH7
There is a method adopted in 708. In this method, an EDO mode designation bit is provided in the control register. EDO
When the mode is not set, the memory control corresponds to the high-speed page mode, and the read data is taken into the microcomputer at the rise of the CAS. On the other hand, when the EDO mode is set, control is performed such that read data is taken into the microcomputer with a delay of 1/2 CLK as compared with the high-speed page mode.

[0010]

As shown in FIGS. 7A and 7B, when comparing the high-speed page mode and the EDO mode, the difference between the rising edge of CAS and the point in time when the read data is fetched is the CAS cycle time. This is a point of shortening, that is, speeding up the read cycle.

However, in the conventional semiconductor device as described above, the difference between the read data fetch timings in the high-speed page mode and the EDO mode is fixed. Therefore, as the operating frequency of the microcomputer becomes higher, this difference becomes smaller and the access time becomes longer. However, there is a problem that the advantage of the EDO mode is hard to be obtained when a memory having the above is used. In addition, since there are two different modes of operation, a high-speed page mode and an EDO mode, there are problems in that the number of operation verification items increases, and as a result, the test time becomes longer.

In view of the foregoing, it is an object of the present invention to provide a semiconductor device which optimizes an access time and takes full advantage of the EDO mode without being conscious of switching between the high-speed page mode and the EDO mode. And

[0013]

SUMMARY OF THE INVENTION In order to solve the above problems, a semiconductor device according to the present invention operates in response to a clock and processes data in accordance with an instruction. A bus unit serving as a data transfer path, a parameter setting unit for setting a parameter for designating a timing of taking in data on the bus unit in units of the clock, and when a read request for an external device is received from the data processing unit, External device control means for generating an access signal connected to the external device together with the bus means, and taking in data from the bus means at a timing according to a parameter set in the parameter setting means. I do.

This makes it possible to perform a memory access with an optimized access time without being aware of the high-speed page mode and the EDO page mode.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a configuration diagram of a semiconductor device according to an embodiment of the present invention. In FIG. 1, reference numeral 12 denotes a semiconductor device according to the embodiment of the present invention, 1 denotes data processing means, 2
Is a read parameter register that stores a parameter that specifies the read data fetch timing, 3 is a timing parameter register that stores access timing parameters other than the read parameter, 4 is a memory control circuit that controls read / write of the memory, and 5 is a memory. A state machine for controlling the control circuit 4; a data input register 6 for storing data output from the memory; a data output register 7 for storing data output from the data processing means 1;
Stores the address output from the data processing means 1,
This is an address output circuit that shifts and outputs an address as needed, and operates in synchronization with the respective clocks 22 input. Reference numerals 9 and 10 denote tristate buffers for controlling data output.

The read parameter register 2 and the timing parameter register 3 constitute a parameter setting means 24. The memory control circuit 4, the state machine 5, the data input register 6, the data output register 7, and the tri-state buffers 9, 10 constitute an external device control means 11. Reference numeral 13 denotes a DRAM connected to the semiconductor device 12 and for which the data processing means 1 performs read / write. 14, 1
Reference numerals 5, 16, and 17 indicate that the memory control circuit 4 is a DRAM
13 is a RAS signal, a CAS signal, a RE signal, and a WE signal for controlling the X.13 signal. Reference numerals 18 and 19 denote a data input register 6, a data output register 7, and a DRAM 13 respectively.
A data bus and an address bus provided between them. 2
Numeral 0 denotes an address bus provided between the data processing means 1 and the address output circuit 8, and 21 denotes a data processing means 1, a read parameter register 2, a timing parameter register 3, a data input register 6, and a data output register 7.
Is a data bus provided between them. The address output circuit 8, the data buses 18, 21 and the address buses 19, 20 constitute a bus means 25. Reference numeral 22 denotes a clock supplied to the semiconductor device 12, and reference numeral 23 denotes state information supplied from the state machine 5 to the memory control circuit 4.

FIG. 2 shows the state transition of the state machine 5. The state machine 5 stays in the IDLE state 100 until the read / write request signal is asserted from the data processing means 1, and transitions from the IDLE state 100 to the row address access state 101 after the assertion of the read / write request signal. At this time, the state machine 5 controls the row address access state 10 until the memory control circuit 4 asserts the row address access end signal.
It stays at 1 and transits from the row address access state 101 to the column address access state 102 after the row address access end signal is asserted. At this time, the state machine 5 sets the column address access state 10 until the memory control circuit 4 asserts both the column address access end signal and the page access signal indicating that the access according to the read / write request signal is a page access.
When both the column address access end signal and the page access signal are asserted, the state transits from the column address access state 102 to the IDLE state 100.

FIG. 3 shows the configuration of the read parameter register 2 and the timing parameter register 3. 301
Is a field for setting a row address output period Tard;
2 is a field for setting a period Tasr from the row address output to the RAS signal 14 assertion, 303 is a field for setting a period Tacd from the column address output to the CAS signal 15 negation, and 304 is a field from the column address output to the CAS signal 15 assertion. Field for setting the period Tasc, 3
Reference numeral 05 denotes a field for setting a period Tcp from the negation of the CAS signal 15 to the output of the column address. 301, 30
The timing parameter register 3 is composed of the fields 2, 303, 304 and 305. 306 is C
This is a field for setting a period Trd from the assertion of the AS signal 15 until the data 18 is taken into the data input register 6.

The operation of the semiconductor device configured as described above according to the embodiment of the present invention will be described below with reference to operation timing diagrams shown in FIGS. 4, 5, and 6.

The outline of the operation is as follows. The state machine 5 is controlled by a read / write request signal output from the data processing means 1, and the memory control circuit 4 is operated in accordance with the parameters of the timing parameter register 3 to generate the memory control signals. In addition to the generation, the DRAM 13 is read by operating the memory control circuit 4 in accordance with the read parameter register 2 to control the timing of reading the read data. In the read operation, W
The E signal 17 is always negated.

(First Setting Example) Here, Tard = 6, Ta
The case where sr = 3, Tacd = 6, Tasc = 2, Tcp = 3, and Trd = 4 will be described with reference to FIG. In FIG. 4, T0 to T25 are cycles each representing one cycle of the clock 22.

The data processing means 1 gives the above setting to the read parameter register 2 and the timing parameter register 3 using the data bus 21.

In response to a read request from data processing means 1 in cycle T1, state machine 5 transits to row address access state 101 in cycle T2. In the cycle T1, the memory control circuit 4 outputs the control signal to the address output circuit 8 upon receiving the state information 23 indicating that the state of the state machine 5 is the IDLE state 100 and the read request from the data processing means 1, and According to the clock 22, counting of the row address output period and the period up to the assertion of the RAS signal is started. In cycle T2, the address output circuit 8 stores the address output from the data processing means 1 in accordance with the control signal of the memory control circuit 4, and outputs a row address to the address bus 19 by performing a shift according to the row address.

The memory control circuit 4 stores the state information 23 of the state machine 5 in the row address access state 101.
, The RAS signal is asserted in the cycle T5 where Tasr = 3, and the cycle T5 where Tard = 6 is asserted.
At the same time as outputting a control signal to the address output circuit 8 in cycle T7 so that the column address is output at
The end of the row address access period is notified to the state machine 5 by a control signal. The state machine 5 transitions to the column address access state 102 in cycle T8 according to the control signal of the memory control circuit 4. In accordance with the control signal of the memory control circuit 4, the address output circuit 8 outputs the column address to the
Output to RAM13. In the same cycle, the memory control circuit 4 starts assertion of the CAS signal 15 and counting of the negation period, and Tasc = 2 while the state information 23 of the state machine 5 indicates the column address access state 102. CAS in cycle T10
It asserts the signal 15 and asserts the RE signal 16 to start counting data input timing.

In a cycle T13, the memory control circuit 4 asserts an enable signal to the data input register 6 for one clock. In a cycle T14 when Trd = 4, the memory control circuit 4 sends the DRAM 13 from the data bus 18 according to the enable signal. Stores the data output by.
The data stored in the data input register 6 is transferred to the data bus 21 through the tri-state buffer 9 as necessary.
And supplied to the data processing means 1. At the same time Ta
In cycle T14 where cd = 6, the memory control circuit 4 negates the CAS signal 15 and starts counting the CAS precharge period. Cycle T17 when Tcp = 3
To output the next column address, the memory control circuit 4
Outputs a control signal to the address output circuit 8 in cycle T16.

Thereafter, the operation as shown in FIG. 4 is obtained by repeating the access in the same manner. (Second setting example) Here, Tard = 6, Tasr = 3, Tacd
= 6, Tasc = 2, Tcp = 3, and Trd = 6 will be described with reference to FIG.

Until the CAS signal 15 and the RE signal 16 are asserted, the operation is the same as in the first setting example. Tacd = 6
In cycle T14, the memory control circuit 4 negates the CAS signal 15 and starts counting the CAS precharge period. Further, thereafter, in a cycle T15, an enable signal is asserted to the data input register 6 for one clock. The data input register 6 stores data output from the DRAM 13 from the data bus 18 in accordance with the enable signal in the cycle T16 when Trd = 6. The data stored in the data input register 6 is output to the data bus 21 through the tri-state buffer 9 as needed, and is supplied to the data processing means 1. In order to output the next column address in cycle T17 when Tcp = 3, the memory control circuit 4 outputs a control signal to the address output circuit 8 in cycle T16.

Thereafter, the operation as shown in FIG. 5 is obtained by repeating the access in the same manner. The operation at the time of reading has been described above. The operation at the time of writing will be described with reference to FIG. 6 according to (first setting example) and (second setting example). During the write operation, the read parameter register 2 is not used, the RE signal 16 is always negated and the WE signal 17 is asserted, and the data flow is
Since only the point from 13 to the data processing means 1 differs from the read operation, only the parts different from the read operation will be described below. Since the read parameter register 2 is not used, the (first setting example) and (second setting example) have the same setting,
Tard = 6, Tasr = 3, Tacd = 6, Tasc = 2, Tcp = 3.

In the cycle T7 where the row address output ends, the memory control circuit 4 outputs an enable signal to the data output register 7 and asserts the WE signal 17 at the same time. The data output register 7 takes in the data output from the data processing means 1 via the data bus 21 in the cycle T8, and outputs the data from the data bus 18 to the DRAM 13 via the tri-state buffer 10. Further, in a cycle T14 in which the CAS signal 15 is negated,
The tristate buffer 10 is closed, and the data bus 18 is brought into a high impedance state.

Thereafter, the operation as shown in FIG. 6 is obtained by repeating the access in the same manner. The operation timing in FIG. 4 is in the high-speed page mode, and the operation timing in FIG.
It corresponds to the DO mode.

In the above embodiment, the value set in the read parameter register 2 is counted in units of the number of clocks, but may be an absolute time independent of the clock cycle. This case can be realized by adding a means for dividing the set absolute time by a given clock cycle and converting the time into the number of clocks. This has the advantage that the user can set the time for fetching data without being aware of the clock frequency.

As described above, according to the embodiment of the present invention, it is possible to perform memory control corresponding to both the high-speed page mode and the EDO mode without being aware of the mode switching simply by changing the value of the read parameter register 2. Becomes Further, since the read parameter can be changed by an integral multiple of the clock, even if the clock frequency becomes higher, C
The difference between the rise of the AS and the point in time at which the read data is fetched can be increased, and the memory control that makes the most of the advantages of the EDO mode can be performed.

[0034]

As described above, according to the present invention, by changing the value of the read parameter register, the high-speed page mode and the ED
Since both the O-page mode can be supported, the number of operation verification items can be reduced, and as a result, the test time can be reduced. Further, by making the read data fetch timing variable, there is an advantageous effect that a memory access with an optimized access time can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a state transition diagram of a state machine 5 shown in FIG.

FIG. 3 is a configuration diagram of a read parameter register 2 and a timing parameter register 3 shown in FIG.

FIG. 4 is a timing chart of a first operation of the semiconductor device according to the embodiment;

FIG. 5 is a timing chart of a second operation of the semiconductor device according to the embodiment;

FIG. 6 is a timing chart of a third operation of the semiconductor device according to the embodiment;

FIG. 7 is an operation timing chart of a DRAM for describing a problem to be solved by the invention;

[Explanation of symbols]

 Reference Signs List 1 data processing means 2 read parameter register 3 timing parameter register 4 memory control circuit 5 state machine 6 data input register 7 data output register 8 address output circuit 9, 10 tristate buffer 11 external device control means 12 semiconductor device 13 DRAM 14 RAS signal 15 CAS signal 16 RE signal 17 WE signal 18, 21 Data bus 19, 20 Address bus 22 Clock 23 State information 24 Parameter setting means 25 Bus means

Claims (6)

[Claims] A data processing unit that operates in response to a clock and processes data in accordance with an instruction; a bus unit serving as an address and data transfer path with an external device; Parameter setting means for setting a parameter specifying timing in the clock unit; and when receiving a read request for an external device from the data processing means, generate an access signal connected to the external device together with the bus means, An external device control means for taking in data from the bus means at a timing according to a parameter set in the parameter setting means. 2. The semiconductor device according to claim 1, wherein the parameter set in the parameter setting means is a time value counted based on the clock. 3. The external device comprises a dynamic random access memory, wherein the time value is based on a change point of a column address strobe signal issued to the dynamic random access memory as one of the access signals. The semiconductor device according to claim 2, wherein counting is performed by counting. 4. The apparatus according to claim 1, wherein said parameter setting means sets, in addition to said parameters, parameters including a timing of sending an address in said bus means and a timing of assertion of said access signal. 3
The semiconductor device according to claim 1. 5. The semiconductor device according to claim 4, wherein said parameter setting means is constituted by a register, and said parameter is written by said data processing means. 6. A data processing unit which operates in response to a clock and processes data in accordance with an instruction, a bus unit serving as an address and data transfer path with an external device, and taking in data on the bus unit Parameter setting means for setting a parameter for designating timing; when receiving a read request for an external device from the data processing means, generate an access signal connected to the external device together with the bus means; An external device control unit that fetches data from the bus unit at a timing according to a set parameter, wherein the parameter is a time value independent of a cycle of the clock.