JP2001175586A - Data processor and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor, which can increase the flexibility of an interface of an external memory device or the like. SOLUTION: A data processor 1 has a bus controller 6 for performing control for external bus access in response to the request of a central processing unit(CPU) 3. The bus controller has a finite state machine 11 for controlling the output of data direction signals (RDir and WDir) for instructing the data direction of external bus access, address output and data output on the basis of the transition of a state code (STN) of plural bits in response to the request of the CPU. The finite state machine outputs the state code to the outside. The data processor can generate strobe signals (CS, RD and WR) for instructing the assert, negate or others of the data direction at desired timing to a memory interface corresponding to the transition of the state code as desired. Thus, the flexibility of the interface to the external device is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a data processor and a data processing system in which flexibility of an interface to an external device such as a memory is considered.

[0002]

2. Description of the Related Art In order to interface a memory to a data processor such as a microcomputer or a microprocessor, a technology for providing an external memory interface controller to interface the memory, or a data processor itself having a built-in memory interface controller for data interface. Two techniques are provided for enabling a memory to be directly connected to a processor.

[0003] In any of the above techniques, the memory interface function is determined for the purpose of interfacing a specific memory. For example, just DRAM
(Dynamic Random Access Memory) when the interface cannot be used with a clock synchronous synchronous DRAM as well as a flash memory with completely different information storage format There are many.

[0004]

According to the study of the present inventor, the technical progress of the memory device is rapid, and the interface specifications of the memory device are changing accordingly, and a great change is expected in the future. In such a situation, when a memory interface circuit is incorporated in the data processor, the data processor itself must be modified to cope with such a change, and there is a limit to the quick response. Also, when a memory interface circuit is provided outside the data processor, such a change can be dealt with only by the memory interface circuit. The present inventor has found that it is necessary to accurately understand the relationship with the bus control. Conventional data processors do not directly output the state of internal bus control to the outside. For example,
Even when the data processor controls the bus with the finite state machine, it does not output the state code of the finite state machine to the outside. The above considerations by the present inventor apply not only to memory devices, but also to other devices subject to external bus access by the data processor.

It is an object of the present invention to provide a data processor which can increase the flexibility of an interface to an external device such as a memory.

Another object of the present invention is to provide a data processing system which can easily realize an interface with a data processor even when using a device having a new interface specification or having a changed interface specification. is there.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the data processor has a bus controller and a control circuit capable of requesting external bus access via the bus controller in one semiconductor chip. In response to a request from the control circuit, the bus controller controls output of a data direction signal indicating a data direction of an external bus access, address output to the outside, and data input / output to / from the outside. , Sequentially generate a plurality of bits of state code in synchronization with the start of the external bus access control and output the generated state code to the outside.

[0010] A data processor according to a more detailed aspect has a central processing unit that decodes and executes instructions, and a bus controller that controls external bus access in response to a request from the central processing unit. The bus controller, in response to a request from the central processing unit, outputs a data direction signal indicating a data direction of an external bus access, an address output, and a data input / output based on a transition of a multi-bit state code. It has a finite state machine to control. The finite state machine outputs the state code to the outside.

The data processor outputs the state code of the finite state machine for controlling the bus to the outside. Therefore, the data processor inputs the state code and the data direction signal to the outside, and receives a desired state code transition. It is possible to generate a strobe signal for giving assertion or negation of data direction and other instructions at a desired timing. Therefore,
The data processor can increase the flexibility of the interface to external devices such as memories.

The finite state machine has a control register in which the number of operating cycles for extending an external bus cycle is specified by the central processing unit, and suppresses transition of the state code during the number of cycles specified by the control register. May do it. This facilitates control of externally inserting a wait state in synchronization with the operation reference clock signal of the data processor.

The data processing system receives the data processor, an external bus connected to the data processor, a memory connected to the external bus, the state code and the data direction signal,
And a memory interface circuit for generating an access control strobe signal for the memory according to the decoding result.

Since a data processor for outputting a state code of a finite state machine for performing bus control to the outside is used, even when a memory device or the like having a new interface specification or a changed interface specification is used, the data processor is not connected to the data processor. Interface can be easily realized.

[0015] The memory interface circuit may include a programmable decoder capable of programming decode logic for the state code and the data direction signal. As a result, it becomes possible to respond quickly when the interface specification is changed or a new device having the interface specification is used.

[0016]

FIG. 1 shows an example of a data processor and a data processing system using the same according to the present invention. Although not particularly limited, the data processor 1 shown in FIG. 1 has a central processing unit (CPU) 3 connected to an internal bus 2 and a random access memory (RAM).
4, input / output circuit (I / O) 5, bus controller (BS)
C) 6 and clock pulse generator (CPG)
7 and is formed on one semiconductor substrate (semiconductor chip) such as single crystal silicon. The data processor 1 is connected to an external memory 9 via a memory interface circuit 8.

The CPU 3 fetches an instruction from the RAM 4 or the like, decodes the instruction, generates a control signal, and performs register loading of operands, operation of the loaded data, memory storage of the operation result, and the like according to the control signal. Then, the data processor 1 is entirely controlled.

The RAM 4 is used as a main memory of the CPU 3. The I / O 5 has a function such as a timer / counter or a serial interface. A clock pulse generator 7 generates an operation reference clock signal CLK from an oscillation signal using an external vibrator,
It is used as a synchronous clock signal of a built-in circuit such as 3 or BSC6, and is output to the outside as a system clock signal.

The BSC 6 has a bus interface circuit (BITF) 10 and a state control machine (FSM) 11. The bus interface circuit 10 connects the external address bus ABUS and the external data bus DBUS to the internal bus 2
Interface to The internal bus 2 is an address bus,
Data bus and control bus are collectively referred to. When the CPU 3 accesses the access space of the external memory 9, the bus interface circuit 10 determines the necessity of the external bus access based on the address area of the address signal supplied from the internal bus 2. BSC6 is connected to CP via internal bus 2.
It has a control register 14 that can be read / written by U3. The control register 14 has address mapping information of the external address space. In the control register 14, information on the number of operating cycles for extending the external bus cycle (extended cycle number information) is set. The lengthening cycle number information is not particularly limited, but may be set for each address area specified by the address mapping information.

The state control machine 11 has a state register 12 and a combination control logic circuit 13. The state register 12 holds a plurality of bits, for example, a 3-bit state code STN supplied from the combination control logic circuit 13,
This is returned to the combination control logic circuit 13 as the current state code STN. The state code STN output from the status register 12 is also output to the outside as it is. The combination control logic circuit 13 responds to an external bus access request from the CPU 3 to output a read direction signal Rdir and a write direction signal WDir as data direction signals for instructing a data direction of the external bus access, And an external data bus DBUS by the bus interface circuit 10.
Data input / output to / from the STN of the state code.
And the setting value of the control register 14.

Here, the control logic of the combination control logic circuit 13 will be described with reference to FIG. The states indicated by the 3-bit state code STN are, for example, five states from state 0 to state 4. State 4
Is reset to state 0. One cycle of each state is one cycle of the clock signal CLK. C
When an external access request from PU3 is detected, in response to this, state 0 is sequentially transited from state 1 to state 4. At this time, the read direction signal R
dir and the write direction signal WDir are asserted from the beginning of state 1 to the end of state 4. The output of the read address and the write address is also from the beginning of state 1 to the end of state 4. The output of the write data is from the beginning of state 2 to the end of state 4. When the number of extension cycles is n, the state of state 3 is maintained for n cycles.

Although not particularly limited, the external memory 9 needs a chip select signal CS, a read signal RD, and a write signal WR as access strobe signals.
The timing required for the strobe signals CS, RD, WR in the read / write operation of the external memory 9 is as follows.
For example, as illustrated in FIG.

The memory interface circuit 8 receives the state code STN and the data direction signals RDir and Wdir, and generates access control strobe signals CS, RD and WR for the external memory 9 according to the decoding result. .

FIG. 3 shows the memory interface circuit 8.
Is shown. The memory interface circuit 8 includes a decoder 20 and latch circuits 21 to 25. The decoder 20 includes the state code STN,
The signals CS-DEC, RD-DEC, WR- are output according to the state of the data direction signals RDir, Wdir.
Generate DEC.

The truth value of the electricity generation logic by the decoder 20 is illustrated in FIG. For example, in state 0, all outputs are negated to "0" regardless of the input.
In state 1, the chip select signal CS is asserted on condition that the state is entered, and if RDir is asserted, RD-DEC is asserted and WDir is asserted.
Is asserted, WR-DEC is asserted.

The signals CS-DEC, RD-DEC, W
The latch circuits 21 to 23 that input R-DEC perform a latch operation in synchronization with the rising edge of the clock signal CLK, and the latch circuits 24 and 25 output the clock signal C.
By performing the latch operation in synchronization with the falling edge of LK, the strobe signals CS, RD, and WR are generated.

A programmable logic array (PLA) or a field programmable gate array (FPGA) capable of forming desired control logic by electrically programming a nonvolatile storage element in the decoder 20 , A desired logic can be easily configured. Since PLA and FPGL are known per se, a detailed description thereof will be omitted.

FIG. 2 shows the memory interface circuit 8.
The data processor 1 is connected to the external memory 9 through the control logic of
A timing chart when read / write access is performed is shown. As is clear from FIG. 2, the signal RDi output from the data processor 1 via the finite state machine
r, WDir, and state code STN, the strobe signal C of the timing required by the external memory 9
S, RD, and WR are generated by the memory interface circuit 8, and the external memory 9 is accessed. For example, in the read cycle from time t0 to time t5, the read address is output during the cycle period and the signal RDi
r is asserted, and states 0 to 4 are engraved. At this time, the external memory 9 is set to the chip selection state by the chip select signal CS during the period from the time t1 to the time t5, and the read signal RD is asserted during the period from the time t2 to the time t4. The read data is output to the data bus DBUS during a period of t4. In the write cycle from time t10 to time t14, the signal RDir is asserted during the cycle period, and the states 0 to 4 are carved. The write address is output during a period from time t11 to time t14. The external memory 9 is set to the chip selection state by the chip select signal CS during the period from time t11 to time t14, and the write signal W is set during the period from time t12 to t13.
R is asserted and the data bus D is
Write data on the BUS is written to the external memory.

As is clear from the above description, the data processor 1 is a finite state machine 11 for performing bus control.
, The state code STN and the data direction signals RDir and WDir are input externally, and assertion or negation of the data direction is performed at a desired timing with respect to the transition of the state code STN. In addition, a strobe signal giving other instructions can be generated as desired. Therefore, the data processor 1 can increase the flexibility of the interface with the memory device 9.

The finite state machine 11 can suppress the transition of the state code STN for the number of extension cycles specified by the control register 14. For example, the access operation of the external memory 9 is performed by the clock signal CLK.
If the number of extended cycles = 2 is set in the control register 14 when the above six cycles are required, the state code is transited in the order of 1, 2, 3, 3, 3, and 4 as a result. The memory interface circuit 8 having logic can extend the assert period of the strobe signals CS, RD, WR by two cycles. This allows
The memory interface circuit 8 can easily insert a wait state.

As shown in FIG. 1, the data processing system using the data processor 1 for outputting the state code STN of the finite state machine 11 for controlling the bus to the outside has a new interface specification. Alternatively, an interface with the data processor 1 can be easily realized even when a device such as a memory whose interface specification is changed is used. By configuring the decoder 20 with a PLA, an FPGA, or the like, the interface specifications of the external memory 9 are changed, or when the external memory 9 having a new interface specification is used, it is possible to respond particularly quickly.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto, and various changes can be made without departing from the gist of the invention. No.

For example, the logic configuration of the memory interface circuit and the type of the strobe signal to be output are not limited to the above examples, and can be changed as appropriate. The state code is not limited to three bits, and may be any number of bits. The external device is not limited to a memory, but may be an I / O such as a memory card controller or a serial interface.
/ O device. Further, the configurations of the internal circuit and the internal bus of the data processor are not limited to those in FIG. 1 and may include an address conversion mechanism, a cache memory, and the like. Further, the circuit module that requests the bus controller to access the external bus is not limited to the CPU, and may be a direct memory access controller or a data transfer controller built in the data processor.

[0034]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the data processor outputs the state code of the finite state machine for controlling the bus to the outside, it asserts or negates the data direction at a desired timing with respect to the transition of the state code, and other instructions. Can be generated as desired. Thus, the data processor can increase the flexibility of an interface to an external device such as a memory.

Even when a device such as a memory having a new interface specification or having a changed interface specification is used, an interface with a data processor can be easily realized to configure a data processing system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a data processor according to the present invention and a data processing system using the same.

FIG. 2 is a timing chart illustrating an operation when a data processor performs read / write access to an external memory via control logic of a memory interface circuit;

FIG. 3 is a block diagram illustrating an example of a memory interface circuit.

FIG. 4 is an explanatory diagram showing truth values of signal generation logic by a decoder.

[Explanation of symbols]

 Reference Signs List 1 data processor 2 internal bus 3 CPU 6 bus controller 7 clock pulse generator 8 memory interface circuit 9 external memory 10 bus interface circuit 11 state control machine 12 state register 13 combination control logic circuit 14 control register CLK operation reference clock signal Rdir read direction signal WDir write direction signal STN state code CS chip select signal RD read signal WR write signal ABUS address bus DBUS data bus 20 decoder 21-25 latch circuit

 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Tatsuro Nishino F-term within Hitachi Semiconductor Group 5-20-1, Kamizuhoncho, Kodaira-shi, Tokyo 5B060 CC01 MB00 5B061 FF01 GG02 RR03 5B062 AA10 CC01 FF02 FF04

Claims (5)

[Claims] 1. A semiconductor device comprising: a bus controller; and a control circuit capable of requesting an external bus access via the bus controller in one semiconductor chip, wherein the bus controller responds to a request from the control circuit. Data that indicates the data direction of external bus access
Controls the output of a direction signal, the output of an address to the outside, and the input / output of data to and from the outside, and sequentially generates a plurality of bits of state code in synchronization with the start of the external bus access control and outputs the state code to the outside A data processor, characterized in that: 2. A central processing unit that decodes and executes instructions, and a bus controller that controls external bus access in response to a request from the central processing unit, wherein the bus controller is a central processing unit. In response to a device request, data indicating the data direction of external bus access
A finite state machine that controls output of a direction signal, address output, and data input / output based on a transition of a state code of a plurality of bits, wherein the finite state machine outputs the state code to the outside A data processor, characterized in that: 3. The finite state machine has a control register in which the number of operation cycles for extending an external bus cycle is specified by the central processing unit, and the state code transition is performed during the number of cycles specified by the control register. 3. The data processor according to claim 2, wherein: 4. A data processor according to claim 3, an external bus to which said data processor is connected, a memory connected to said external bus, and said state code and said data direction signal. A memory interface circuit for generating a strobe signal for access control of the memory in accordance with a decoding result. 5. The data processing device according to claim 4, wherein said memory interface circuit comprises a programmable decoder capable of programming decode logic for said state code and said data direction signal. system.