JP2010282284A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer compatible with a new interface specification. <P>SOLUTION: A bus controller 30 includes a fixed bus control part 34, and a variable bus control part 35. A CPU 10 accesses an internal ROM 50 via the fixed bus control part 34, and reads variable bus control logic information, to be mapped in a programmable variable bus control logic part 35. The CPU 10 accesses an external memory connected to an external bus 62 via the variable bus control logic part 35. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a microcomputer which is a semiconductor integrated circuit, and more particularly to bus control.

  A microcomputer which is a semiconductor integrated circuit is widely used for device control. In addition, there are various types of memories mounted on the microcomputer, such as those having a larger memory capacity and those capable of high-speed memory access. For example, SRAM (Static Random Access Memory), flash memory, DRAM (Dynamic Random Access Memory), etc. are mentioned as a kind of memory.

  When these are connected to the bus, control specifications, addresses, access times, and the like in each memory are different, so interface specifications corresponding to the connected memory are required.

  In particular, when a new type of memory is provided, a new interface specification is required.

  In order to cope with this, it is possible to divide the address space of the microcomputer into a plurality of areas and select an interface for each area.

  Specifically, multiple interface specifications are implemented as bus control. This is implemented as a state machine or the like.

  Then, which state transition is to be taken is selected depending on, for example, an address output from the CPU serving as the bus master and a user setting.

  When the number of interfaces to be mounted increases, there is a problem that logic such as a state machine becomes complicated and a development period becomes long.

  In general, it is much more complicated to develop a single logic in which all n interfaces are mounted than to develop n interfaces separately.

  In addition, since one type of interface is normally set in each area of the address space, there is a problem that even if a plurality of interface specifications are implemented, an interface that is not actually used can be considered, which is wasteful.

  Also, the optimal mounting form may differ for one interface depending on the operating frequency. For example, if the operating frequency is high, the number of logical stages between FFs (Flip Flop) needs to be smaller than the latency. If this is performed in a region where the operating frequency is low, the effect of increasing the latency becomes relatively large.

  In view of these, for example, it is conceivable to support a new interface specification using a programmable FPGA (Field Programmable Gate Array) or PLD (Programmable Logic Array).

  For example, Japanese Patent Laid-Open No. 2004-56716 discloses a configuration in which an FPGA or a PLD is incorporated in a chip, reads configuration data from the built-in flash memory, and constructs a logic circuit in the FPGA or PLD. The method to do is disclosed.

  However, Japanese Patent Application Laid-Open No. 2004-56716 discloses a method of constructing a logic circuit by reading configuration data stored in a flash memory and transferring the configuration data to a programmable logic circuit. A method for providing a new interface specification for the attached memory is not disclosed.

  Japanese Patent Laid-Open No. 6-75849 discloses that a logic for mounting a memory control circuit corresponding to an internal programmable logic array is determined in accordance with a determination signal instructing the type of external memory. ing.

JP 2004-56716 A JP-A-6-75849

  However, in Japanese Patent Laid-Open No. 6-75849, after power-on, that is, when the programmable logic array is initialized, configuration data input from a specific terminal by an MPU (Micro Processing Unit) is used as a bus. However, there is no disclosure of means for accessing a program ROM in which data for constructing an internal programmable logic array is stored.

  That is, in the initial initialization state, since a programmable logic array is not configured, it is considered that a separate control circuit for controlling the program ROM is actually required, but any configuration is appropriate. There are no considerations.

  Therefore, the above document does not disclose a microcomputer that can cope with a new interface specification.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a microcomputer that can cope with a new interface specification.

  A microcomputer according to an embodiment of the present invention includes a control unit, an internal memory for storing construction data, an internal bus connected to the internal memory, a bus controller, and an external bus interface. The bus controller includes a bus control unit that accesses an internal memory via an internal bus, and a programmable logic unit. The control unit reads the construction data stored in the internal memory, and has a bus control function for accessing the external memory connected via the external bus interface on the programmable logic unit based on the construction data. To construct.

  According to one embodiment of the present invention, the microcomputer reads the construction data by the bus control unit that accesses the internal memory, and constructs a bus control function for accessing the external memory on the programmable logic unit. Therefore, it can cope with a new interface specification.

It is a figure explaining schematic structure of the microcomputer 1 grade | etc., According to Embodiment 1 of this invention. It is a figure explaining the address space of the microcomputer. 1 is a diagram illustrating a configuration of a PLD (Programmable Logic Device) 100. FIG. FIG. 4 is a diagram illustrating a specific example of the architecture of the LUT array 120 in FIG. 3. FIG. 3 is a diagram for explaining an LUT logical unit 121. It is a figure explaining the control timing of SRAM of an external bus interface. It is a figure explaining the control timing of SDRAM of an external bus interface. It is a figure explaining the state transition diagram of SDRAM. It is a figure explaining the setting of the bus controller 30 at the time of power activation according to embodiment of this invention. It is a figure explaining schematic structure of microcomputer 1 # etc. according to Embodiment 2 of this invention. It is a figure explaining the switching process of a variable bus control part. It is a figure explaining schematic structure of the microcomputer 1a according to Embodiment 3 of this invention. It is a figure explaining schematic structure of the microcomputer 2 according to Embodiment 4 of this invention. It is a figure explaining the process of the bus controller according to Embodiment 4 of this invention. It is a figure explaining schematic structure of another microcomputer 2 # according to Embodiment 4 of this invention. It is a figure explaining the case where dedicated RAM is divided and used for the area | region for variable bus control information, and the area | region for configuration memory. It is a figure explaining schematic structure of the microcomputer 3 according to Embodiment 5 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol in a figure shall show the same or an equivalent part.

(Embodiment 1)
A schematic configuration of microcomputer 1 and the like according to the first embodiment of the present invention will be described with reference to FIG.

  Referring to FIG. 1, a microcomputer 1 according to an embodiment of the present invention includes a CPU (Central Processing Unit) 10, an internal CPU bus 12, an internal peripheral bus 14, an internal memory bus 16, and a DMAC (Direct Memory). An access controller 15, a peripheral function 20, a bus controller 30, a ROM (Read-Only Memory) 50, a RAM (Random Access Memory) 55, and an external bus interface 60 are included.

  The CPU 10 is connected to the DMAC 15 and the bus controller 30 via the internal CPU bus 12 and manages the entire microcomputer 1.

  The DMAC 15 controls DMA transfer in the microcomputer 1 in response to a DMA transfer request from the CPU 10.

  The bus controller 30 manages the external bus 62 via the connected internal CPU bus 12, internal peripheral bus 14, internal memory bus 16, and external bus interface 60. Each bus includes at least one of an address bus line, a data bus line, a data control signal line, and the like.

  The ROM 50 is a boot ROM and stores a startup program and the like. The RAM 55 is used as a work area for the CPU 10.

  The external bus interface 60 is connected to the external bus 62 and executes data exchange between the bus controller 30 and a memory connected to the external bus 62.

The bus controller 30 includes a bus management unit 40 and a bus control unit 31.
The bus management unit 40 includes an internal CPU bus I / F 42, an internal peripheral bus I / F 44, and an arbitration control unit 46.

  The internal CPU bus I / F 42 is connected to the internal CPU bus 12 and executes data exchange with the CPU 10 via the internal CPU bus 12.

  The internal peripheral bus I / F 44 is connected to the internal peripheral bus 14 and exchanges data with the peripheral function 20 or the DMAC 15 via the internal peripheral bus 14.

  The arbitration control unit 46 monitors the bus use state, determines which device is given the right to use the bus with respect to the internal CPU bus 12, the internal peripheral bus 14, the internal memory bus 16, and the external bus 62, and uses the bus. We are mediating rights.

  The bus control unit 31 includes an address decoder 32, a fixed bus control unit 34, a variable bus control unit 35, a lock mechanism 38, and a multiplexer 36.

  The address decoder 32 decodes, for example, an address instruction from the CPU 10 or the DMAC 15 and activates a fixed bus control unit 34 or a variable bus control unit 35 described later.

  The fixed bus control unit 34 controls the ROM 50 or the RAM 55 connected to the internal memory bus 16 via the multiplexer 36.

  On the other hand, the variable bus control unit 35 includes at least one of a FLASH / ROM 70, an SRAM (Static Random Access Memory) 80, or an SDRAM (Synchronous DRAM) 90 connected to the external bus 62 via the multiplexer 36 and the external bus interface 60. Control one.

  The multiplexer 36 switches the connection between the fixed bus control unit 34 and the internal memory bus 16 or the connection between the variable bus control unit 35 and the external bus interface 60. The multiplexer 36 switches the connection based on the processing result obtained by the decoding process by the address decoder 32.

  In the present embodiment, the variable bus control unit 35 is assumed to be configured by a programmable PLD (Programmable Logic Device). In this example, a configuration using a PLD is described. However, the configuration is not limited to the PLD, and an FPGA (Field Programmable Gate Array) or the like can also be used.

The address space of the microcomputer 1 will be described with reference to FIG.
Referring to FIG. 2A, here, a case where a 4 GB address space (H'00000000 to H'FFFFFFFF) is provided is shown. This address space is controlled by the bus controller.

  An internal ROM is allocated to a partial area of area 0, and area 1 is allocated for variable bus control.

  In addition, an internal RAM and an internal I / O register are allocated to a part of the area 2. Assume that the addresses of the internal ROM, internal RAM, and internal I / O register are predetermined.

  Referring to FIG. 2B, here, a case where the area 1 of the address space is further divided into two is shown. Specifically, the case where it is divided into areas 1a and 1b is shown. For example, two memory devices connected to the external bus can be assigned to areas 1a and 1b, respectively.

  The configuration of a PLD (Programmable Logic Device) 100 will be described with reference to FIG.

  Referring to FIG. 3, PLD 100 has a configuration in which blocks 110 including a LUT (Look Up Table) array 120 and an FF (Flip Flop) cluster 130 are connected to each other via an interconnect unit 140.

  The interconnect unit 140 is interposed between the outside of the PLD 100 and the block 110 and between the blocks 110, and inputs and outputs signals between them.

  A specific example of the architecture of the LUT array 120 in FIG. 3 will be described with reference to FIG.

  Referring to FIG. 4, LUT array 120 is a plurality of LUT logical units 121 integrated in a matrix at a high density as a two-dimensional array.

  In FIG. 3, the FF cluster 130 has a plurality of FF logic units arranged in a column as a one-dimensional array.

The LUT logical unit 121 will be described with reference to FIG.
Referring to FIG. 5, the LUT logic unit 121 is a 2-input 1-output LUT composed of a 4-bit configuration memory and a 4to1 multiplexer.

  The LUT can set a logical function by setting the value of the 4-bit configuration memory.

  The output value Y for the input values A and B is determined based on a logical function corresponding to the set value of the 4-bit configuration memory (MEM1 to MEM4).

  In the LUT array 120, a wiring switch (not shown) is arranged between the LUT logical units 121 and connects the LUT logical units 121 to each other. The connection between the LUT logical units 121 is switched by this wiring switch. As this wiring switch, for example, a PMOS, an NMOS, or the like is used, and the LUT logic unit 121 may be electrically connected or disconnected by controlling the gate voltage.

  As described above, the LUT logic unit 121 and the wiring switch can change the logic and connection by changing the built-in configuration memory. Therefore, the circuit can be reconfigured after the LSI is manufactured.

  In this embodiment, the variable bus control unit is constructed by storing (mapping) variable bus control logic information described later in the configuration memory of the PLD.

Next, the control timing of the memory connected to the external bus will be described.
The control timing of the external bus interface SRAM will be described with reference to FIG.

  Referring to FIG. 6A, here, a case of reading when the external memory is an SRAM is shown.

  Here, the bus clock SDφ is shown, and it is assumed that one cycle is two cycles.

  Specifically, the read address Am for the external memory connected to the external bus 62 is input to the bus controller 30 together with the control signal. The address Am is decoded by the address decoder 32. Then, based on the decoding result, an area assigned to the corresponding external memory, for example, a chip select signal CS_n and a read enable signal RD_n corresponding to area 1 are asserted. Read data D15-D8 / D7-D0 from the SRAM is valid in the T2 cycle.

  Referring to FIG. 6B, here, a case of writing when the external memory is an SRAM is shown.

  Here, as in the case of reading, the write address Am for the external memory connected to the external bus 62 is input to the bus controller 30 together with the control signal. The address Am is decoded by the address decoder 32. Based on the decoding result, the chip select signal CS_n and the write enable signal WR_n corresponding to the area assigned to the corresponding external memory, for example, the area 1 are asserted. The write data D15-D8 / D7-D0 to the SRAM become valid from the fall of the T1 cycle.

  The control timing of the SDRAM of the external bus interface will be described with reference to FIG.

  Referring to FIG. 7A, here, a case of reading when the external memory is an SDRAM is shown.

  Here, a bus clock SDφ is shown, and the SDRAM operates in synchronization with the bus clock.

  Specifically, in the Td1 cycle, the row address for the external memory connected to the external bus 62 is input to the bus controller 30 together with the control signal. Specifically, the row address strobe signal RAS_n is asserted, and the row address is captured during that time. At this time, the read / write designation signal WE_n is asserted. The column address strobe signal CAS_n is negated.

  A command is issued based on the combination of RAS, CAS, and WE, and a PALL command for executing all bank precharges is issued.

  Next, in the Td2 cycle, the row address strobe signal RAS_n is asserted, and the active command ACTV is issued when the column address strobe signal CAS_n and the read / write designation signal WE_n are negated.

Next, the Td3 cycle is in the NOP state.
Next, in the Td4 cycle, the column address strobe signal CAS_n is asserted. Meanwhile, the column address is fetched. Further, the read / write designation signal WE_n is asserted.

  A write command WRITE is issued based on the combination of RAS, CAS, and WE.

  Then, the write data D15-D8 / D7-D0 to the SDRAM becomes valid in the Td4 cycle.

A state transition diagram of the SDRAM will be described with reference to FIG.
Referring to FIG. 8, after entering refresh state ST2 or power-on state ST4, an all-bank precharge command is issued (state ST6). Thereby, for example, when two banks A and B are provided in the SDRAM, both banks are precharged.

Then, an active command for bank A is issued (state ST8).
Then, a read / write command for bank A is issued (state ST10). As a result, a read or write operation of bank A is executed.

  Next, when page change processing is requested, a precharge command for bank A is issued (state ST12).

  Then, an active command for bank A is issued (state ST14). And it returns to state ST10 again.

  On the other hand, if the bank change process is requested in the state ST10, then the active command for the bank B is issued (state ST16).

  Then, a read / write command for bank B is issued (state ST18). Thereby, the read or write operation of the bank B is executed.

  Next, when page change processing is requested, a precharge command for bank B is issued (state ST20).

And it returns to state ST16 again.
On the other hand, when the bank change process is requested in the state ST18, the process proceeds to the state ST12. The subsequent processing is the same.

  Therefore, as shown in FIGS. 6 to 8, access to the SDRAM requires an access sequence using a command, unlike access to the SRAM.

  In the first embodiment of the present invention, a simple access sequence such as the SRAM used in the ROM 50 or the RAM 55 is accessed by the fixed bus control unit 34.

  On the other hand, an external memory that requires a complicated protocol (access sequence) such as SDRAM is accessed by the variable bus control unit 35.

  Using FIG. 9, setting of bus controller 30 at the time of power-on according to the embodiment of the present invention will be described.

  Referring to FIG. 9, it is first determined whether or not there is a power-on reset (step S2). Specifically, as power is turned on, a power-on reset circuit (not shown) outputs a power-on reset signal. The CPU 10 determines whether or not the signal is detected, and determines that the power is turned on when the signal is detected.

  Next, the CPU 10 executes a reset process (step S4). Specifically, the initial value is reset and initialization processing such as confirmation of the bus connection status is executed.

  Next, the CPU 10 executes a boot process (step S6). Specifically, the CPU 10 executes data reading of a program stored in the internal ROM. Specifically, the CPU 10 designates the address of the area 0 in which the internal ROM described in FIG. 2 is stored to the bus controller 30 via the internal CPU bus 12. The address decoder 32 of the bus controller 30 decodes an address input via the internal CPU bus I / F 42. If it is determined that the address is in area 0, the fixed bus control unit 34 is activated. The fixed bus control unit 34 accesses the ROM 50 through the multiplexer 36 and the internal memory bus 16.

  Then, the fixed bus control unit 34 of the bus controller 30 accesses the ROM 50 and reads a startup program or the like stored in the ROM 50.

  Next, the CPU 10 determines whether or not the variable bus control logic information is stored in the ROM 50 (step S8).

  If the CPU 10 determines that the variable bus control logic information is stored in the ROM 50 (YES in step S8), the CPU 10 sets the variable bus control information (step S10).

  Specifically, the CPU 10 constructs the variable bus control unit 35 by mapping the variable bus control logic information stored in the ROM 50 to the configuration memory of the PLD. Thereby, the variable bus control unit 35 can be used. For example, as an example, the variable bus control logic information stored in the ROM 50 corresponds to the control function of the SDRAM 90. Then, the variable bus control unit 35 notifies the lock mechanism 38 that the mapping of the variable bus control logic information is completed.

Then, the lock mechanism 38 sets a lock signal (step S11).
By setting the lock signal, storage of variable bus logical information in the variable bus control unit 35 can be prohibited. Further, the lock mechanism 38 notifies the address decoder 32 that a lock signal has been set. The address decoder 32 can start the variable bus control unit 35 upon receiving a notification of the setting of the lock signal from the lock mechanism 38. If the address decoder 32 has not received a lock signal setting notification from the lock mechanism 38, it is determined that the mapping to the variable bus control unit 35 has not been completed, so that the variable bus control unit 35 is activated. The fixed bus control unit 34 may be activated or may be the target of exception processing such as an address error.

Then, the process ends (END).
The variable bus control logic information in the ROM 50 may be stored in advance during chip design, or the variable bus control logic information may be stored in the ROM 50 from the outside using, for example, a ROM writer via a serial communication interface (SCI) included in peripheral functions. Control information may be written.

  For example, a case where the SDRAM 90 connected to the external bus 62 is accessed will be described.

  The CPU 10 designates the address of the area 1 described in FIG. 2 to the bus controller 30 via the internal CPU bus 12. The address decoder 32 of the bus controller 30 decodes an address input via the internal CPU bus I / F 42. If it is determined that the address is in area 1, the variable bus control unit 35 is activated. At this time, the multiplexer 36 switches the connection between the variable bus control unit 35 and the external bus interface 60 based on the decoding processing result of the address decoder 32.

  Then, the variable bus control unit 35 accesses the SDRAM 90 via the multiplexer 36, the external bus interface 60, and the external bus 62.

  In the case of a configuration in which an interface is provided for each type of memory, it is necessary to prepare an interface for each connected device, which may increase the circuit scale. It is also possible to reduce the circuit scale of the controller by merging the same functions. However, if the external memory configuration is diversified depending on the system / application, the functions should be merged in advance so as to correspond to all devices. Can be very difficult and complex, and can add extra design cost.

  By adopting a method of preparing variable bus control logic information and mapping it to the variable bus control unit as in the present application method, the circuit scale can be reduced. Further, it is not necessary to design a complicated controller, and the development period can be shortened.

  Further, by storing the variable bus control logic information, it is possible to cope with a new interface specification for the external memory.

  In this example, as an example, the variable bus control unit 35 constructed in the PLD based on the variable bus control logic information has been described as being accessible to the SDRAM 90 connected to the external bus 62. The present invention is not limited, and similarly, the present invention can be similarly applied to the FLASH / ROM 70 and the SRAM 80. That is, the variable bus control logic information for the FLASH / ROM 70 or the variable bus control logic information for the SDRAM 90 may be stored in the ROM 50, respectively.

(Embodiment 2)
A schematic configuration of microcomputer 1 # and the like according to the second embodiment of the present invention will be described with reference to FIG.

  Referring to FIG. 10, microcomputer 1 # according to the second embodiment of the present invention is different from microcomputer 1 in that two variable bus control information PA and PB are stored in internal ROM 50. . For example, it is assumed that the variable bus control unit 35 constructed in the PLD based on the variable bus control information PA can access the FLASH / ROM 70 connected to the external bus 62. Further, for example, it is assumed that the variable bus control unit 35 constructed in the PLD based on the variable bus control unit PB can access the SDRAM 90 connected to the external bus 62.

  In this example, as an example, it is assumed that area 1a in FIG. 2B is allocated as an external memory corresponding to FLASH / ROM 70. Further, it is assumed that the area 1b in FIG. 2B is allocated as an external memory corresponding to the SDRAM 90.

  The switching process of the variable bus control unit will be described with reference to FIG. Note that the method of mapping variable bus control information to the variable bus control unit 35 first is the same as that described in the first embodiment.

  Referring to FIG. 11, first, the address for the external memory is decoded (step S20). Specifically, as described above, the address decoder 32 of the bus controller 30 decodes an address input via the internal CPU bus I / F 42.

  Next, the address decoder 32 determines whether or not the designated area can be handled by the current variable bus control logic (step S22). For example, if it is determined that the address of the area 1a is designated, it is determined whether or not the current variable bus control logic corresponds to the area 1a.

  In step S22, when the address decoder 32 determines that the designated area can be handled by the current variable bus control logic (YES in step S22), the address decoder 32 executes the transfer (step S24). For example, when it is determined that the address of the area 1a is designated, and when it is determined that the current variable bus control logic corresponds to the area 1a, data transfer processing related to data reading or data writing is executed. .

  On the other hand, if the address decoder 32 determines in step S22 that the specified area cannot be handled by the current variable bus control logic (NO in step S22), the current logic is the logical information PA. It is determined whether or not there is (step S26).

  When address decoder 32 determines that the current logic is variable bus control logic information PA (YES in step S26), address decoder 32 requests to switch from variable bus control logic information PA to variable bus control logic information PB. Is output to the CPU 10 (step S28).

  On the other hand, when address decoder 32 determines that the current logic is not variable bus control logic information PA (NO in step S26), address decoder 32 issues a request for switching from variable bus control logic information PB to variable bus control logic information PA. It outputs to CPU10 (step S30).

  Next, the CPU 10 determines whether or not the data transfer process with the outside is completed (step S32). This is because if the function of the variable bus control unit 35 is switched before the data transfer process with the outside is completed, the previous transfer process is stopped and the process is not properly terminated.

  If it is determined in step S32 that the data transfer process with the outside has been completed (YES in step S32), the CPU 10 next requests the lock release, and the lock mechanism 38 releases the lock. (Step S34).

  Specifically, the lock mechanism 38 notifies the variable bus control unit 35 that the lock has been released, and the variable bus control information can be stored in the variable bus control unit 35 by this processing. The lock mechanism 38 notifies the address decoder 32 that the lock signal has been released. Upon receiving the notification of the release of the lock signal, the address decoder 32 disables the variable bus control unit 35 from being activated. This is because it is determined that the mapping to the variable bus control unit 35 is not completed when the lock signal release notification is received.

Then, the logical information is transferred (step S36).
Specifically, as described above, the CPU 10 executes data reading of a program stored in the internal ROM. Specifically, the CPU 10 maps the variable bus control information PA or the variable bus control information PB stored in the internal ROM 50 to the variable bus control unit 35.

  Thereby, the variable bus control unit 35 can be used. For example, as an example, the variable bus control unit 35 constructed in the PLD based on the variable bus control logic information PA is assumed to be accessible to the FLASH / ROM 70 connected to the external bus 62. On the other hand, it is assumed that the variable bus control unit 35 constructed in the PLD based on the variable bus control logic information PB can access the SDRAM 90 connected to the external bus 62.

Next, the lock mechanism 38 sets a lock signal (step S38).
By setting the lock signal, storage of variable bus logical information in the variable bus control unit 35 can be prohibited. Further, the lock mechanism 38 notifies the address decoder 32 that a lock signal has been set. The address decoder 32 can start the variable bus control unit 35 upon receiving a notification of the setting of the lock signal from the lock mechanism 38.

  Then, data transfer processing relating to data reading or data writing in the memory corresponding to the designated area is executed based on the decoding result obtained by decoding the address for the external memory (step S40).

  For example, if it is determined that the address of the area 1a is designated, and the current variable bus control logic corresponds to the area 1b, the variable bus control logic is switched to the area 1a and the data transfer process is executed. . Conversely, if it is determined that the address of the area 1b is designated, and the current variable bus control logic corresponds to the area 1a, the variable bus control logic is switched to the area 1b to perform data transfer processing. Execute.

Then, the process ends (END).
By switching the function of the variable bus control unit 35 that is a PLD by this method, it becomes possible to efficiently switch and access the external memory connected to the external bus.

(Embodiment 3)
A schematic configuration of microcomputer 1a according to the third embodiment of the present invention will be described with reference to FIG.

  Referring to FIG. 12, microcomputer 1 # a according to the third embodiment of the present invention is different from microcomputer 1 in that variable RAM control information is stored in internal RAM 55.

  As in this configuration, variable bus control information can be stored in the internal RAM 55.

  If there are multiple types of external memory and it is not possible to specify which external memory is used as the external memory during chip development (when determining ROM data), the variable bus control information can be transferred to the external memory or peripheral function when building the system. It is also possible to store in the internal RAM 55 by a communication interface via a serial communication interface (SCI) included in.

  Then, by mapping to the above-described PLD based on the variable bus control information stored in the internal RAM 55, it is possible to access an external memory connected to the external bus. That is, it is possible to cope with a new interface specification for an external memory.

(Embodiment 4)
A schematic configuration of microcomputer 2 according to the fourth embodiment of the present invention will be described with reference to FIG.

  Referring to FIG. 13, microcomputer 2 according to the fourth embodiment of the present invention differs from microcomputer 1 in that bus controller 30 is replaced with bus controller 30 #. Since the other points are the same, detailed description thereof will not be repeated. Another difference is that a lock mechanism 38 # that receives an input of an unlocking instruction from the arbitration control unit 46 is provided instead of the lock mechanism 38.

  The bus controller 30 # is different from the bus controller 30 in that a configuration control unit 37 and a dedicated RAM 39 are further provided.

  The configuration control unit 37 maps the variable control logic information stored in the dedicated RAM 39 to the variable bus control unit 35.

  Processing of the bus controller according to the fourth embodiment of the present invention will be described using FIG.

  Referring to FIG. 14, first, the address for the external memory is decoded (step S20). Specifically, as described above, the address decoder 32 of the bus controller 30 decodes an address input via the internal CPU bus I / F 42.

  Next, the address decoder 32 determines whether or not the designated area can be handled by the current variable bus control logic (step S22). For example, if it is determined that the address of the area 1a is designated, it is determined whether or not the current variable bus control logic corresponds to the area 1a.

  In step S22, when the address decoder 32 determines that the designated area can be handled by the current variable bus control logic (YES in step S22), the address decoder 32 executes the transfer (step S24). For example, when it is determined that the address of the area 1a is designated, and when it is determined that the current variable bus control logic corresponds to the area 1a, data transfer processing related to data reading or data writing is executed. .

  On the other hand, if the address decoder 32 determines in step S22 that the specified area cannot be handled by the current variable bus control logic (NO in step S22), the current logic is the logical information PA. It is determined whether or not there is (step S26).

  If address decoder 32 determines that the current logic is logic information PA (YES in step S26), address decoder 32 outputs a request for switching from variable bus control logic information PA to variable bus control logic information PB. (Step S28). Specifically, the address decoder 32 outputs a request for switching the variable bus control logic information (PA → PB) to the configuration control unit 37.

  On the other hand, when it is determined that the current logic is not logic information PA (NO in step S26), a request for switching from variable bus control logic information PB to variable bus control logic information PA is output (step S30). Specifically, the address decoder 32 outputs a request for switching the variable bus control logic information (PB → PA) to the configuration control unit 37.

  The configuration control unit 37 outputs a wait request to the address decoder 32 in response to the variable bus control logic information switching request (step S29).

  The address decoder 32 suspends processing according to the wait request and waits for transfer using the subsequent variable bus control unit 35.

  Next, the arbitration control unit 46 determines whether or not the data transfer process with the outside is completed (step S32). This is because if the function of the variable bus control unit 35 is switched before the data transfer process with the outside is completed, the previous transfer process is stopped and the process is not properly terminated.

  In step S32, when the adjustment control unit 46 determines that the data transfer process with the outside is completed (YES in step S32), the adjustment control unit 46 next requests the unlocking. The lock mechanism 38 releases the lock (step S34). Specifically, the lock mechanism 38 notifies the variable bus control unit 35 that the lock has been released, and the variable bus control information can be stored in the variable bus control unit 35 by this processing. The variable bus control unit 35 notifies the configuration control unit 37 that the lock has been released.

Then, the logical information is transferred (step S36).
Specifically, upon receiving a notification that the lock has been released, the configuration control unit 37 accesses the dedicated RAM 39 and executes data reading of the program stored in the dedicated RAM 39. Specifically, the configuration control unit 37 maps the variable bus control information PA or the variable bus control information PB stored in the dedicated RAM 39 to the variable bus control unit 35.

  Thereby, the variable bus control unit 35 can be used. For example, as an example, the variable bus control unit 35 constructed in the PLD based on the variable bus control logic information PA is assumed to be accessible to the FLASH / ROM 70 connected to the external bus 62. On the other hand, it is assumed that the variable bus control unit 35 constructed in the PLD based on the variable bus control logic information PB can access the SDRAM 90 connected to the external bus 62.

Next, the lock mechanism 38 # sets a lock signal (step S38).
By setting the lock signal, storage of variable bus logical information in the variable bus control unit 35 can be prohibited. Further, the lock mechanism 38 notifies the address decoder 32 that a lock signal has been set. The address decoder 32 can start the variable bus control unit 35 upon receiving a notification of the setting of the lock signal from the lock mechanism 38.

  And the configuration control part 37 cancels | releases a weight request | requirement (step S39).

  Specifically, the configuration control unit 37 notifies the address decoder 32 of cancellation of the wait request.

  The address decoder 32 receives the notification of the release of the wait request, and executes data transfer processing related to data reading or data writing in the memory corresponding to the designated area based on the decoding result obtained by decoding the address for the external memory. (Step S40).

  For example, if it is determined that the address of the area 1a is designated, and the current variable bus control logic corresponds to the area 1b, the variable bus control logic is switched to the area 1a to execute the transfer. On the other hand, if it is determined that the address of area 1b is designated, and the current variable bus control logic corresponds to area 1a, the variable bus control logic is switched to area 1b and the transfer is executed. To do.

Then, the process ends (END).
By switching the function of the variable bus control unit 35, which is a PLD, by this method, it is possible to efficiently switch and access an external memory connected to the external bus, and the configuration within the bus controller 30 #. Since the function of the variable bus control unit 35 is switched by the control unit 37, the function can be switched at high speed without using the CPU 10. In addition, the CPU process and the configuration process can be executed in parallel without interrupting the CPU process due to an interrupt, and it is possible to reduce the degradation of the system performance.

  As in this example, in the configuration according to the first embodiment, the adjustment control unit 46 determines whether or not the data transfer process with the outside is completed, and the lock mechanism 38 is used instead of the CPU. It is also possible to request the lock release.

  For example, as described with reference to FIG. 9, data is read from the program stored in the internal ROM by boot processing as described in FIG. Specifically, the CPU 10 can be realized by accessing the internal ROM 50 via the fixed bus control unit 34 and writing the variable bus control information PA and PB into the dedicated RAM 39 via the internal memory bus 16. .

  In addition, as described above, the variable bus control information can be transferred from the internal RAM to the dedicated RAM without being limited to the internal ROM.

  Alternatively, the variable bus control information can be written to the dedicated RAM 39 from the outside by a communication interface via the SCI included in the peripheral function.

  Further, in the example of FIG. 13 described above, the arbitration control unit 46 monitors the bus state in response to a request for switching the variable bus control logic information. Then, the arbitration control unit 46 determines whether or not the data transfer processing with the outside has been completed, and if it is determined that the transfer has been completed, a method of requesting the lock mechanism 38 # to release the lock Explained.

  On the other hand, it is also possible to give the configuration control unit the function of the lock mechanism.

  FIG. 15 illustrates a schematic configuration of another microcomputer 2 # according to the fourth embodiment of the present invention.

  Referring to FIG. 15, another microcomputer 2 # according to the fourth embodiment of the present invention is different from microcomputer 2 in that bus controller 30 # is replaced with bus controller 30 # a. Since the other points are the same, detailed description thereof will not be repeated. Specifically, the configuration control unit 37 # is provided with a lock mechanism function. Since other configurations are the same, detailed description thereof will not be repeated. That is, the configuration control unit 37 # holds information as to whether or not it is locked as an internal state. When the lock is set, writing to the variable bus control unit 35 is prohibited, and the lock is disabled. When it is released, writing to the variable bus control unit 35 is enabled.

  The processing of the bus controller described above with reference to FIG. 14 is almost the same, but in step S32, the configuration control unit 37 # determines whether the data transfer processing with the outside is completed (step S32). . If the configuration control unit 37 # determines in step S32 that the data transfer process with the outside has been completed (YES in step S32), the lock that is held as the internal state is then released ( Then, the logical information is transferred (step S36) and the lock is set (step S38). The subsequent processing is the same as described above.

  Also in this system, since the function of the variable bus control unit 35 is switched by the configuration control unit 37 # inside the bus controller 30 # a, the function can be switched at high speed without using the CPU 10. Further, the configuration can be simplified by providing the configuration control unit 37 # with the function of the lock mechanism.

  Further, in the configuration shown in FIG. 13 and FIG. 15, a configuration in which the dedicated RAM 39 is arranged close to the PLD which is the variable bus control unit 35 is adopted, and a part of the dedicated RAM is configured in the 4-bit configuration described above in the PLD. It is also possible to use it as an area of the configuration memory (MEM1 to MEM4).

  The case where the dedicated RAM is used separately for the variable bus control information area and the configuration memory area will be described with reference to FIG.

  With the method shown in FIG. 16, it is possible to reduce the circuit area by using a part of the dedicated RAM for storing the variable bus control information as an area for the configuration memory.

  Further, the dedicated RAM is constituted by, for example, a dual port RAM. Since it is possible to write data using the other port while reading data from one port, for example, the variable bus control information is transferred from the ROM 50 connected to the internal memory bus 16 to the dedicated RAM. Even in this case, high-speed transfer is possible.

(Embodiment 5)
The schematic configuration of microcomputer 3 according to the fifth embodiment of the present invention will be described using FIG.

  Referring to FIG. 17, microcomputer 3 according to the fifth embodiment of the present invention is different from microcomputer 1 in that peripheral function 20 is replaced with peripheral function 20 #. Since the other points are the same, detailed description thereof will not be repeated.

Peripheral function 20 # includes a peripheral function management unit 21 and a peripheral function control unit 24.
Peripheral function management unit 21 includes an internal peripheral bus I / F 22 and an arbitration control unit 23.

  The internal peripheral bus I / F 22 is connected to the internal peripheral bus 14 and executes data exchange with the CPU 10 or the DMAC 15 via the internal CPU bus 12.

The arbitration control unit 23 performs arbitration of the bus use right.
Peripheral function control unit 24 includes a fixed peripheral function unit 25, a variable peripheral function unit 26, a lock mechanism 27, and a multiplexer 28.

  It is assumed that the fixed peripheral function unit 25 can perform data communication with the outside through the multiplexer 28 using, for example, the port AA.

  On the other hand, it is assumed that the variable peripheral function unit 26 can perform data communication with the outside through the multiplexer 28 using, for example, the port BB.

  Specifically, as described above, for example, it is assumed that peripheral function control logic information for setting the variable peripheral function unit 26 is included in the ROM 50 connected to the internal memory bus 16.

  Then, it is read out by the CPU 10 via the fixed bus control unit 34 and mapped to the variable peripheral function unit 26. Since the mapping method and the like are the same as those described in FIG. 1, detailed description thereof will not be repeated.

  With this method, it is possible to design a new function for a peripheral function by providing a PLD not only for the bus controller but also for other peripheral functions. For example, a peripheral function corresponding to a new communication interface is set. It is also possible to do.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1, 1 #, 1a, 2, 3 Microcomputer, 10 CPU, 12 internal CPU bus, 14 internal peripheral bus, 15 DMAC, 16 internal memory bus, 20, 20 # peripheral function, 21 peripheral function management unit, 22 internal peripheral Bus I / F, 23 adjustment control unit, 24 peripheral function control unit, 25 fixed peripheral function unit, 26 variable peripheral function unit, 27, 38, 38 # lock, 28 multiplexer, 30, 30 #, 30 # a bus controller, 31 bus control unit, 32 address decoder, 34 fixed bus control unit, 35 variable bus control unit, 36 multiplexer, 37, 37 # configuration control unit, 39 dedicated RAM, 40 bus management unit, 42 internal CPU bus I / F, 44 Internal peripheral bus I / F, 46 Arbitration controller, 50 ROM, 55 RAM, 60 External bus Interface, 70 FLASH / ROM, 80 SRAM, 90 SDRAM.

Claims (8)

A control unit;
An internal memory for storing construction data;
An internal bus connected to the internal memory;
A bus controller;
With an external bus interface,
The bus controller
A bus control unit for accessing the internal memory via the internal bus;
Including a programmable logic part,
The control unit reads the construction data stored in the internal memory, and accesses the external memory connected via the external bus interface on the programmable logic unit based on the construction data A microcomputer that builds the bus control function of   The microcomputer according to claim 1, wherein the internal memory corresponds to a RAM.   The microcomputer according to claim 1, wherein after the reset process, the control unit reads the construction data stored in the internal memory and constructs the bus control function.   The internal memory is provided corresponding to each of the first and second external memories connected via the external bus interface, and a bus control function for accessing the corresponding external memory is constructed on the logic unit. The microcomputer according to claim 1, wherein the microcomputer stores first and second construction data for performing. The bus controller further includes an address decoder,
The address decoder receives an input of address information for accessing one of the first and second external memories connected via the external bus interface, and generates a switching signal based on a decoding result;
5. The microcomputer according to claim 4, wherein the control unit reads one of the first and second construction data from the internal memory in the previous period according to the switching signal, and switches a bus control function to be constructed on the logic unit. A peripheral circuit including the programmable peripheral function logic unit;
The internal memory stores peripheral function construction data for constructing peripheral functions,
The control unit reads peripheral function construction data stored in the internal memory, and constructs the peripheral function on the programmable peripheral function logic unit based on the peripheral function construction data. The microcomputer as described. A control unit;
An internal memory for storing construction data;
An internal bus connected to the internal memory;
A bus controller;
With an external bus interface,
The bus controller
A bus control unit for accessing the internal memory via the internal bus;
A programmable logic part;
Dedicated memory,
A configuration control unit that builds a bus control function on the programmable logic unit,
The control unit reads the construction data stored in the internal memory, stores it in the dedicated memory,
The configuration control unit builds a bus control function for accessing an external memory connected via the external bus interface based on the construction data stored in the dedicated memory. The logic unit includes a plurality of circuit information holding means,
The microcomputer according to claim 7, wherein the plurality of circuit information holding units are configured using a part of the dedicated memory.

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