JP2008059300A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of attaining low electric power consumption in a microcomputer. <P>SOLUTION: This microcomputer is provided with a CPU 101 operated by an internal electric power source 1, and a holding RAM 104 operated by an internal electric power source 2. The microcomputer has a usual operation mode supplying the internal electric power source 1 and the internal electric power source 2 to operate a clock of the CPU 101, a sleep mode or software standing-by mode supplying the internal electric power source 1 and the internal electric power source 2 to stop the clock of the CPU 101, and a deep standing-by mode blocking the internal electric power source 1 and supplying the internal electric power source 2 to stop the clock of the CPU 101. The microcomputer is provided with an address switch 102 for selecting a boot address when restored from the deep standing-by mode to the usual operation mode, one side of the selected boot address is a ROM 114 connected to an outside, and the other side is the holding RAM 104. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a microcomputer (hereinafter simply referred to as a “microcomputer”), and more particularly to a technique effective when applied to a microcomputer having a low power consumption mode.

  As a technique examined by the present inventor, for example, the following techniques can be considered in a microcomputer.

  Conventionally, a ROM built-in microcomputer was used as a system microcomputer. The system microcomputer controls the power supply IC. When reducing system power, shut off power to all components except the system microcomputer and power IC. At this time, the system microcomputer itself is in the low power mode. That is, the clock is stopped and power supply to other than the minimum block is internally cut off. When the system is restored from the low power state, the system microcomputer is first restored, and then power supply to other components is started by program control of the system microcomputer. Since the system microcomputer accesses the ROM built in itself, there is no problem even if power is not supplied to external components.

  Such a system often includes a microcomputer (ROMless microcomputer) that operates at a high speed instead of incorporating a ROM in addition to the system microcomputer. In this process, the ROM built-in microcomputer (system microcomputer) is in charge of controlling the power supply IC and the ROM-less microcomputer is in charge of processing that requires higher processing performance (for example, audio CODEC).

As a technique related to such a microcomputer, for example, Patent Document 1 is cited. In the technique of Patent Document 1, in order to make it possible to access an attached external storage device without using system software, power is supplied from an external program in the external storage device and an internal program in the boot ROM. There is provided selection means for selecting a program to be started when the power is turned on, and the memory area switching means switches the memory area so that the access request for the start address output from the processor at power-on is selected by the selection means. It is said to be performed for.
JP-A-8-17183

  By the way, as a result of examination of the microcomputer technology as described above by the present inventors, the following has been clarified.

  In recent years, there has been an increasing demand for building a system using only a ROMless microcomputer. In the case of a ROMless microcomputer, it is necessary to read the program from the external ROM, so if the power of the external ROM is cut off in the low power state of the system, the program can be read when the microcomputer is returned from the low power state. Can not. In other words, low power consumption cannot be achieved by a method similar to that of a conventional ROM built-in microcomputer. In the low power state of the system, this problem can be solved by supplying power to the outside in addition to the power supply IC and microcomputer, but the power reduction effect is naturally reduced.

  In many cases, components such as SDRAM and ASIC are also connected on the bus connecting the ROMless microcomputer and external ROM (FLASH memory, etc.). When the microcomputer is returned from the low power state, the power to these components is cut off. It is not preferable from the viewpoint of reliability or the like to supply power to the external ROM and operate a bus connected to components in a power-off state.

  Therefore, an object of the present invention is to provide a technology capable of realizing low power consumption in a microcomputer.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The microcomputer according to the present invention includes a CPU that operates with a first internal power supply and a RAM that operates with a second internal power supply. The microcomputer supplies the first internal power source and the second internal power source to operate a clock of the CPU, the first internal power source and the second internal power source. And a second operation mode in which the clock of the CPU is stopped and a third operation in which the clock of the CPU is stopped by supplying the second internal power by cutting off the first internal power supply Mode. And a means for selecting a boot address when returning from the third operation mode to the first operation mode, and one of the selected boot addresses is an externally connected memory, and the other is It is the RAM.

  According to the present invention, low power consumption can be realized in a microcomputer.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a block diagram showing the configuration of a microcomputer according to an embodiment of the present invention.

  First, an example of the configuration of the microcomputer according to the present embodiment will be described with reference to FIG. The microcomputer 100 of this embodiment is, for example, a microcomputer with a RAM boot function having a low power consumption mode, and is a semiconductor integrated circuit (LSI) formed on one semiconductor chip by a well-known semiconductor manufacturing technique. . The microcomputer 100 includes, for example, a CPU 101, an address switch 102, a high-speed RAM 103, a holding RAM 104, input / output devices # 0 to #N (105a, 105b,..., 105n), an external bus controller 106, a power supply The circuit 107, the power control unit 108, the reset / interrupt control unit 109, the IO buffers 110a and 110b, the bus bridge 111, the clock generator 112, and the like are included.

  The CPU 101 can execute instructions stored on the LSI (microcomputer 100), the high-speed RAM 103 in the LSI, and the holding RAM 104.

  The address switch 102 switches the address (boot address) to be referred to when the power is turned on or when returning from the deep standby mode when the holding RAM boot signal is given from the power control unit 108. The boot address stores the program to be executed next by the CPU 101 and the top address of the stack area.

  The high-speed RAM 103 is a memory that is connected to the CPU 101 via a high-speed bus and is accessible by the CPU 101 in one cycle. However, the leakage current is large. For this reason, the power is cut off in the deep standby mode, and the stored contents are lost.

  The bus bridge 111 is a bus bridge for connecting a high-speed bus and a system bus and absorbing a difference in operation speed.

  The holding RAM 104 is a memory that can operate only at a low speed but has a small leakage current. The power is supplied even in the deep standby mode, and the stored contents are not lost. The main object of the present invention is to boot from this holding RAM 104 when returning from the deep standby mode. In that case, before shifting to the deep standby mode, it is necessary to transfer information necessary for the boot process and a series of subsequent processes to the holding RAM 104. The holding RAM 104 stores a boot program for returning from the low power consumption mode to the normal operation mode. The high-speed RAM 103 described above operates at a higher speed than the holding RAM 104.

  Input / output devices # 0 to #N (105a, 105b,..., 105n) are input / output devices such as a serial interface and a parallel interface for exchanging information inside and outside the LSI.

  The external bus controller 106 is an interface block for accessing the external RAM 113, ROM 114, ASIC 115, etc. via the external bus.

  The power supply circuit 107 steps down power supplied from outside the LSI (microcomputer power supply) in accordance with an instruction from the power control unit 108, generates two types of internal power supplies, and supplies them to the LSI. The internal power supply 1 is cut off during deep standby. The internal power supply 2 is also supplied with power during deep standby.

  The power control unit 108 controls transition to and return from the deep standby mode in accordance with instructions from the CPU 101 and the reset / interrupt control unit 109. Further, in accordance with the setting of the built-in control register, the boot address instruction signal to the address switch of the CPU 101 and the terminal state of each IO buffer group during deep standby and immediately after returning from deep standby are instructed.

  The reset / interrupt control unit 109 accepts a reset, an interrupt request from outside the LSI, and an interrupt request (not shown) from each module inside the LSI according to a predetermined priority, and instructs each module inside the LSI to process. To do.

  When a reset or an external interrupt is accepted during the deep standby mode, a wakeup request indicating the return from the deep standby mode is output to the power control unit 108, and processing for each module is requested after the return from the deep standby mode. .

  The reset / interrupt control unit 109 generates an internal reset signal for the LSI internal module. The internal reset signal is asserted not only when an external reset signal is given, but also when an external interrupt is accepted during the deep standby mode.

  However, the power control unit 108 is reset only by an external reset signal. In other words, it is not reset by an external interrupt during deep standby mode.

  The IO buffers 110a and 110b output signals inside the LSI to the outside of the LSI and supply input signals from outside the LSI to the inside of the LSI. In general, the operating voltages are different between the outside of the LSI and the inside of the LSI, but the IO buffers 110a and 110b absorb this difference. The IO buffers 110a and 110b are divided into a plurality of groups, and the terminal states during deep standby and immediately after returning from deep standby can be controlled for each group. In this example, the I / O buffer 110b related to the external bus and the I / O buffer 110a for other purposes are divided into two groups.

  The terminal state during deep standby in the IO buffers 110a and 110b is the previous state (input / output, output value) when “terminal holding” is set, and the high impedance (HiZ) when “terminal holding is not set”. It becomes. The state at the time of return from deep standby in the IO buffers 110a and 110b is “terminal holding”, terminal holding is continued until a predetermined operation is performed, and “terminal holding not” is shifted to a reset state. To do.

  FIG. 2 is a block diagram showing a clock configuration of the microcomputer according to the present embodiment. This LSI (microcomputer 100) operates with three types of clocks: a CPU clock, a high-speed clock, and a low-speed clock. These clocks are generated by the clock generator 112.

  In order to realize high computing performance, the CPU 101 and the high-speed RAM 103 operate with a high-speed clock (CPU clock, high-speed clock). Other blocks that do not require such high performance operate with a slower clock (low-speed clock) in order to reduce power consumption.

  FIG. 3 is a diagram showing an outline of the low power consumption mode of the microcomputer according to the present embodiment. This LSI (microcomputer 100 with RAM boot function) has three types of low power consumption modes in addition to the normal operation mode. The outline of each low power consumption mode is shown below.

  FIG. 4 is a waveform diagram showing an operation in the sleep mode in the low power consumption mode. When the CPU executes the SLEEP instruction in a state where the standby enable bit (STBY bit) provided in the power control unit 108 is “0”, the present LSI transits from the normal mode to the sleep mode. In sleep mode, only the CPU clock stops. The high-speed clock and low-speed clock operate in the same manner as in the normal operation mode. The CPU 101 stops after executing the SLEEP instruction, but the register contents of the CPU 101 are retained.

  The sleep mode is canceled by an interrupt request outside the LSI or an interrupt request from various input / output devices inside the LSI. When an interrupt request occurs, the sleep mode returns to the normal operation mode. After returning to the normal operation mode, the CPU 101 performs processing according to the given interrupt request.

  Of course, the sleep mode is also released when a reset is given.

  FIG. 5 is a waveform diagram showing the operation of the software standby mode in the low power consumption mode. If the CPU 101 executes the SLEEP instruction when the STBY bit is "1" and the deep standby enable bit (DSTB bit) in the power control unit is also "0", the LSI switches from normal mode to software standby mode. Transition. In software standby mode, the clock generator stops in addition to all LSI internal clocks including the CPU clock. The CPU 101 stops after executing the SLEEP instruction, but the contents of the registers in the CPU 101 are retained. As for the registers of the input / output devices # 0 to #N (105a, 105b,..., 105n), there are registers for which contents are held and registers for which they are initialized.

  The software standby mode is canceled by an interrupt request from outside the LSI. When an interrupt request outside the LSI is generated, the software standby mode is shifted to the oscillation stabilization period. When shifting to the oscillation stabilization period, the clock oscillator starts operating, but the CPU clock, high-speed clock, and low-speed clock remain stopped. The clock generated by the oscillator is supplied only to the oscillation stabilization period measurement counter. When the number of cycles set in the counter elapses before shifting to software standby, the oscillation stabilization period ends and the normal operation mode is restored.

  After returning to the normal operation mode, the CPU 101 performs processing according to the given interrupt request. The input / output devices # 0 to #N perform an operation determined for each circuit. For example, for the circuit in which the contents of all the registers are held, the operation before the transition to the software standby mode is continued.

  Needless to say, the software standby mode is canceled when a reset is given.

  FIG. 6 is a waveform diagram showing an operation in the deep standby mode in the low power consumption mode. When the CPU 101 executes the SLEEP instruction with both the STBY bit and the DSTB being “1”, the present LSI transits from the normal mode to the deep standby mode. In the deep standby mode, not only all clocks and clock generators stop, but also a part of the LSI internal power supply (internal power supply 1) is shut off. Of course, all the contents of the registers of the CPU 101 and the input / output devices # 0 to #N are lost.

  The deep standby mode is canceled by an interrupt request from outside the LSI. When an interrupt request external to the LSI is generated, the transition from deep standby mode to the oscillation stabilization period occurs. When shifting to the oscillation stabilization period, the supply of the internal power supply 1 is resumed and the clock oscillator starts operating. The subsequent operation is the same as the return from software standby.

However, the operation after returning to the normal operation mode is different from software standby. The CPU 101 performs the same processing as when a reset is given regardless of the given interrupt request.
The input / output devices # 0 to #N also operate in the same way as when the reset is released, like the CPU 101.

  Needless to say, the software standby mode is canceled when a reset is given.

  FIG. 7 is a diagram showing the configuration of the address switch 102. When the internal reset signal once asserted is negated when an external reset is given or when returning from deep standby, the CPU 101 performs a boot process. Here, the boot processing refers to processing for reading the initial values of the program counter (PC) and the stack pointer (SP) from a specific address (boot address) and setting (initializing) them to the PC and SP. First set the PC, then set the SP. In the case of a ROMless microcomputer that does not incorporate a ROM inside the LSI, the boot address indicates the LSI external space, and a ROM is usually connected here.

  When the holding RAM boot signal is given from the power control unit 108, the address switcher 102 switches the boot address to another address. Specifically, the address originally pointing to the external ROM 114 is switched to the holding RAM 104.

  The booting instruction register 701 outputs a booting signal after the internal reset signal is applied until the boot process is completed. The boot-in-progress signal is set by an internal reset signal and reset (cleared) by a boot end signal. The boot end signal is output in the cycle in which the SP initial value read access is accepted by the high-speed bus. This signal can be easily generated by observing the address output from the CPU 101 and a signal (not shown) indicating access acceptance on the high-speed bus.

  When the holding RAM boot signal is given during the output of the booting signal, the boot address selector 702 replaces the upper bits of the address output by the CPU 101 with the switching address and outputs it to the high-speed bus. The switching address is a fixed value embedded in the address switch 102 and is a value indicating the area of the holding RAM 104.

  FIG. 8 is a diagram illustrating a register configuration in the power control unit 108. Processing related to the operation during the deep standby in the power control unit 108 and the operation when returning from the deep standby will be described.

  The power control unit 108 includes a deep standby control register and a terminal holding release register. These registers are initialized to “0” by an external reset, and can be accessed by the CPU 101 via the system bus.

  The RAMBOOT bit in the deep standby control register is a bit indicating whether or not to boot from the holding RAM 104 when returning from deep standby, and this bit serves as a holding RAM boot signal. When the RAMBOOT bit is “0”, the external ROM 114 is booted without booting from the holding RAM 104. When the RAMBOOT bit is “1”, the storage RAM 104 is booted.

  The CS0KEEP bit in the deep standby control register is a bit indicating whether or not to hold the terminal state of the IO buffer 110b related to the external bus in the deep standby mode. When the CS0KEEP bit is “0”, the terminal state is not held during deep standby (the IO buffer 110b is in a high impedance state). When the CS0KEEP bit is “1”, the pin state is retained during deep standby.

  The IOKEEP bit in the deep standby control register is a bit indicating whether or not to hold the terminal state of the IO buffer 110a other than that related to the external bus in the deep standby mode. When the IOKEEP bit is “0”, the IO buffer 110a is in a high impedance state without holding the terminal state during deep standby. When the IOKEEP bit is “1”, the pin state is retained during deep standby.

  The KEEPCLR bit in the terminal holding release register is a bit for releasing the terminal state holding. The pin holding state is released by writing "1" to this bit.

FIG. 9 is a schematic diagram showing the configuration of the IO buffers 110a and 110b with terminal holding function.
When both the input enable 1 and the input enable 2 are at the H level, the IO buffers 110a and 110b are in an input state, and an input signal applied to the PAD from the outside of the LSI is transmitted to the input terminal in the LSI.

  When both the output enable 1 and the output enable 2 are at the H level, the IO buffers 110a and 110b are in the output state, and the signal given to the output terminal in the LSI is output from the PAD terminal. That is, when the L level is given to the output terminal in the LSI, the L output state is set, and when the H level is given to the output terminal in the LSI, the H output state is set.

  When both the logical product of input enable 1 and input enable 2 and the logical product of output enable 1 and output enable 2 are false, the IO buffers 110a and 110b are in a high impedance state. At this time, the signal at the output terminal in the LSI is not transmitted to the PAD, and the signal given to the PAD from the outside of the LSI is not transmitted to the input in the LSI.

  In FIG. 9, LATs 901a and 901b are data latches. When the L level is given to the state holding terminal, the signal given from the booster circuit is transmitted to the right as it is. When the H level is given to the state holding terminal, the data latch holds the previous value. In other words, when the H level is given for the state holding, the signal change given to the output in the LSI, the output enable 1 and the output enable 2 is ignored. In this state, the L output state or the H output state does not change to another state, or the other state does not change to the L output state or the H output state. That is, the terminal state when viewed from the outside of the LSI is maintained. This state is referred to as a terminal holding state.

  The step-down circuit 902 and the step-up circuits 903a to 903d are circuits for converting the voltage level of the signal, but the details are omitted. For example, the internal power supply 1 is 1.2V, and the IO power supply is 3.3V.

  Here, the input in LSI, input enable 1, output in LSI, and output enable 1 are connected to a block for inputting / outputting signals to / from the outside of the LSI using this IO buffer, such as an external bus controller and input / output device # 0. Input enable 2, output enable 2, and state retention are connected to the power control unit 108. That is, the power control unit 108 can force the IO buffer to a high impedance state or a terminal holding state by giving appropriate values to these terminals.

  10 and 11 are waveform diagrams showing control timings related to terminal holding in the power control unit 108. FIG. 10 shows a case without terminal holding and FIG. 11 shows a case with terminal holding. Here, the deep standby mode signal is a signal generated internally by the power control unit 108 and is asserted when the transition to the deep standby mode is started, and is negated while returning from the deep standby and asserting the internal reset signal. The

  As shown in FIG. 10, when the terminal state is not held, the input enable 2 and the output enable 2 are negated at the same timing as the deep standby mode signal. As a result, the IO buffers 110a and 110b enter a high impedance state.

  As shown in FIG. 11, when holding the terminal state, the state holding signal is asserted in synchronization with the rising edge of the deep standby mode signal, and in synchronization with writing “1” to the KEEPCLR bit in the terminal holding release register. Negated. The values of input enable 2 and output enable 2 can be any value.

  FIG. 12 is a waveform diagram showing control timing related to terminal holding in the power control unit 108, and shows a case where the RAMBOOT bit in the deep standby control register is “0” and the CS0KEEP bit is “1”. When the RAMBOOT bit in the deep standby control register is "0" and the CS0KEEP bit is "1", the negation timing of the state holding signal of the external bus IO buffer 110b is slightly different. The state hold signal for the external bus is negated in synchronization with the fall of the deep standby mode signal without waiting for writing “1” to KEEPCLR. This is because when the RAMBOOT bit is “0”, it is necessary to perform the boot processing from the external ROM 114 immediately after the internal reset is negated, and therefore it is necessary to release the terminal holding state before that.

  FIG. 13 is a block diagram showing a configuration of a microcomputer according to another embodiment of the present invention. In the configuration of FIG. 1, there is an address switch 102 between the CPU 101 and the high-speed bus, but the address switch 102 may be between the bus bridge 111 and the system bus as shown in FIG. That is, it suffices if it is closer to the CPU 101 than the system bus.

  FIG. 14 is a diagram showing an example in which the internal power supply 2 is further subdivided. In the above example, the case where there are only two types of internal power supplies has been shown, but it may be further subdivided.

  For example, as shown in FIG. 14, the holding RAM 104 is divided into four, and different power sources are supplied to each. With respect to these power sources, whether or not to supply power in the deep standby mode is determined according to the setting of the power cutoff control register provided in the power control unit 108. The VDD3OFF bit to the VDD5OFF bit correspond to the internal power supply 3 to the internal power supply 5, and the power supply in which these bits are set to “1” is cut off in the deep standby mode. Of course, there may be other division methods. In this way, by further dividing the internal power supply, a plurality of internal power supplies can be individually controlled, and efficient low power consumption can be achieved.

  As described above, the microcomputer according to the present embodiment is a semiconductor integrated circuit having a low power consumption mode that cuts off a part of the internal power supply, and a boot address when returning from the low power consumption mode to the normal mode. Can be selected, and one of the selected boot addresses is a device (external ROM) connected to the outside of the semiconductor integrated circuit, and the other is a storage element (holding RAM) inside the semiconductor integrated circuit. It is characterized by that. Therefore, when returning from the low power consumption mode to the normal mode, it is possible to boot from the holding RAM, so it is possible to shut off the power of the external ROM in the low power consumption mode, and realize low power consumption. Can do.

  In addition, the microcomputer according to the present embodiment can select the state of the input / output terminal in the low power consumption mode in which a part of the internal power supply is cut off, and the terminal immediately before the transition of one state to the low power consumption mode. It is the maintenance of the state. Therefore, since the terminal state immediately before the transition to the low power consumption mode can be maintained, the indeterminate state of the input / output terminals in the low power consumption mode can be avoided, the malfunction can be prevented, and the reliability can be improved. Can be planned.

  Although the invention made by the present inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the scope of the invention. Needless to say.

  The present invention can be used in the manufacturing industry of semiconductor devices, electronic devices, and the like.

It is a block diagram which shows the structure of the microcomputer by one embodiment of this invention. It is a block diagram which shows the clock structure of the microcomputer by one embodiment of this invention. It is a figure which shows the outline | summary of the low power consumption mode of the microcomputer by one embodiment of this invention. It is a wave form diagram which shows operation | movement of a sleep mode among low power consumption modes. It is a wave form diagram which shows operation | movement of software standby mode among low power consumption modes. It is a wave form diagram which shows operation | movement of deep standby mode among low power consumption modes. It is a figure which shows the structure of an address switch. It is a figure which shows the register structure in an electric power control part. It is a schematic diagram which shows the structure of IO buffer with a terminal holding | maintenance function. It is a wave form diagram which shows the control timing regarding terminal holding | maintenance in an electric power control part (in the case of no terminal holding). It is a wave form diagram which shows the control timing regarding terminal holding | maintenance in an electric power control part (in the case of terminal holding | maintenance). It is a wave form diagram which shows the control timing regarding terminal holding | maintenance in a power control part (when a RAMBOOT bit is "0" and a CS0KEEP bit is "1"). It is a block diagram which shows the structure of the microcomputer by other embodiment of this invention. FIG. 3 is a diagram showing an example in which the internal power supply 2 is further subdivided.

Explanation of symbols

100 Microcomputer 101 CPU
102 Address switch 103 High-speed RAM
104 Retention RAM
105 I / O Device 106 External Bus Controller 107 Power Supply Circuit 108 Power Control Unit 109 Reset / Interrupt Control Unit 110 IO Buffer 111 Bus Bridge 112 Clock Generator 113 RAM
114 ROM
115 ASIC
701 Booting instruction register 702 Boot address selector 901 LAT
902 Step-down circuit 903 Step-up circuit

Claims (5)

A CPU operating with a first internal power supply;
Comprising a RAM operating with a second internal power supply,
Supplying a first internal power source and a second internal power source, and a first operation mode in which a clock of the CPU operates;
Supplying a first internal power supply and a second internal power supply, and a second operation mode in which a clock of the CPU is stopped;
A third operation mode in which the first internal power supply is shut off, the second internal power supply is supplied, and the clock of the CPU is stopped;
Means for selecting a boot address at the time of returning from the third operation mode to the first operation mode, and one of the selected boot addresses is a memory connected to the outside;
The microcomputer is characterized in that the other is the RAM. The microcomputer according to claim 1.
The RAM is a low speed RAM,
The microcomputer further comprises a high-speed RAM that operates at a higher speed than the low-speed RAM. The microcomputer according to claim 1.
The microcomputer further comprises an input / output terminal having a function of holding a terminal state immediately before the transition to the third operation mode. The microcomputer according to claim 1.
The microcomputer, wherein the second internal power supply is further divided into a plurality of internal power supplies. The microcomputer according to claim 1.
The microcomputer is a semiconductor integrated circuit formed on one semiconductor chip.

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