JP2009259114A - System semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stop supplying a clock corresponding to an entry not used for entering a low-power consumption mode when a system memory enters the low-power consumption mode. <P>SOLUTION: A memory controller 12 includes a command buffer 21, a control register 22, a bank sequencer 23, a control signal generating circuit 24, and a clock gating circuit 25. In a normal mode, a clock gating circuit 25 outputs a clock signal CLK1 to a command queue 31 and a writing data queue 32 which are arranged in the command buffer 21, based on a Disable control signal Ssr to be input. In shifting from the normal mode to the low-power consumption mode, the control signal Ssr to be input is enabled. Thus, the clock gating circuit 25 stops supplying to the command buffer 21 the clock signal other than the clock signal CLK1 corresponding to one entry. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a system semiconductor device.

  With the progress of miniaturization, high integration, and low power consumption of semiconductor elements, many system semiconductor devices incorporating a data processing device, a memory controller, a data processing controller, and the like have been developed. The data processing device is also called a processor or a microprocessor, and the system semiconductor device is also called a SoC (System On a Chip) or a system LSI (see, for example, Patent Document 1).

In an embedded system in which a system semiconductor device, a system memory, and the like described in Patent Document 1 are incorporated, area saving, cost reduction, and power consumption reduction are required. Conventionally, in a system semiconductor device incorporating a memory controller, when the system memory shifts from the normal mode to the low power consumption mode, data transfer access from the data processing device is limited to a control register provided in the memory controller. Access to is not performed. However, a clock signal other than a clock signal corresponding to one entry required is also input to the command queue and write data queue provided in the memory controller. For this reason, there is a problem that extra power is consumed.
JP 2007-108882 (page 22, FIGS. 1 and 2)

  The present invention provides a system semiconductor device capable of stopping supply of a clock corresponding to an entry other than an entry used for shifting to a low power consumption mode when the system memory shifts to a low power consumption mode. .

  A system semiconductor device according to one embodiment of the present invention includes a built-in memory that stores data, an arithmetic unit, and a memory management unit, a data processing device that generates an access request to the system memory, and a multi-entry command queue and write A command buffer having a data queue; a control register for controlling data transfer; a control signal output from the control register; and a clock signal supply stopping means for outputting an output signal to the command buffer. And a memory controller that receives an access request to the system memory from the data processing device and transfers data to the system memory. In the normal mode, the clock signal stopping means is based on the control signal. Output the clock signal to the command buffer The clock signal stopping unit outputs a clock signal corresponding to one entry of the command queue and the write data queue to the command buffer based on the control signal when shifting to the low power consumption mode, and corresponds to the other entries. The supply of the clock signal to the command buffer is stopped.

  According to the present invention, when the system memory shifts to the low power consumption mode, the system semiconductor device capable of stopping the supply of the clock corresponding to the entry other than the entry used for shifting to the low power consumption mode is provided. Can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a system semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embedded system device. In this embodiment, when the system memory shifts to the low power consumption mode, the clock gating circuit is used as means for stopping the supply of clocks corresponding to entries other than the entry used for shifting to the low power consumption mode. It is provided in a semiconductor device.

  As shown in FIG. 1, the embedded system device 50 is provided with a system semiconductor device 1 and a system memory 2. The embedded system device 50 is connected to, for example, various built-in devices (for example, office office devices) via an interface (not shown), and comprehensively controls the various built-in devices.

  The system semiconductor device 1 is also called SoC (System On a Chip) or system LSI. The system semiconductor device 1 is provided with a data processing device 11, a memory controller 12, an interface I / F1, and an interface I / F2.

  The data processing device 11 is also called a processor or a microprocessor. The data processing apparatus 11 has a built-in memory for storing data, an arithmetic unit, a memory management unit, etc. (not shown), functions as a main engine (overall control) of peripheral devices, and requests access to the system memory 2 The data is output to the memory controller 12 via the interface I / F1.

  The memory controller 12 performs data transfer control between the data processing device 11 and the system memory 2. The memory controller 12 is connected to the system memory 2 via the interface I / F2. The memory controller 12 is provided with a command buffer 21, a control register 22, a bank sequencer 23, a control signal generation circuit 24, and a clock gating circuit 25.

  The system memory 2 is a synchronous circuit that is easy to design and uses a high-capacity SDRAM (Synchronous Dynamic Random Access Memory) with high cost performance for continuous data string access. Instead of the SDRAM, a DDR (Double Data Rate) SDRAM or a DDR2 SDRAM capable of high-speed data transfer may be used.

  The command buffer 21 is provided between the interface I / F 1 and the bank sequencer 23, and an access request to the system memory 2 is input from the data processing device 11. The command buffer 21 is provided with a command queue 31 that can store a plurality of commands and a write data queue 32 that can store a plurality of write data. The command queue 31 and the write data queue 32 are provided with a plurality of entries (for example, registers).

  One command corresponding to a burst unit of the system memory 2 can be stored in one entry of the command queue 31. In one entry of the write data queue 32, write data corresponding to the data width of the data processing device 11 and the interface I / F 2 can be stored.

  Here, since the SDRAM is used as the system memory 2, the system memory 2 corresponding to the subsequent command is issued before the write / read command of the system memory 2 corresponding to a certain command is issued by the command queue 31 having a plurality of entries. It is possible to issue a precharge / active command. In addition, the presence of the multi-entry write data queue 32 can improve the performance of write burst transfer.

  The control register 22 is provided between the command buffer 21 and the clock gating circuit 25 and is provided with a plurality of registers that control data transfer and define the operation of the memory controller 12. The control register 22 is provided with a register for managing whether the system memory 2 is in a normal mode in which the system memory can be accessed or a low power consumption mode such as self-refresh that does not perform system memory access. The control register 22 outputs a control signal Ssr for controlling whether or not to transmit the clock signal CLK1 to the command buffer 21 to the clock gating circuit 25.

  In the normal mode, all entries in the command queue 31 and the write data queue 32 operate. However, in the low power consumption mode mode, only one entry operates, and the other entries are controlled so as not to change at all. The

  The bank sequencer 23 is provided between the command buffer 21 and the control signal generation circuit 24. A sequencer corresponding to each bank of the system memory 2 is provided, and the sequencer manages each bank state.

  The control signal generation circuit 24 is provided between the bank sequencer 23 and the interface I / F 2, receives a data transfer command and write data for the system memory 2, generates a control signal for the system memory 2, and performs system memory access. Realize.

  The clock gating circuit 25 functions as a clock signal supply stop unit, is provided between the control register 22 and the command buffer 21, and receives the clock signal CLK1 and the control signal Ssr output from the control register 22, and receives the control signal Ssr. The gated clock signal CLKG is output to the command queue 31 and the write data queue 32 provided in the command buffer 21 based on the above. When the control signal Ssr is disabled, the clock signal CLK1 is output from the clock gating circuit 25. When the control signal Ssr is Enable, the supply of the clock signal CLK1 from the clock gating circuit 25 to the command buffer 21 is stopped.

  Next, data transfer of the data processing apparatus will be described with reference to FIGS. FIG. 2 is a diagram showing a flow of data transfer to the system memory, and FIG. 3 is a diagram showing a flow of data transfer to the control register.

  As shown in FIG. 2, when the data processing device 11 performs data transfer in the normal mode to the system memory 2, for example, in the case of write data transfer, first, a command and write data are sent from the data processing device 11 to the interface I / O. The data is transferred to the command buffer 21 via F1.

  Next, the command and write data are transferred to the bank sequencer 23 via the command queue 31 and the write data queue 32 provided in the command buffer 21.

  Subsequently, the command and the write data are transferred to the signal generation circuit 24, and transferred from the signal generation circuit 24 to the system memory 2 via the interface I / F2.

  As shown in FIG. 3, when the data processing device 11 executes data transfer to the control register 22 (such as shifting to the low power consumption mode), for example, in the case of write data transfer, the data processing device 11 sends a command and write Data is transferred to the command buffer 21 via the interface I / F1.

  Then, the command and the write data are transferred to the control register 22 via the command queue 31 and the write data queue 32 provided in the command buffer 21.

  Next, the low power consumption mode of the system memory will be described with reference to FIGS. FIG. 4 is a timing chart showing the transition from the normal mode to the self-refresh mode, and FIG. 5 is a timing chart showing the transition from the self-refresh mode to the normal mode. Here, the transition from the normal mode to the self-refresh mode and the transition from the self-refresh mode to the normal mode can be handled by using one entry of the command queue and the write data queue, and no extra entry is required. The low power consumption mode includes a sleep mode and a standby mode in addition to the self-refresh mode.

  As shown in FIG. 4, in the normal mode, the control signal Ssr output from the control register 22 to the clock gating circuit 25 is “Low” level of Disable, and the command queue 31 in which the clock signal CLK 1 is provided in the command buffer 21. The command A1 and the like are transferred to the interface I / F1, and the command A11 and the like are transferred to the interface I / F2.

  Next, the low power consumption mode entry command AA1 necessary for shifting to the low power consumption mode such as the self-refresh mode is transferred from the data processing apparatus 11 to the interface I / F1. The low power consumption mode entry command AA1 is transferred to the control register 22 via the command buffer 21. In response to the low power consumption mode entry command AA1, the control register 22 changes the control signal Ssr output to the clock gating circuit 25 from “Low” level of Disable to “High” level of Enable.

  The clock gating circuit 25 transmits only the clock signal CLK1 corresponding to one entry of the command queue 31 and the write data queue 32 to the command buffer 21 based on the Enable control signal Ssr. Based on the Enable control signal Ssr, the clock gating circuit 25 stops the supply of the clock signal CLK1 corresponding to the other entry to the command buffer 21.

  The command buffer 21 is controlled as having only one entry of the command queue 31 and the write data queue 32. The low power consumption mode entry command AA1 is transferred to the interface I / F2 with a delay from the interface I / F1, and no system memory access is performed.

  In the interface I / F1, commands issued after the low power consumption mode entry command AA1 are always stored in one specific entry, and are not stored in other entries. In the interface I / F2, no system memory access command is issued after the low power consumption mode entry command AA1. For this reason, generation | occurrence | production of the excess electric power in the system semiconductor device 1 and the system memory 2 can be suppressed.

  As shown in FIG. 5, in the low power consumption mode such as the self-refresh mode, no command is transferred to the interfaces I / F1 and I / F2. When shifting from the low power consumption mode such as the self-refresh mode to the normal mode, the low power consumption mode exit command BB1 necessary for returning to the normal mode is transferred from the data processing device 11 to the interface I / F1. The low power consumption mode exit command BB1 is transferred to the control register 22 via the command buffer 21. The control register 22 changes the control signal Ssr output to the clock gating circuit 25 from the “High” level of Enable to the “Low” level of Disable in response to the low power consumption mode exit command BB1.

  The clock gating circuit 25 receives the disable control signal Ssr, and then, based on the disable control signal Ssr, the clock signal corresponding to the entry used to return the command queue 31 and the write data queue 32 to the normal mode. CLK1 is transmitted to the command buffer 21. Further, the low power consumption mode exit command BB1 is transferred to the interface I / F2 with a delay from the interface I / F2, and system memory access is performed. After the low power consumption mode exit command BB1 is transferred, the command B2 is transferred to the interface I / F1, and the command B12 is transferred to the interface I / F2.

  As described above, in the system semiconductor device of this embodiment, the embedded system device 50 is provided with the system semiconductor device 1 and the system memory 2. The system semiconductor device 1 is provided with a data processing device 11, a memory controller 12, an interface I / F1, and an interface I / F2. The memory controller 12 is provided with a command buffer 21, a control register 22, a bank sequencer 23, a control signal generation circuit 24, and a clock gating circuit 25. The clock gating circuit 25 is provided between the control register 22 and the command buffer 21, and receives the clock signal CLK1 and the control signal Ssr output from the control register 22. In the normal mode, the clock gating circuit 25 outputs the clock signal CLK1 to the command queue 31 and the write data queue 32 provided in the command buffer 21 based on the input disable control signal Ssr. At the time of transition from the normal mode to the low power consumption mode, the control signal Ssr input to the clock gating circuit 25 becomes Enable, and the clock gating circuit 25 sends a signal other than the clock signal CLK1 corresponding to one entry to the command buffer 21. Stop supplying.

    For this reason, when the transition from the normal mode to the low power consumption mode is performed, the clock signal CLK1 other than that required is not supplied, so that no extra power is consumed in the system semiconductor device 1, so that the power consumption can be reduced. .

  In the present embodiment, the data processing device 11 has a central processing unit (CPU Central Processing Unit) function. However, a separate CPU may be provided, and the data processing device 11 may have only a data processing function. .

  Next, a system semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram showing an embedded system device. In this embodiment, the configuration of the memory controller is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 6, the embedded system device 50a includes a system semiconductor device 1a and a system memory 2. The embedded system device 50a is connected to, for example, various built-in devices via an interface (not shown), and performs overall control of the various built-in devices.

  The system semiconductor device 1a is also called SoC or system LSI. The system semiconductor device 1a includes a data processing device 11, a memory controller 12a, an interface I / F1, and an interface I / F2.

  The memory controller 12 a performs data transfer control between the data processing device 11 and the system memory 2. The memory controller 12a is provided with a command buffer 21, a control register 22, a bank sequencer 23, a control signal generation circuit 24, and a switch 26.

  The control register 22 outputs a control signal Ssra for controlling whether or not to transmit a clock signal to the command buffer 21 to the switch 26. When shifting from the normal mode to the self-refresh mode, the control signal Ssra is different from the change in the signal level of the control signal Ssr of the first embodiment, and the clock signal CLK1 corresponding to one entry of the command queue 31 and the write data queue 32. Is output to the command buffer 21, the Disable “Low” level is changed to the Enable “High” level. Further, when shifting from the self-refresh mode to the normal mode, the control signal Ssra is changed from “High” level of Enable to “Low” level of Disable with a delay corresponding to one entry.

  The switch 26 is an SPDT (Single Pole Double Throw) switch, to which a control signal Ssra is input, the pole side is connected to the command queue 31 and the write data queue 32 of the command buffer 21, and the throw side is The signal line to which the clock signal CLK1 is transmitted is connected to the low potential side power supply (ground potential) Vss. Based on the control signal Ssra, the switch 26 connects the signal line to which the clock signal CLK1 is transmitted, the command queue 31 and the write data queue 32, or the low potential side power supply (ground potential) Vss, the command queue 31 and the write data queue. One of the 32 connections is selected, and the signal S1 is output to the command queue 31 and the write data queue 32.

  The switch 26 functions as a clock signal supply stop unit. When the control signal Ssra is “Low” level of Disable, the clock signal CLK1 is output to the command queue 31 and the write data queue 32 as the signal S1, and the control signal Ssr is enabled. At the “High” level, the signal S 1 at the low potential side power supply (ground potential) Vss level is output to the command queue 31 and the write data queue 32.

  That is, the switch 26 performs the same operation as the clock gating circuit 25 of the first embodiment.

  As described above, in the system semiconductor device of this embodiment, the embedded system device 50a is provided with the system semiconductor device 1a and the system memory 2. The system semiconductor device 1a includes a data processing device 11, a memory controller 12a, an interface I / F1, and an interface I / F2. The memory controller 12a is provided with a command buffer 21, a control register 22, a bank sequencer 23, a control signal generation circuit 24, and a switch 26. The switch 26 is provided between the control register 22 and the command buffer 21, and receives the clock signal CLK1 and the control signal Ssra output from the control register 22. In the normal mode, the switch 26 outputs the clock signal CLK1 to the command queue 31 and the write data queue 32 provided in the command buffer 21 based on the input disable control signal Ssra. At the time of transition from the normal mode to the low power consumption mode, the control signal Ssra inputted to the switch 26 becomes Enable, and supply to the command buffer 21 other than the clock signal CLK1 corresponding to one entry is stopped.

  For this reason, when the transition from the normal mode to the low power consumption mode is performed, the clock signal CLK1 other than that required is not supplied, so that no extra power is consumed in the system semiconductor device 1a, so that the power consumption can be reduced. .

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, the system semiconductor device and the system memory are connected via an interface, but the system semiconductor device and the system memory may be connected via a system bus. Further, a coprocessor that can be defined by the user may be provided in the data processing apparatus.

1 is a block diagram illustrating an embedded system device according to a first embodiment of the invention. The figure which shows the flow of the data transfer to the system memory which concerns on Example 1 of this invention. FIG. 3 is a diagram showing a flow of data transfer to a control register according to the first embodiment of the present invention. 3 is a timing chart showing a transition from a normal mode to a self-refresh mode according to Embodiment 1 of the present invention. 3 is a timing chart showing a transition from the self-refresh mode to the normal mode according to the first embodiment of the present invention. The block diagram which shows the embedded system apparatus which concerns on Example 2 of this invention.

Explanation of symbols

1, 1a System semiconductor device 2 System memory 11 Data processing device 12, 12a Memory controller 21 Command buffer 22 Control register 23 Bank sequencer 24 Control signal generator 25 Clock gating circuit 26 Switch 31 Command queue 32 Write data queue 50, 50a System device CLK1 Clock signal CLKG Gated clock signal I / F1, I / F2 Interface S1 Signal Ssr, Ssra Control signal Vss Low potential side power supply (ground potential)

Claims (5)

A data processing device having a built-in memory for storing data, an arithmetic unit, and a memory management unit, and generating an access request to the system memory;
A command buffer having a multi-entry command queue and a write data queue, a control register for controlling data transfer, a control signal and a clock signal output from the control register, and a clock for outputting an output signal to the command buffer A memory controller that receives a request to access the system memory from the data processing device and transfers data to the system memory;
The clock signal stop means outputs the clock signal to the command buffer based on the control signal in the normal mode, and the clock signal stop means controls the control in the transition to the low power consumption mode. A system that outputs a clock signal corresponding to one entry of a command queue and a write data queue to the command buffer based on the signal, and stops supplying a clock signal corresponding to another entry to the command buffer. Semiconductor device.   The memory controller is provided with a sequencer for each bank of the system memory, and a bank sequencer that manages the state of each bank, a data transfer command to the system memory, and write data are input to control the system memory The system semiconductor device according to claim 1, further comprising: a control signal generation circuit that generates a signal and realizes system memory access.   3. The clock signal stop unit restarts the supply of the clock signal to the command buffer based on the control signal when shifting from the low power consumption mode to the normal mode. System semiconductor devices.   4. The system semiconductor device according to claim 1, wherein the clock signal stopping means is a clock gating circuit or an SPDT switch.   5. The system semiconductor device according to claim 1, wherein the system memory is an SDRAM, a DDR SDRAM, or a DDR2 SDRAM.

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