JP2001202155A - Low power consumption processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To finely control power consumption of a processor by enabling high speed, smooth and dynamic switching of multiple clocks and further enabling high speed and dynamic switching of multiple CPUs. SOLUTION: High speed and smooth switching of clocks is realized by generating a switching signal 15 the clock levels of which before and after switching are the same and which is synchronized with a standard clock CL by a clock switching control circuit 13, taking out a clock from a PLL clock driver 12 by selecting it by a multiplexer 14 by the switching signal 15. The switching is dynamically executed by outputting select signals SELA, SELB by execution of an instruction of the CPU. In the switching between CPUs 20, 30, when the CPU under operation executes a switching instruction of the CPUs, supply of clocks to other CPUs is started, the present CPU enters a stopped state and the CPUs to which the clocks are supplied stop the clocks of other CPUs and starts operation of the present CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing device with a built-in CPU aiming at power saving.

[0002]

2. Description of the Related Art In recent years, the functions and performances of computer systems, mainly personal computer systems such as microcomputers / PCs and laptop PCs, have been improved, and the power consumed by these processors has been rapidly increasing. And it is becoming a problem in various aspects. General industrial, OA, scientific and technological calculation, embedded processing and control processing devices also suffer from problems such as adverse effects on the natural environment, power costs, environmental costs, power supply conditions, etc. It can be expected that demand for power saving will increase in the future. Particularly in a handheld (portable) processing device such as a laptop personal computer, the power supply is often provided by a battery in the usage environment, and it is essential to save power, which is directly connected to the available time.

Conventionally, in a personal computer (PC) aiming at power saving, the following two methods have been proposed as the most effective methods for power saving. One of them is to prepare a low-speed clock and a high-speed clock, as disclosed in Japanese Patent Application Laid-Open No. 8-241145, and to provide an idle state (a state in which the PC is not executing valid processing) and a back cloud processing (priority order). Low-speed processing)
The other is to reduce the operating power by switching the power supply to a low-speed CPU chip (generally having low power consumption) and a high-speed chip as disclosed in Japanese Patent Application Laid-Open No. 11-7344. (Generally consumes large power), the bus from the two CPUs is connected in common, and when processing that does not cause any problem even at low speed processing is switched to the low speed CPU chip side, the operating power is reduced. It is. Japanese Patent Laid-Open No. 10-9 discloses a technique that enables smooth clock switching by switching the clock speed.
No. 1272 and the like.

[0004]

The prior art has the following problems, and the solution is a problem. (A) In recent years, the internal operating frequency of CPUs has become extremely high (300 to 600 MHz), and it is substantially impossible to smoothly switch clocks outside the CPU (on a board or the like). In this regard, the prior art does not disclose any solution. (B) It is required to reduce power consumption by fine power control. However, the conventional technology has a large overhead of clock switching and CPU switching, and cannot meet the demand. (C) In the prior art for switching the CPU, a general C
It is premised that a PU chip is used, and the overhead of matching processing of internal information between CPUs is large, and it is difficult to perform a detailed switching processing operation. (D) A high-speed CPU uses a high-speed technology such as a cache memory or a high-speed bus system.
Does not disclose any conventional technology regarding the handling of the high-speed technology and the newly required architecture.

SUMMARY OF THE INVENTION An object of the present invention is to provide a processing device capable of switching clocks and CPUs in a smooth and small manner with a small overhead and finely, and also capable of switching a cache memory and a bus in a short time to greatly reduce power consumption. It is in.

[0006]

According to the present invention, there is provided a PLL clock driver for generating a plurality of clocks having different frequencies in synchronization with a given reference clock, and a clock generated by the PLL clock driver. A clock switching multiplexer for selecting one according to the input switching signal and outputting the selected clock after the switching;
The clock switching multiplexer generates a signal corresponding to a clock switching selector signal provided at a timing synchronized with the reference clock, wherein the pre-switching clock selected before switching and the post-switching clock are at the same signal level. A clock switching unit that outputs the signal as the switching signal to the clock switching multiplexer; and a CPU that operates in response to a clock output output from the clock switching multiplexer. A power consumption processing device is disclosed.

Further, according to the present invention, in the above low power consumption processing device, the clock switching means is synchronized with a synchronizing flip-flop for synchronizing the selector signal with a clock synchronized with a reference clock, and is synchronized with the flip-flop. The selector signal is active, and the state is set at the timing when the pre-switching clock and the post-switching clock have changed to the same level, the selector signal is inactive, and the switching is performed with the pre-switching clock. A low-power consumption processing device, comprising: a flip-flop for selection, the state of which is reset at the timing when the subsequent clock changes to the same level, and transmitting the output of the flip-flop for selection as the switching signal. I do.

Further, according to the present invention, a low power consumption processing device is provided as a first device.
A second processing device that includes a processing device and includes a CPU that consumes lower power than a CPU included in the first processing device; and each CP in the first processing device and the second processing device.
CP for keeping information between U register files the same
U interface means, a first cache memory system connected to the CPU of the first processing device, first cache memory control means for controlling the first cache memory system, CPU of the first processing device, and first cache memory A first bus means including a bus control means input / output via the system; a second bus means including a bus control means from a CPU of the second processing device; and a first bus means and a second bus means. Bus switch interface means for switching in response to the bus control means from the processing device and the second processing device to input and output an external bus and an external control signal at a timing suitable for an external resource; Selecting and operating one of the second processing devices,
There is disclosed a low power consumption processing device including: a mode switching unit that stops a CPU in a processing device that is not selected or keeps the CPU in an idle state.

Further, according to the present invention, in the above low power consumption processing device, the mode switching means is incorporated in the first and second processing devices, and one of the first and second processing devices during operation is provided. When the operation is shifted from the processing device to the other processing device, the mode switching means of the operating processing device controls the other processing device to stop or to release the idle state and to control the processing device to shift to the idle state. Then, the mode switching means of the other processing device activated by this controls the clock supply to the processing device that was operating so far, and the other processing device was operating so far. Disclosed is a low-power consumption processing device that is controlled to operate while taking over the state of the processing device.

Further, according to the present invention, in the above low power consumption processing device, when the operating processing device rewrites its own register file, the register file of the stopped processing device is also matched to the rewriting result. Disclosed is a low power consumption processing device characterized by rewriting via an interface between CPUs.

Further, in the low power consumption processing apparatus according to the present invention, the CPU may issue a clock switching selector signal to dynamically switch a clock frequency, and the CPU may control the processing apparatus by the mode switching means. Disclosed is a low power consumption processing device provided with at least one of CPU switching instructions for dynamically switching.

[0012]

Embodiments of the present invention will be described below in detail. First, considering the power consumption of a computer, the power consumption is mainly proportional to the processing capacity of the CPU. In other words, the power consumption of the CPU of the computer system has been increasing under the following circumstances, and it is considered that it will continue to increase in the future.

(1) The CPU is required to have a processing capability of executing a large-scale functional program such as an OS, which is increasing year by year, without stress, and the functional hardware for that purpose and the CPU for directly increasing the CPU processing speed are required. The amount of hardware (such as pipelines, cache memories and their control hardware) has been increasing accordingly. This means that the switching amount of the transistor per unit time is increased.
Since the power consumption of a recent process-based CPU is proportional to the switching amount of the transistor, the power consumption is increased.

(2) As a main technology for speeding up a CPU, a CMOS process is miniaturized (in recent years, 0.1 to
A 0.2 μm process is being used) to achieve high integration and an improvement in the switching speed of a transistor.
A technique for improving the frequency of the clock supplied to the core) is awaited. In recent years, it is not uncommon for a 500 MHz class clock to be used inside a CPU chip. The high integration characteristic of the process is used for parallelization of hardware and the like, and contributes to a reduction in latency of a pipeline or the like, that is, an improvement in a clock frequency due to a synergistic effect with an improvement in switching speed. However, the switching amount of the transistor described in (1) increases synergistically, leading to a significant increase in power consumption.

(3) As a method of reducing power consumption when designing a CPU, a low power consumption mode for controlling power by stopping a clock when the CPU does not need to operate is provided, and a low voltage operation ( 3.3V, 2.2V, etc.) are currently used. However, the former is not power saving for an effective processing time because power consumption is not reduced during normal operation. In addition, the latter is a technique that has greatly contributed to the reduction of power consumption in recent years.However, if the voltage is excessively reduced too much, the switching speed of the transistor or the driving capability itself may be reduced and the performance such as the operating speed of the CPU may be deteriorated. It is also considered undesirable in terms of signal noise margin.

In consideration of low power consumption and power saving in the CPU design of (1) to (3), the CPU of (3)
Except for the low voltage operation, how the number of effective switching gates (or the number of transistors) in the CPU per unit time can be reduced when the CPU is executing the effective processing,
It can be seen that this is a point of reducing the power consumption of the CMOS process high performance CPU. It is clear from (1) and (2) that the only way to achieve this is to combine the technique of reducing the number of effective operation transistors themselves by reducing the circuit logic scale with the technique of reducing the clock frequency. However, as described in (1) and (2), these methods are completely opposite to the performance enhancement of the CPU, and in order to avoid the inconsistency, processing that does not require much high-speed processing or It is necessary to provide a CPU architecture and an instruction set for power saving, which can effectively apply these methods to processing that can be regarded as substantial idle processing. In other words, any task or processing step can be freely and quickly responded to any of the various power consumption modes required during operation, and the power control operation can be controlled by a command in a program or an external command. It is necessary to provide a CPU that can freely and dynamically perform fine power reduction control that can be executed by the CPU. For example, a high power consumption CPU optimized for high speed operation and a low speed CPU optimized for low power consumption are integrated into one chip, which can be freely switched and operated, and given to each CPU. A power control instruction set that allows the basic clock frequency to be freely switched may be provided, and power control instructions may be finely arranged in a program according to a required operation speed.

FIG. 1 is based on the above policy.
FIG. 2 is a block diagram illustrating a configuration example of a low power consumption processing device according to the present invention.
And a low-speed CPU core 30 which is not so fast but consumes low power, and clock frequency switching circuits 10 and 70 which supply frequency-variable CPU clocks 11 and 81 to both CPU cores. However, low speed CPU
The clock 81 for the core may have a constant frequency, in which case the clock frequency switching circuit 70 is unnecessary. C
The PU cores 20 and 30 are connected via inter-CPU interface circuits 21 and 31 in each core, and are connected to two CPs.
It is used for coherency control between the register files 22 and 32 in the U core (control for maintaining the same contents) and for exchange of status information between CPU cores. Each CPU core may be provided with cache memories 40 and 50, respectively. In particular, for the high-speed CPU core 20, a cache memory system 40 capable of high-speed access for storing information on external resources 90 such as an external I / O and a memory system in order to improve processing efficiency is essential. There are many cases. External resources 90 (memory,
Bus means B1 and B2 from each CPU core exist to execute access to I / O, system bus, etc., but only the active one of the two CPU cores is connected to an external resource. Is provided with a bus switch interface 60. When the cache memory systems 40 and 50 are present, the bus means B1 and B2 once transmit the cache memory control signal C from the CPU core.
1 and C2 are connected to the cache memory systems 40 and 50, respectively, and input / output information from / to the external resource 90 via the bus switch interface 60 only when there is no information in the cache memory. In addition, both C
When the PU core has a cache memory, inter-cache interfaces 41 and 51 for performing coherency control between the cache memories are provided.

In the configuration shown in FIG. 1 described above, the clock frequency switching circuits 10 and 70 are provided for each of the CPU cores 20 and 30, and these change the clock frequency to each CPU core at the time ( A means for controlling the operation of each CPU core so as to optimally switch the processing speed and power consumption according to processing contents and environment) is provided.
By switching between the high-speed CPU core 20 and the low-speed CPU core 30 and dynamically controlling the entire processing apparatus so that the overall processing speed and power consumption become more optimum, the power management is more efficient than in the past. / Operation speed management can be performed dynamically during operation, and as a result, overall power consumption of the entire system can be reduced.

The clock frequency switching circuit 10 is a phase locked loop (PLL) for generating a plurality of clocks strictly synchronized with each other from a basic clock CL as a reference for operation.
A loop) clock driver 12, a clock switching multiplexer 14 for selecting one of a plurality of clocks 17 therefrom, and a switching control synchronous clock 16 (using any one of clocks 17) from a PLL clock driver. The switching signal 15 corresponding to the selector signal SELA is generated in synchronization with the
And a clock switching control circuit 13 for sending out the clock switching control signal. The multiplexer 14 supplies the clock 11 selected by the switching signal 15 to the CPU core 20,
0 operates based on the operation clock 11. The clock frequency switching circuit 70 has the same configuration, but the frequency of the output clock 81 is different.

In the configuration of the above clock frequency switching circuit 10, a clock driver 12 incorporating a PLL is used. This is because, when a plurality of clocks are generated by a simple dividing circuit as in the prior art, a) it is necessary to prepare the fastest clock for the external input, and b) the degree of freedom of the frequency that can be generated is low (1 , 1/2, 1/4, 1 /
8) times, and c) there is a problem that the output clock is delayed with respect to the basic clock. However, all these problems can be solved by using the PLL.
That is, even if the basic clock CL has a low frequency, a very high frequency clock is generated by the internal VCO, the frequency is divided, and the phase comparison with the basic clock may be performed. By configuring to generate a plurality of types of clocks using the internal clock from the VCO, the degree of freedom of the frequency that can be generated can be increased. Also V
A plurality of types of CO can be provided, and the degree of freedom of the frequency to be generated is further increased. Further, by returning a reference feedback clock to the PLL via a delay element corresponding to the delay amount of a multiplexer or the like, the delay of the target clock output can be removed or adjusted by removing the delay of the output clock with respect to the basic input clock. Or easier.

FIG. 2 shows an example of the configuration of the clock switching control circuit 13. In this circuit, the clock 17 from the PLL clock driver 12 is two clocks (a high-speed clock and a low-speed clock). Clock selection signal S
CIN is the selector signal SELA or SELB itself shown in FIG. 1 or a signal generated in response thereto, and is a signal synchronized with the synchronization clock 16 by flip-flops (FF) 107 and 106, that is, a PLL clock. The signals are strictly synchronized with the plurality of clocks 17 from the driver 12. This signal is taken out as two inverted outputs of the Q output and the QN output of the flip-flop 106 and input to the three-input NAND gates 102 and 101. The NAND gates 102 and 101 perform NAND logic of the high-speed clock and the low-speed clock, and the outputs of the NAND gates are sent to the set terminal S and the reset terminal R of the latch RS flip-flop 113 composed of the gates 104 and 103, respectively. Is entered. This R
The output of the gate 104, which is the output on the set side of the S flip-flop 113, is output to the clock switching multiplexer 14 as the clock switching signal 15.

FIG. 3 is a timing chart showing the operation of the clock switching control circuit 13 shown in FIG.
The high-speed clock has twice the frequency of the low-speed clock. These high-speed and low-speed clocks and the synchronization clock 16
Are all output synchronously from the PLL clock driver 12. The clock selection signal SCIN transits to the high level (time t0), and the clock selection signal SCIN is switched to the flip-flop 107,
Flip-flop 10 obtained by synchronization by 106
6, the clock switching signal 15 switches from the low level to the high level using the timing (time t1) when both the high-speed clock and the low-speed clock transition to the high level, and the clock output 1
1 is also switched from the high-speed clock to the low-speed clock.
Conversely, the clock selection signal SCIN transitions from the high level to the low level (time t2), and the QN output of the flip-flop 106 obtained by synchronizing the clock selection signal SCIN with the flip-flops 107 and 106 changes to the high level. The clock switching signal 15 is switched from the high level to the low level using the timing (time t3) at which both the high-speed clock and the low-speed clock transition to the high level. The clock output 11 is accordingly switched from the low-speed clock to the high-speed clock. However, since both the high-speed and low-speed clocks are already at the high level at time t3, the switching is performed immediately at the timing of the change of the clock switching signal 15. Here, switching timing t
1, t3 is an appropriate delay tc including a gate transit time between the synchronization clock 16 and the high-speed and low-speed clocks.
sd1 and tcsd2, and the change point is surely present when both the high-speed and low-speed clock levels are stably at the high level. As a result, occurrence of a hazard or the like at the time of switching is prevented.

As shown in FIG. 2, if the inverted clock 108 of the synchronization clock 16 or the clock 16 is delayed by the delay gate 109, or the timing is satisfied (the state of the A1 and A2 inputs of the multiplexer 14). If the signal 15 changes at a timing when the clock signal is stable), the output of the latch RS flip-flop is output using the synchronization clock 16 itself.
05 and adjusted so as to satisfy the above timing, the clock switching signal 15 may be used.
Similarly, a hazard or the like can be prevented.

FIG. 4 shows a modification of the clock switching control circuit shown in FIG. 2, in which an exclusive OR of a high-speed clock and a low-speed clock is taken by an (EXOR) gate 114, and its inverted output is a two-input NAND gate 101. 'And 102', and the other components are the same as those in FIG. According to this configuration, even when both the high-speed clock and the low-speed clock are at the low level or the high level, it is possible to realize a circuit that executes the switching operation based on the change point of the clock selection signal as long as it is at the same level. I can do it. EXO
If it is desired to remove the hazard from the R gate 114, the output of the gate 114 is inverted or inverted of the synchronizing clock, or the NAND gate 10 is output via a flip-flop 115 driven by a clock whose clock is appropriately delayed.
It may be supplied to 1 'and 102'. Note that, due to the hazard from the EXOR gate 114, the clock switching signal 15
Even if a hazard occurs, since the multiplexer 14 is configured using a transfer gate switch, the state of the inputs (A1, A2) is stabilized at the same level due to the characteristics of the CMOS transfer gate described later. As long as the switching signal changes (including the hazard), it can be considered that no hazard is generated at the output of the multiplexer 14. Therefore, the flip-flop 115 should be present, but is not considered an essential element.

FIG. 5 shows an example of the configuration of the multiplexer 14 for switching between the high-speed and low-speed two clocks in FIG.
This is a transfer gate switch formed by a CMOS process. The transistors 110P and 111P are called P-type transistors. A negative potential is applied to the gates (terminals to which the S input is connected) of the transistors 110P and 111P. When a higher potential is applied to the A1 (high-speed clock) input. It becomes conductive and transmits the potential of the A1 input to the buffer 112B. On the other hand, the transistors 110N and 111N are called N-type transistors. When a positive potential is applied to the gate and a lower potential is applied to the A2 input, the transistors 110N and 111N become conductive.
The 2 (low-speed clock) input potential is transmitted to the buffer 112B. Therefore, one of the A1 and A2 inputs can be output to the terminal Z via the buffer 112B depending on the potential of the S input.
Since the path is composed of two stages of transistors, a high-speed switch is possible. Under the conditions other than the above conditions, the output side of each transistor becomes high impedance, but the input impedance of the buffer 112B is also CMOS.
Since the circuit is high impedance, charge is accumulated at the connection between the transistor output and the buffer input, and the state immediately before the state is maintained for a while, and this state is also reflected on the output terminal Z. You. Therefore, when the clock switching signal 15 (S input) is switched, the inverter 112
Even if there is a moment when both transistor gate inputs become low due to the delay of G, if the potential applied to the A1 input and the A2 input is stable at that time, no hazard is generated from the buffer 112B. , Smooth clock switching is performed.

FIG. 6 shows another configuration example of a multiplexer for switching between two clocks, which also has a part of the function of a clock switching control circuit. Basic switch 6 of this circuit
Reference numeral 00 denotes a transfer gate switch formed by a CMOS process as in FIG. 5, but the format of the select signal from the CPU and the switching signal 15 of the switch 600 are different. That is, the basic switch 600 outputs the switching signal S
When A1 is "0", the A1 input is output, and when the switching signal SA2 is "0", the A2 input is output. The input select signals SelA1 and SelA2 are C for selecting the A1 input and A2 input of the clock when they are "1", respectively.
SelA1 = "1", S by the EXOR gate 602 and the NAND gates 603 and 604 from the PU.
When elA2 = "0", signals SA1 = "0" and SA2 =
It becomes “1” and the input A1 is output, and SelA1 =
When "0" and SelA2 = "1", the signal SA1 =
"1", SA2 = "0", and the input A2 is output. Further, by the operation of these gates, SelA1, SelA1,
When A2 is both "0" or "1", the signal SA1
= SA2 = “1”, the basic switch 600 is completely turned off, and both the A1 and A2 inputs are prevented from being output.

The selector signal is temporarily latched by the latch clock LCL using the register 601 and sent to the basic switch 600. This is because the switching timing is synchronized with the clock and the switching signal is latched and simultaneously switched. , SA2 to minimize the switching timing error and prevent the two inputs of the basic switch 600 from being short-circuited. Here, the former is the synchronization. For this purpose, the latch clock LCL must be strictly synchronized with the basic clock CL.
As this method, it is common to output a switching command from the CPU in synchronization with the basic clock CL.

FIG. 8 shows an example of a circuit in which the circuits of FIG. 6 are connected in multiple stages to switch the four-input clocks CL1 to CL4. The basic switches 600 of FIG. 6 are connected in multiple stages, and these are connected to select signals CL1 to CL4. 6 is switched by a switching signal generated by latching the register 804 with the latch clock LCL in the same manner as in FIG. In addition,
A buffer (112B in FIG. 6) connected to the output terminal Z of each basic switch 600 is not required for each switch, and only a buffer 803 needs to be provided at the last output terminal of the multi-stage connection, thereby forming a clock driver.

In the above, the configuration examples and operations of the clock switching control circuit and the multiplexer for switching between the high-speed and low-speed two clocks have been described with reference to FIGS. 2 to 6, but each circuit example for switching more clocks will be described. Is described next. FIG. 7A shows one of four clocks CL1 to CL4.
This is an example of a circuit for selecting and taking out one, and is a circuit corresponding to the clock switching control circuit 13 and the multiplexer 14 in FIG. The multiplexers 701 to 703 are for two-input switching shown in FIG. 5, and a switch portion is composed of these multistage couplings. The switching signal is given by the output of the register 704, and the switching timing is the same as that described with reference to FIG.
L. The selection signals SelE1 and SelE2 input to the register 704 are signals obtained by encoding the selection signals SelCL1 to SelCL4 from the CPU as shown in FIG. 7B. These selection signals Sel
It is considered that E1, SelE2, the register 704, and the latch clock realize the function of the clock switching control circuit, but the part for generating the selection signal and the latch clock is shown in FIG.
Is omitted. Although an example of four clocks has been described here, a larger number of switchings can be similarly configured.

FIG. 7 shows an example of a configuration in which the multiplexers of FIG. 5 are connected in multiple stages. A circuit combining the clock switching control circuit 13 and the multiplexer 14 described in FIG. 2 or FIG. Numerous clock switchings are performed even in a multi-stage connection. In this case, smooth switching control can be similarly realized by a method of setting the timing of switching when the clocks have the same level of logic, depending only on the respective clocks before and after the switching. That is, after masking an unrelated clock input in the first-stage circuit, an AND logic is taken and the NAND gate 101,
102, or EXOR + inverted logic (E
XNOR) and input to the NAND gates 101 and 102. For example, if one clock input is fixed to “1” (mask), EX is used even when AND logic is used.
Even if OR + inverted logic is used, it becomes a mere buffer for passing the other clock, and only when that clock is the clock to be switched next, the switching operation is performed with the clock selection signal synchronized with that clock. become. If both clocks are not related, the clock selection signal itself should not change in the circuit, and the output of the multiplexer 14 should be fixed to "1". From these two conditions, only the finally living clock path, that is, the multiplexer that switches between the currently selected clock path and the clock path to be selected next, and one set of the switching control circuit are provided. Since it can be regarded as operating as the basic two-input clock switching control circuit described above, the same smooth switching operation is possible. The clock path to be newly switched may be determined by decoding the switching instruction fetched by the CPU, specifying the selector signal to each of the corresponding multiplexers, and setting them to necessary logic.

FIG. 9 shows an example of a clock frequency switching circuit at the time of multi-stage input and an example of use of a PLL clock driver in the circuit. Each of the switching circuits 911 to 917 is, for example, as shown in FIG.
A register is added to the multiplexer shown in FIG. 7 as shown in FIG. 7, and a select signal is latched and synchronized with this register by using a clock of frequency f.
This is the same as the configuration in FIG. As described above, if synchronization is performed with the clock having the highest frequency from the PLL, strict synchronization with the basic clock can be achieved. Alternatively, the circuit in FIG. 6 may be used as these switching circuits.

In FIG. 9, a clock frequency to be fed back is assumed to be f, and a basic clock having a frequency of f / 32 is input from the outside based on the clock frequency, and f / 2, f / 3, f /
4, f / 6, f / 10, f / 16, f / 22, f / 32
And a PLL clock driver capable of generating nine kinds of frequencies of f. The clock with the frequency f is the highest-speed clock that is also used as a synchronization clock. The PLL clock driver 901 receives the reference clock C
L (f / 32) to the reference clock (REFCL)
K), and the above nine clock phases are adjusted so that the phase of the signal obtained by internally multiplying the feedback clock CLB by 1/32 and the phase of the reference clock substantially match. That is, since each generated clock is generated strictly in synchronization with the clock having the highest frequency f, it is output from the PLL clock driver at a phase earlier by that amount in accordance with the delay amount of the feedback clock CLB. Will be. Therefore, the switching circuit 9
Rows 11 to 914, rows 915 and 916, and row 91
Delay correction circuits 921 to 92 corresponding to the respective delay amounts in the 7th column
3 is inserted into the synchronous clock (f) as shown to form a synchronous clock for each stage, and the delay correction circuit 92
If the three outputs are returned to the PLL clock driver as the feedback clock CLB, strict synchronization can be achieved in which the phase of the clock output CLout of the final stage output to the CPU substantially coincides with the basic clock phase. In addition,
The phase of the clock output generated from the PLL clock driver can be finely adjusted by using a PLL to which a loop filter (corrected by a resistor and a capacitor) can be externally attached.

It is considered that the use of the PLL for switching the clock frequency will be indispensable to be built in the CPU chip as the CPU becomes faster in the future. That is, even at present, the internal clock of the LSI is 500 MHz.
Class CPU and external system (on electronic board)
It is not a frequency that can be handled directly. Therefore, it is necessary to have a configuration in which the external basic clock is suppressed to about 100 MHz or less and a high-speed operation is performed inside the LSI chip. Further, the CPU system as shown in FIG.
It can be said that it means that it will not be established unless summarized as I. That is, in order to perform switching control by strictly synchronizing clocks exceeding 500 MHz, it is necessary to integrate at least the clock frequency switching circuits 10 and 70 including the PLL clock driver and the CPU cores 20 and 30 into one chip. It is a natural flow to integrate the entire system of FIG. 1 ideally as a one-chip CPU. At present, there is no low-power single-chip LSI with such a concept, but based on FIG. 1, the structural features, functions and effects that can be newly realized in consideration of integration into a one-chip CPU, are based on FIG. Consider the following.

The advantages and necessity of integrating the clock frequency switching circuit and the CPU core are as described above. Therefore, the functions and effects of integrating the two CPU cores 20 and 30 into a one-chip LSI will first be examined. First
By integrating two CPU cores into one chip, the CP
The communication latency by the U-to-U IF circuit can be reduced, and the throughput can be dramatically improved. For example, coherency control between the register files 22 and 32 can be realized in real time. When the operating CPU changes its own register file, it sends the register information to be written, the changed data information and the write command in parallel to the register file in the other CPU, and changes the corresponding register contents in real time. Can be stored. As a result, even if switching between CPUs occurs, it is not necessary to copy the context again, and an effect is obtained that processing can be started immediately without extra overhead.

Second, clock frequency switching circuits 10 and 7
0 and selector signals SELA, SELB and CP composed of the input clock mask signal described above.
Switching control signals / information between U and the like can be generated at high speed with low latency. Conventionally, a means for generating these signals has to be prepared as a status register or the like outside the CPU, and a method of setting and resetting a value by using a MOV instruction or a load / store instruction of the CPU has to be adopted. However, by integrating them into one chip and appropriately arranging them as instructions of the CPU in the embedded program, it can be configured to be executed immediately when fetched by the CPU. As a result, in the CPU core, the asynchronous synchronization processing FFs 107 and 106 in the clock frequency switching circuits 10 and 70 can be removed, or the FF 1
In some cases, it is possible to make synchronization possible only with
Since the internal operating frequency has the advantage of being much faster than the external, the latency involved in switching can be greatly reduced. An example of connection of a control signal for switching between CPUs and an example of a switching protocol thereof will be described later. However, there is an advantage that information transmission between the CPUs can be quickly performed, and operations and processes corresponding to the information can be quickly performed with high response. As a result, fine power control can be described in the program and an effect of further reducing power consumption can be obtained.

Next, consider the one-chip LSI built in the cache memory units (cache memory systems 40 and 50). First, similarly to the coherency control of the register file, a high-speed cache-to-cache interface synchronized with a machine cycle can be configured by one chip, so that the contents of the cache memories can be kept the same in real time. Specifically, the operating CPU
When the cache memory of the other CPU is rewritten, the same address portion of the cache memory of the other CPU is rewritten in parallel. The information sent from the operating CPU is a target cache memory address, cache data, and a write command signal. When the write command becomes active, the contents of the corresponding cache memory address are converted to the target cache data in real time. Rewrite. In the past, since the CPU chips were separate, it was necessary to flush (invalidate) the previous cache information once when the CPU resumed operation. However, this method increases the overhead related to the cache memory when switching the CPU. It can be minimized. When a cache memory system is prepared for each CPU core, the structure of the memory system is divided into a high-speed type and a low power type, and the former is assigned to a high-speed CPU core and the latter is assigned to a low-speed CPU core. Thus, it is possible to provide a structure that is optimal overall in terms of power consumption and operation speed. Further, only the cache memory unit is made into one chip, and the CPU unit and bus means B1, B2, cache memory control signal C1,
A method of externally combining a signal group such as C2 is also conceivable,
Clearly CPU compared to the case where everything is integrated into one chip
It can be said that the access latency between the resource and the resource increases and the performance of the CPU system is negative.

Second, it is also possible to make two sets of cache memories into one set by forming one chip. In particular,
One cache memory is shared by two CPU cores,
High-speed CP to use cache memory more effectively
While the U side is operating, high-speed access is executed by clock synchronous access control or the like.
Static access control by write command (C
In the case of the MOS process, the power consumption may be substantially zero except when the access is made by a command. This not only eliminates the need for coherency management / control between cache memories, but also eliminates the need for one memory unit that requires a large number of transistors.
By removing one set, it is possible to increase the capacity of another set of cache memory, reduce the size of the chip, and achieve higher speed or lower power consumption. In this case as well, in order to realize the coherency control and the shared cache memory as described above, the cache access control on the CPU side is performed on the assumption that the control algorithm of the cache memory and the structure of the cache memory system are common to both CPUs. The circuit must be designed. In this case, the bus switch interface 60 is not of the type that switches the buses from the two CPUs, and is controlled so that an external access operation occurs immediately when access to the integrated cache memory system fails. It may be configured as an input / output bus switch buffer.

Bus switch interface unit 6
It is also effective to combine 0s in another LSI and arrange them near the resource 90. In particular, when the cache memory system is integrated into one and shared by two CPUs, the bus means B1 and B2 are connected by a cache memory, and when access to the cache memory from the cache memory fails (on the cache memory). (When there is no necessary data), there is only one bus means necessary for accessing an external resource. If this internal bus means is defined as an external access bus of the LSI chip of the CPU system, the bus switch interface unit 60 can be defined as a bus interface unit serving as an interface to resources, a system bus, and the like. If this is integrated in an LSI together with a resource access control signal, a decoder, an input / output buffer, and the like, a method of arranging one or a plurality of resources in the vicinity of each resource or local resource block can be adopted. . Centralized CP
As compared with the case where wiring is routed from the U chip, a buffer delay, a decoder delay, and the like can be eliminated (a bus interface unit can be used instead of a buffer IC or a decoder required near a resource), thereby increasing the speed. there is a possibility.

Next, switching control between CPUs will be described with reference to FIGS. First, FIG. 10 shows signal connections for switching control between CPUs and clock frequency control. The high-speed CPU 20 and the low-speed CPU 30 have clock select control circuits 202 and 203, respectively (may be built in the CPU). When the CPU fetches a clock frequency setting / change instruction or a CPU switching instruction and starts executing the instruction, the corresponding clock select control circuit 202 or 203 transmits a necessary control signal (Select, S).
top etc.) to generate the clock selection drivers 200, 2
01 is controlled. Here, the clock selection drivers 200 and 201 shown in FIG. 10 correspond to the functions of the clock frequency switching circuits 10 and 70 in FIG. Also, the signal Sell
ct (A) and (B) are selector signals S in FIG. 1 including control signals such as the above-described clock switching multiplexer switching signal and clock input mask signal.
The signal Stop corresponds to the function of ELA and SELB.
(A) and (B) show the clock stop signal CLST of FIG.
A, It corresponds to the function of CLSTB.

In FIG. 10, the CP selected during the operation is shown.
Assuming a configuration in which a clock is supplied only to U, the Stop signal is cross-connected so that start / stop processing of the clock supplied to itself is executed by the CPUs on the other side. FIG. 11 illustrates how the switching from the high-speed CPU 20 to the low-speed CPU 30 is performed, which will be described in detail. First, operating CP
When the high-speed CPU 20, which is U, fetches a switch command (switch to the CPU 30), it generates a restart command to the CPU 30 and shifts to the idle state. The restart command accompanies the clock control command 23 to the clock select control circuit 202, executes the clock restart to the CPU 30 (cancels the stop (B)), and restarts the clock to the CPU 30 via the inter-CPU communication line 61. Immediately after the startup, an instruction is issued to exit the idle state and shift to the next processing step. When the clock is restarted, the CPU 30 first stops the clock via the clock select control circuit 203 to stop the clock on the CPU 20 side.
After activating p (A), the CPU exits the idle state and proceeds to the next processing step.
Uses the information of the CPU 20 copied to its own register and subsequently executes necessary processing, so that there is no inconsistency in the processing procedure and processing contents.
The same applies to the switching in the opposite direction from the CPU 30 to the CPU 20.

As described above, the switch command between CPUs and C
A clock frequency switching command to the PU and a real-time power control command can be incorporated in a command set of the CPU so that the commands can be used freely in a program. The use of these real-time power control instructions is described below.

When a real-time power control instruction is used for a control controller such as a sequencer, the difference in the sampling time of each task is often directly related to the difference in the priority as shown in FIG. In other words, it can be said that a task with a shorter sampling time (indicated by a triangle in the figure) has a higher tendency to require high-response processing and is a task with a higher priority. Therefore, when a task switch (ag in the figure) occurs between these tasks, the power control command is executed at the head of the started task or in the OS supporting the task switch, and as a result, Select an appropriate CPU and clock frequency according to the priority. For example, the task TA1 with the highest priority is the fast C
The PU core 20 is selected to select the clock with the highest clock frequency.
The clock frequency of the low-speed CPU core 30 is set to the highest setting, and the task 3 having the lowest priority is set to the medium-speed clock frequency of the low-speed CPU core 30. Select As described above, it is effective to shift to the selection mode in which the power consumption is reduced as the task priority decreases.
In idle mode such as sleep mode or wait mode (suspend mode) in which no task is executed, wasteful power consumption can be minimized by setting the clock frequency of the low-speed CPU core 30 to the lowest setting. More effective.

FIG. 13 shows an example of the task processing of each CPU in the multiprocessor operation, and shows a state in which related tasks are synchronized by the inter-processor synchronization mechanism and scheduled parallel processing is progressing. .
SYNCm-n indicates that CPUm and CPUn are synchronized, idle indicates idle time (idle time), and N
OP indicates a state in which nothing is processed (idle task). In this figure, idle and NOP can be recognized when pre-scheduling a task, so it is effective to place a power control instruction there and set an appropriate power saving mode (for example, set the clock frequency of the low-speed CPU core to the lowest). It is possible to achieve power saving.

Next, an example of a power control means and a utilization technique in a processing device operating using a battery system, for example, a notebook personal computer will be described. (1) In a battery-driven processing apparatus having a power control means for dynamically adjusting power consumption and a battery monitoring means for detecting a remaining amount of a battery, when a target operating time at which a processor system is to be operated by a battery is set. The target operating time is guaranteed by dynamically adjusting the power consumption while referring to the remaining amount of the battery. (2) In the above (1), priorities are given to the applications processed by the processing device according to the processing load, and the lighter the processing, the lower the power consumption (= lower the processing speed) and the processing is executed. Thus, the power consumption is adjusted without causing the operator to feel a load during execution of a high-load application. (3) In (1) or (2), a means (such as an external hardware switch or a software switch) that allows the user of the processing device to directly select the priority of processing in the supervisor mode is provided, and power consumption corresponding to the selected priority is provided. (Power control). This operation may be performed in real time during operation. Such (1)
The power control means used in the methods (3) to (3)
It is most effective to use the power control means based on a combination of the above-described CPU switching (high-speed / low-speed CPU switching) and clock frequency switching.

Next, an example of power control (power save) in a method of finely setting power consumption on a window screen on a CRT of a processing apparatus (PC or the like) using the power control means of the present invention will be described. . (1) A control button for setting the priority of the multitask application is provided in each window, or a priority setting window is displayed when each application is started, and the priority is set with a mouse. The power consumption setting controller controls the processing frequency of each application, determines the optimum clock frequency from the priority state of all applications, the overall power consumption of the PC, and the power supply state, thereby efficiently improving the PC performance expected by the user. It can be assigned to the power of the CPU and low power consumption can be achieved. (2) When leaving the PC terminal, an application requiring a background high-speed operation is specified on the power consumption setting window screen. The power consumption setting controller immediately suspends unnecessary devices, such as a display, and determines an optimal clock frequency from the relationship between the amount of calculation performed until the user returns, power consumption, and the power supply state. As a result, it is possible to efficiently execute expected processing while the user does not access and to reduce power consumption.
Here, as a mechanism to sense that you are away from the terminal,
A method such as detection by an input device (keyboard, mouse, or the like) or setting of transition to the low power consumption mode directly on the setting window screen is used. (3) Specify a device not to be used in the window, and put the device in a sleep state. As a result, power consumption can be reduced according to the usage status of the user.

Here, the power consumption setting controller is
This is a program module described using the above-described power control instruction set for operating the above-described power control means (combination of CPU switching and clock frequency switching) of the present invention. If high-speed control is required, this controller may be implemented as firmware. When there is a firmware execution system other than the CPU, the power control instruction set can be directly instructed from the execution system by an external bit line or information input / output means or the like, and the CPU,
It is necessary to provide external command indicating means for immediately executing the corresponding power control command in the system. The firmware execution system executes a necessary power control procedure using the external command instruction means.

The techniques used have been described above. Programs describing these procedures are automatically generated by inserting a power control instruction into a conventional program by a precompiler according to conditions, and downloaded to a system.
By embedding the driver as an OS driver or a system call and providing a mechanism for starting up the OS as needed, it can be realized without directly burdening the user.

Further, the processing device shown in FIG. 1 has a form including two CPUs as the easiest form to implement, but it is also possible to configure a processing device including three or more CPUs. . Among them, one C works effectively.
Only the PU, and the contents of the registers changed during the operation of the CPU can be copied in real time to the registers of the other CPUs not selected as in the case of the configuration with the two CPUs, and the coherency can be maintained. Thus, the interface between CPUs is configured and operates. When switching between CPUs, the CPU to be switched is specified in the switching command. When the instruction is executed, between the designated CPU and the currently selected CPU, the two described in the present embodiment are executed.
A switching operation procedure between the two CPUs is performed.

A processing device including such a plurality of CPUs includes:
It can also be applied to a fault-tolerant system, a high-reliability system with proxy processing in the event of an abnormality, and the like. That is, when an abnormality is detected in the currently executed instruction processing (for example, a parity error or the like), switching to another CPU is performed using the switching means between the CPUs, and the instruction is reprocessed to avoid a malfunction. Becomes possible. In this case, the register is not changed by the instruction in which the error has occurred, or the register contents of some past processing steps are
It is necessary to provide a means for holding the data in the U and restoring the contents of the register of the selected CPU to the state at the time of re-execution.

[0050]

According to the present invention, the following effects can be obtained. (1) The power can be dynamically, finely and quickly controlled, and the effect of reducing the power consumption of the processing device can be obtained. (2) The present invention proposes a technology capable of implementing a low-cost one-chip CPU, and has an effect of being applicable to various applications requiring low power consumption while securing high cost performance.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a low power consumption processing device according to the present invention.

FIG. 2 is a configuration example of a clock switching control circuit.

FIG. 3 is a time chart illustrating an operation of the clock switching control circuit of FIG. 2;

FIG. 4 is a modification of the circuit of FIG. 2;

FIG. 5 is a configuration example of a multiplexer.

FIG. 6 is an example of a clock switching circuit.

FIG. 7 is another example of the clock switching circuit.

FIG. 8 is an example of a multi-clock switching circuit.

FIG. 9 is an example of a number of clock frequency switching circuits.

FIG. 10 is a connection example of CPU switching control.

FIG. 11 is an operation explanatory diagram of FIG. 10;

FIG. 12 is a diagram illustrating an example of task switching, sampling time, and priority of a sequencer system or the like.

FIG. 13 is a diagram illustrating a task processing example of each CPU in a multiprocessor operation.

[Explanation of symbols]

 10, 70 Clock frequency switching circuit 12 PLL clock driver 13 Clock switching control circuit 14 Clock switching multiplexer 20 High-speed CPU core 21, 31 Inter-CPU IF circuit 22, 32 Register file 23 Bus control means 30 Low-speed CPU core 40, 50 Cache memory system 41, 51 Inter-cache IF 60 Bus switch interface 61 Communication line between CPUs 90 External resources 101, 102 Multi-input NAND gate 106, 107 Synchronization processing flip-flop 113 Latching RS flip-flop 114 EXOR gate

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Kenjiro Yamamoto 502 Kandachi-cho, Tsuchiura-shi, Ibaraki Pref. Machinery Research Laboratory, Inc. Inside the Machinery Research Laboratory (72) Inventor Yasuyuki Momoi 502 Kandachicho, Tsuchiura-shi, Ibaraki Pref.Mechanical Research Laboratories, Hitachi Ltd. (72) Inventor Katsuhisa Ike 502 Kandate-cho, Tsuchiura-shi, Ibaraki F-term in Machine Research Laboratory, Hitachi, Ltd. 5B079 AA06 BA02 BB01 BC01

Claims (7)

[Claims] 1. A PL that generates a plurality of clocks synchronized with a given reference clock and having different frequencies from each other
An L clock driver, a clock switching multiplexer for selecting one of the clocks generated by the PLL clock driver in accordance with the input switching signal, and outputting the selected clock as a clock after the switching; The clock before switching and the clock after switching are selected at the same signal level and generate a signal corresponding to a clock switching selector signal provided at a timing synchronized with the reference clock, and this signal is switched to the clock switching. A low power consumption processing device comprising: a clock switching unit that outputs the switching signal to a multiplexer; and a CPU that operates in response to a clock output output from the clock switching multiplexer. 2. The low power consumption processing device according to claim 1, wherein the clock switching means is synchronized with a synchronizing flip-flop for synchronizing the selector signal with a clock synchronized with a reference clock, and is synchronized with the flip-flop. The selector signal is active, and the state is set at the timing when the pre-switching clock and the post-switching clock have changed to the same level, the selector signal is inactive, and the switching is performed with the pre-switching clock. A low-power consumption processing device, comprising: a selection flip-flop whose state is reset at a timing when the subsequent clock changes to the same level; and transmitting an output of the selection flip-flop as the switching signal. 3. A second processing device comprising the low power consumption processing device of claim 1 as a first processing device, a second processing device including a CPU having lower power consumption than a CPU included in the first processing device, An inter-CPU interface means for maintaining the same information between register files of the CPUs in the processing device and the second processing device; a first cache memory system connected to the CPU of the first processing device; A first cache memory control unit for controlling the memory system; a first bus unit including a CPU of the first processing device and a bus control unit input / output via the first cache memory system; and a CPU of the second processing device. A second bus means including a bus control means, and a first bus means and a second bus means responsive to the bus control means from the first processing device and the second processing device. Switching, bus switch interface means for inputting / outputting an external bus and an external control signal at a timing suitable for an external resource; and selecting and operating one of the operation of the first processing device and the second processing device. CPU in the processing unit that did not exist
And a mode switching means for stopping or keeping an idle state. 4. The low power consumption processing device according to claim 3, wherein the mode switching means is incorporated in the first and second processing devices, and one of the first and second processing devices during operation. When the operation is shifted from the processing device to the other processing device, the mode switching means of the operating processing device controls the other processing device to stop or to release the idle state and to control the processing device to shift to the idle state. Then, the mode switching means of the other processing device activated by this controls the clock supply to the processing device that was operating so far, and the other processing device was operating so far. A low-power-consumption processing device that controls to operate by taking over the state of the processing device. 5. The low power consumption processing device according to claim 3, wherein, when the operating processing device rewrites its own register file, the register file of the stopped processing device is also matched with the rewriting result. A low power consumption processing device characterized by rewriting via an interface between CPUs. 6. The low power consumption processing device according to claim 1, wherein the CPU has a clock switching command for issuing the clock switching selector signal to dynamically switch a clock frequency. Low power consumption processing device. 7. The low power consumption processing device according to claim 3, wherein the CPUs of the first and second processing devices issue the clock switching selector signal to change the clock frequency. A low power consumption processing device comprising at least one of a clock switching command for dynamically switching and a CPU switching command for dynamically switching a processing device by the mode switching means.