CN1315018C - Clock pulse switchover structure and its clock pulse switchover method - Google Patents
Clock pulse switchover structure and its clock pulse switchover method Download PDFInfo
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- CN1315018C CN1315018C CNB021298394A CN02129839A CN1315018C CN 1315018 C CN1315018 C CN 1315018C CN B021298394 A CNB021298394 A CN B021298394A CN 02129839 A CN02129839 A CN 02129839A CN 1315018 C CN1315018 C CN 1315018C
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Abstract
The present invention provides a clock pulse switching structure and a clock pulse switching method. A buffer and a low-stage multiplexer are used for locking a clock pulse selection signal to control the output clock pulse signal. The hardware complexity of the multiplexer and a switching control circuit is directly proportional to the number of the clock pulse signals to be switched, the complexity of the circuit is greatly simplified, and the manufacturing cost is reduced.
Description
Technical field
The present invention relates to a kind of time clock switched system that can be used for using in the multiple clock pulse system device, particularly a kind ofly can be used for using in the multiple clock pulse system device, and have the time clock switched system that minimum defective (Glitch) takes place.
Background technology
Circuit for multiple clock pulse signal work switches has considerable application in present development in science and technology.For example promptly possess the internal memory that many different clock operating speeds are arranged in computer system, and this clock switching circuit can be applicable to promptly in the internal memory of these different operating speed, the time clock of reading data in EMS memory is switched.And another kind is more significantly used, and promptly is for example at present computer system operator scheme (Operating Mode) that arrives commonly used and idle mode (Idle Mode).Under operator scheme, can read or write data with the time clock of upper frequency certainly, if but under idle mode, then can reduce operating frequency, save the consumption of power.And such switching then must be applied to the switching of operating clock pulse, just must use this time clock switched system and realize this purpose.
Traditional time clock switched system, shown in Figure 1A, this time clock switched system 100 comprises 110 and switching controls 120 of a multiplexer (MUX).This switching control 120 realizes that by the selection signal that outputs to multiplexer 110 multiplexer 110 switches the purpose of output different clock signal.The complexity of this multiplexer 110 is square to be directly proportional with the clock pulse signal number that will switch, therefore comparatively complicated on hardware, cost is also higher, for example, with the switching for four clock pulse signal Clk_A, Clk_B, Clk_C and Clk_D, this multiplexer 110 is the selection signal (S by switching control 120
3S
2S
1S
0) come pairing input end in the multiplexer is switched selection output.
As receive input end (0001), (0100), (0111), (1101) of multiplexer 110 respectively at clock pulse signal Clk_A, Clk_B, Clk_C and the Clk_D shown in Figure 1A.And switching control 120 receives a time clock selection signal (Clk_Sel) and a sampling clock pulse (Sample_Clk) signal with multidigit.After receiving time clock selection signal Clk_Sel, this switching control 120 comes the selection signal (S of conversion output according to sampling clock pulse Sample_Clk
3S
2S
1S
0), select signal (S and receive this at multiplexer 110
3S
2S
1S
0) after, be worth according to it and export time clock (Out_Clk).And its corresponding output valve is shown in Figure 1B, as selecting signal (S
3S
2S
1S
0)=(0001) time, then export time clock Out_Clk=Clk_A, as selecting signal (S
3S
2S
1S
0)=(0100) time, then export time clock Out_Clk=Clk_B, as selecting signal (S
3S
2S
1S
0)=(0111) time, then export time clock Out_Clk=Clk_C, as selecting signal (S
3S
2S
1S
0)=(1101) time, then export time clock Out_Clk=Clk_D.
In addition, in known time clock switched system, need extra sampling clock pulse Sample_Clk signal.And, for selecting suitable sampling clock pulse Sample_Clk, must consider a restriction, promptly its frequency must be higher than all the clock pulse signal frequencies that will switch.As shown in Figure 2, be another kind of time clock switched system 200 for two time clock x0_clk and the switching of x1_clk do.This time clock switched system comprises that a quadravalence multiplexer (MUX4) 210, switches control device 220.
And among two time clock x0_clk that will switch and the x1_clk, the x0_clk time clock has higher frequency.Therefore, the minimum frequency that must not be lower than the x0_clk time clock of the frequency of the sampling clock pulse Sample_Clk that is adopted.And in Fig. 2, show pre_x0_clk and pre_x1_clk system respectively via the output valve of sampling clock pulse Sample_Clk through two D flip- flops 230 and 240 couples of two the time clock x0_clk and x1_cl.In this hypothesis, if pre_xn_clk=xn_clk, n=0 or 1 represents that then the time of xn_clk time clock level (duration oflevel) is enough long.And switching control 220 also receives another and switches enable signal (Swith_H) except the sampling clock pulse Sample_Clk that reception is used for taking a sample.When switching enable signal Swith_H is high level (being logical one), promptly via the selection signal (S1 that exports, the operation of S0) switching, as shown in Figure 2, (S1 S0) is equaling (0,0), (0,1), output signal out_clk is respectively x0_clk, 0,1 and x1_cl when (1,0) or (1,1).
For the operating clock pulse diagram of time clock switched system 200 shown in Figure 2, shown in Fig. 3 A-3B and Fig. 4 A-4B.In Fig. 3 A, demonstration will be converted to the xl_clk of lower frequency from the time clock x0_clk of upper frequency, when switching enable signal Swith_H is high level (High) (time is t0), begin to carry out blocked operation.When the time t2 of sampling clock pulse Sample_Clk rising edge, the x0_clk time clock value of gained is with corresponding to the time t1 of previous Sample_Clk rising edge the time, and the pre_x0_clk time clock value of gained equates (being low level).At this moment, (S1 S0) promptly transfers (1,0) to by (0,0) to select signal, at this moment, output signal out_clk promptly transfers high level to, and when time t3, selects signal (S1, S0) promptly transfer (1,1) to, and that output signal out_clk transfers promptly with the x1_clk time clock is synchronous to by (1,0).
And in Fig. 3 B, equally show the x1_clk that is converted to lower frequency from the time clock x0_clk of upper frequency, when switching enable signal Swith_H is high level (High) (time is t0), begin to carry out blocked operation.When the time t2 of sampling clock pulse Sample_Clk rising edge, the x0_clk time clock value of gained is with corresponding to the time t1 of previous Sample_Clk rising edge the time, the pre_x0_clk time clock value of gained equates that different is that these two values are high level.When t2, (S1 S0) promptly transfers (0,1) to by (0,0) to select signal, at this moment, output signal out_clk promptly transfers low level to, and when time t3, selects signal (S1, S0) promptly transfer (1,1) to, and that output signal out_clk transfers promptly with the x1_clk time clock is synchronous to by (0,1).
In Fig. 4 A, demonstration will be converted to the time clock x0_clk of upper frequency from the x1_clk of lower frequency, and (time is t0) begins to carry out blocked operation when switching enable signal Swith_H is high level (High).During the time t2 of sampling clock pulse Sample_Clk rising edge, the x1_clk time clock value of gained is with corresponding to the time t1 of previous Sample_Clk rising edge the time, and the pre_x0_clk time clock value of gained equates (being high level).At this moment, (S1 S0) promptly transfers (0,1) to by (1,1), and at this moment, output signal out_clk promptly transfers low level to select signal.When Sample_Clk rising edge time t3 that follows and t4, the x0_clk time clock value of gained is high level, and present output signal out_clk is a low level, therefore can't be synchronous.When following next Sample_Clk rising edge time t5, x0_clk time clock value is a low level, and therefore, (S1 S0) promptly transfers (0,0) to by (0,1), and that output signal out_clk promptly transfers to the x0_clk time clock is synchronous to select signal.
With Fig. 4 category-A seemingly, in Fig. 4 B, demonstration will be converted to the time clock x0_clk of upper frequency from the x1_clk of lower frequency, (time is t0) begins to carry out blocked operation when switching enable signal Swith_H and be high level (High).During the time t2 of sampling clock pulse Sample_Clk rising edge, the x1_clk time clock value of gained is with corresponding to the time t1 of previous Sample_Clk rising edge the time, and the pre_x0_clk time clock value of gained equates that different is to be low level.At this moment, (S1 S0) promptly transfers (1,0) to by (1,1), and at this moment, output signal out_clk promptly transfers high level to select signal.When the Sample_Clk rising edge time t3 that follows, the x0_clk time clock value of gained is a low level, and present output signal out_clk is a high level, therefore can't be synchronous.When following next Sample_Clk rising edge time t4, x0_clk time clock value is a high level, and therefore, (S1 S0) promptly transfers (0,0) to by (1,0), and that output signal out_clk promptly transfers to the x0_clk time clock is synchronous to select signal.
In above-mentioned two kinds of known time clock switched systems, the complexity of multiplexer is and square being directly proportional of the clock pulse signal number that will switch that therefore comparatively complicated on hardware, cost is also higher.In addition, more restriction is arranged in the selection of sampling clock pulse.
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of time clock switched system, the complexity of its multiplexer is to be directly proportional with the clock pulse signal number that will switch, can simplify the complexity of circuit in large quantities, reduces manufacturing cost.
Another object of the present invention, provide another kind of time clock switched system, its sampling clock pulse is the time clock that adopts highest frequency in the clock pulse signal that institute's desire is selected, and needing can avoid extra sampling clock pulse, and its frequency is selected the problem of time clock less than institute's desire.
For achieving the above object, the invention provides a kind of time clock switched system, select signal in order to receive a time clock bus signals and a time clock, wherein this clock pulse bus signal has at least the first clock pulse signal and second clock pulse signal, and the time clock switched system is in order to optionally to export in this first clock pulse signal and this second clock pulse signal in this clock pulse bus signal.This time clock switched system comprises that one switches control device, one first multiplexer, one or door, a Sheffer stroke gate, one first latch means, one second latch means, one second multiplexer and one the 3rd multiplexer.
This switching control is in order to receiving first clock pulse signal, second clock pulse signal, to switch enable signal and sampling clock pulse signal, and according to the driving of switching enable signal, exports one first and select the signal and the second selection signal.First multiplexer selects signal and second to select signal in order to receive first, and selects the value of signal and optionally export first clock pulse signal or the second clock pulse signal that couples with it according to first and second.Or (OR) door selects signal to select signal with second in order to receive first, and selects signal to do one or (OR) export one first time clock write signal after the logical process to first and second.Select signal to select signal with non-(NAND) door in order to receive first with second, and to first and second select signal do one with non-(NAND) logical process after export a second clock pulse write signal.And first latch means is in order to receive clock pulse selecting signal, the first time clock write signal and sampling clock pulse signal, and, select conversion of signals to export one first time clock to time clock and select signal according to the first time clock write signal and sampling clock pulse signal.Second latch means is in order to receive clock pulse selecting signal, second clock pulse write signal and sampling clock pulse signal, and, select conversion of signals to export a second clock pulse selecting signal to time clock according to second clock pulse write signal and sampling clock pulse signal.Second multiplexer is couple to first multiplexer, selects signal in order to the receive clock pulse bus signal and first time clock, and selects signal to export first clock pulse signal to the first multiplexer according to first time clock.The 3rd multiplexer is couple to first multiplexer, in order to receive clock pulse bus signal and second clock pulse selecting signal, and export second clock pulse signal to the first multiplexer according to the second clock pulse selecting signal, so that first multiplexer is optionally exported first clock pulse signal or second clock pulse signal, the control method of the control of first multiplexer such as traditional time clock and a sampling clock pulse.
First latch in above-mentioned time clock switched system comprises one first second order multiplexer and one first impact damper.Wherein, the first second order multiplexer is in order to the receive clock pulse selecting signal and the first time clock write signal, and exports time clock according to the driving of the first time clock write signal and select signal.First impact damper is selected signal in order to receive the sampling clock pulse signal with the time clock of being exported via the first second order multiplexer, and selects signal according to sampling clock pulse signal latch time clock, and exports first time clock and select signal.
Second latch in above-mentioned time clock switched system comprises a second order multiplexer and one second impact damper.Wherein, this second order multiplexer in order to receive clock pulse selecting signal and second clock pulse write signal, and is exported time clock according to the driving of second clock pulse write signal and is selected signal.This second impact damper is selected signal in order to receive the sampling clock pulse signal with the time clock of being exported via the second order multiplexer, and selects signal according to sampling clock pulse signal latch time clock, and output second clock pulse selecting signal.
For achieving the above object, the invention provides a kind of time clock switched system, select signal in order to receive a time clock bus signals and a time clock.This clock pulse bus signal has one first clock pulse signal and a second clock pulse signal at least.This time clock switched system is in order to optionally to export first clock pulse signal or the second clock pulse signal in the clock pulse bus signal.And this time clock switched system comprises that one switches control device, one first multiplexer, one first latch means, one second latch means, one second multiplexer and one the 3rd multiplexer.Switching control is in order to receiving first clock pulse signal, second clock pulse signal, to switch enable signal and sampling clock pulse signal, and according to the driving of switching enable signal, the signal and the second selection signal are selected in output first.First multiplexer selects signal and second to select signal in order to receive first, and selects the value of signal and optionally export first clock pulse signal or the second clock pulse signal that couples with it according to first and second.First latch means is in order to receive clock pulse selecting signal, first clock pulse signal, second clock pulse signal and sampling clock pulse signal, and, select conversion of signals to export one first time clock to time clock and select signal according to first clock pulse signal, second clock pulse signal and sampling clock pulse signal.Second latch means is in order to receive clock pulse selecting signal, first clock pulse signal, second clock pulse signal and sampling clock pulse signal, and, select conversion of signals to export a second clock pulse selecting signal to time clock according to first clock pulse signal, second clock pulse signal and sampling clock pulse signal.Second multiplexer is couple to first multiplexer, selects signal in order to the receive clock pulse bus signal and first time clock, and selects signal to export first clock pulse signal to the first multiplexer according to first time clock.The 3rd multiplexer is couple to first multiplexer, in order to receive clock pulse bus signal and second clock pulse selecting signal, and export second clock pulse signal to the second multiplexer according to the second clock pulse selecting signal, so that first multiplexer is optionally exported first clock pulse signal or second clock pulse signal.
Switched system for several time clock, the invention provides a kind of time clock switched system, illustrate that with two time clock can receive one first clock pulse signal and a second clock pulse signal, wherein the frequency of first clock pulse signal is higher than this second clock pulse signal.This time clock switched system is in order to optionally to export first clock pulse signal or second clock pulse signal.This time clock switched system comprises that one switches control device and one first multiplexer.This switching control is in order to receive first clock pulse signal, second clock pulse signal, a switching enable signal and a sampling clock pulse signal, and wherein, this sampling clock pulse signal is first clock pulse signal.This switching control is exported one first selection signal and one second selection signal according to switching enable signal and sampling clock pulse signal.First multiplexer is couple to switching control, and in order to receive first clock pulse signal, second clock pulse signal, the first selection signal and the second selection signal, and first multiplexer is selected the value of signal according to first and second that is received, and optionally exports in first clock pulse signal and this second clock pulse signal.
For achieving the above object, the present invention proposes a kind of time clock switched system, in order to receive a plurality of clock pulse signals, wherein the highest frequency clock pulse signal is one first clock pulse signal.This time clock switched system is in order to optionally to export one of these clock pulse signals.This time clock switched system comprises that mainly one switches control device and one first multiplexer.And this switching control is in order to receive these clock pulse signals, to switch enable signal and sampling clock pulse signal, and wherein this sampling clock pulse signal is first clock pulse signal.This switching control is exported a plurality of selection signals according to switching enable signal and sampling clock pulse signal.And first multiplexer is couple to switching control, and in order to receiving these clock pulse signals and to select signal, and the value of signals is selected according to these that are received by first multiplexer system, optionally an output time clock signal wherein.
For achieving the above object, the invention provides a kind of clock pulse switchover method, be applicable to according to a sampling clock pulse signal, one output clock pulse signal is switched to a second clock pulse signal from one first original clock pulse signal, and wherein the frequency of first clock pulse signal is higher than this second clock pulse signal.This clock pulse switchover method comprises selects this sampling clock pulse signal to equal first clock pulse signal, and then when sampling clock pulse signal rising edge, temporarily transfer output clock pulse signal to high level, then when the next sampling clock pulse signal rising edge of following, detect the level of second clock pulse signal, when if the second clock pulse signal is high level, soon output clock pulse signal can be switched to the output of second clock pulse signal.
For achieving the above object, the invention provides a kind of clock pulse switchover method, be applicable to according to a sampling clock pulse signal, one output clock pulse signal is switched to one first clock pulse signal from an original second clock pulse signal, and wherein the frequency of first clock pulse signal is higher than this second clock pulse signal.This clock pulse switchover method comprises selects the sampling clock pulse signal to equal first clock pulse signal earlier.When the very first time, second clock pulse signal value during according to sampling clock pulse signal rising edge, and whether the second clock pulse signal value when previous sampling clock pulse pulse wave is identical, whether the level of judging the second clock pulse signal according to this can switch, wherein if two all identical then expressions of level can begin to switch.Then judge the second clock pulse signal value when the very first time, if low level, then temporarily with the fixing output of output signal high level, and when the sampling clock pulse signal of next cycle rises, directly transfer this output signal to low level, and with this first clock pulse signal output.And if this second clock pulse signal value when the very first time is a high level, then temporarily with the fixing output low level of output signal, and follow when the sampling clock pulse signal of next cycle descends temporarily with output signal fixed conversion output high level, then when next sampling clock pulse signal descends, directly this output clock pulse signal is selected to switch to the output of first clock pulse signal.
For achieving the above object, the invention provides a kind of clock pulse switchover method, be applicable to according to a sampling clock pulse signal, one output clock pulse signal is switched to one first clock pulse signal from an original second clock pulse signal, and wherein the frequency of this first clock pulse signal is higher than the second clock pulse signal.This clock pulse switchover method comprises selects the sampling clock pulse signal to equal first clock pulse signal, and then when the very first time, second clock pulse signal value during according to sampling clock pulse signal drop edge, and whether the second clock pulse signal value when previous sampling clock pulse is identical, whether the level of judging the second clock pulse signal according to this can switch, wherein if two all identical then expressions of level can begin to switch.Then judge second clock pulse signal value in the very first time, if low level, then temporarily with the fixing output of output signal high level, and when the sampling clock pulse signal of next cycle descends, directly transfer output signal to low level, export and switch to first clock pulse signal.And if the second clock pulse signal value when the very first time is a high level, then temporarily with the fixing output low level of output signal, and follow when the sampling clock pulse signal of next cycle descends temporarily with output signal fixed conversion output high level, then when next sampling clock pulse signal descends, directly output clock pulse signal is selected to switch to this first clock pulse signal output.
Description of drawings
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly is described in detail below in conjunction with the accompanying drawings.
Figure 1A shows traditional a kind of time clock switched system.
Figure 1B shows the multiplexer output valve corresponding with it according to the selection signal of the traditional time clock switched system among Figure 1A.
Fig. 2 shows another kind of traditional time clock switched system.
Fig. 3 A and 3B show in traditional time clock switched system of Fig. 2, switch to the sequential chart of lower frequency time clock from the upper frequency time clock.
Fig. 4 A and 4B show in traditional time clock switched system of Fig. 2, switch to the sequential chart of upper frequency time clock from the lower frequency time clock.
Fig. 5 has illustrated the time clock switched system of a preferred embodiment of the present invention.
Fig. 6 has illustrated in the time clock switched system of Fig. 5, is converted to the time sequential routine figure of time clock x1_clk from time clock x0_clk.
Fig. 7 has illustrated and be converted to the operating clock pulse diagram of time clock x1_clk from time clock x0_clk in the time clock switched system of Fig. 5.
Fig. 8 has illustrated and be converted to the operating clock pulse diagram of time clock x0_clk from time clock x1_clk in the time clock switched system of Fig. 5.
Fig. 9 has illustrated and be converted to the operating clock pulse diagram of time clock x0_clk from time clock x1_clk in the time clock switched system of Fig. 5.
Figure 10 has illustrated the operating process at the time clock switched system of Fig. 5.
Figure 11 has illustrated a time clock switched system of another preferred embodiment of the present invention.
Figure 12 has illustrated that in the time clock switched system of Figure 11, time clock switches to the sequential chart of time clock x1_clk from time clock x0_clk.
Figure 13 has illustrated in the time clock switched system of Figure 11, switches to the sequential chart of time clock x0_clk from time clock x1_clk.
Figure 14 has illustrated in the time clock switched system of Figure 11, switches to the sequential chart of time clock x0_clk from time clock x1_clk.
Figure 15 has illustrated the operational flowchart at the time clock switched system of another preferred embodiment of Figure 11 the present invention.
Embodiment
First embodiment
Preferred embodiment below in conjunction with description of drawings the present invention application.Icon with reference to the accompanying drawings, identical assembly is represented with identical label.
Please refer to Fig. 5, the time clock switched system 500 of a preferred embodiment of the present invention is described.This time clock switched system 500 mainly comprises the multiplexer (MUX A) 530 and multiplexer (MUX B) 540 that a multiplexer that is used for exporting (MUX) 510, switches control circuit 520 and is used for selecting input clock pulse.This multiplexer 510 is the multiplexer of a quadravalence, and (S1, S0), corresponding its value (0,0), (0,1), (1,0), (1,1) are exported four signal x0_clk, 0,1, x1_clk respectively to receive the selection signal of being exported by control switching circuit 520.
And clock pulse bus (Bus of Clocks) signal clk_xn that multiplexer 530 receptions will be switched and time clock select signal clk_sel via a latch means 531, comprise multiplexer (MUX 2) 532 and impact damper (REGA) 534, the time clock that latchs after the effect is selected signal muxa_sel.Select signal muxa_sel according to time clock, this multiplexer 530 will be selected signal x0_clk output.And export according to the value that impact damper writes drive signal (rega_wr_H) this multiplexer (MUX 2) 532.And impact damper 534 latchs (Latch) time clock selection signal clk_sel and uses control multiplexer 530 via sampling clock pulse sample_clk.It is selection signal (S1 via Fig. 5 right side that this impact damper writes drive signal rega_wr_H, S0), signal through gained after one first logical operation of one first logical calculation device 560, this first logical calculation device 560 with or the door (OR) 560 be example, first logical operation then is or (OR) logical operation.
And for when beginning to switch, then the switching enable signal switch_H that is received by control switching circuit 520 is controlled.In the present embodiment, this switching enable signal switch_H selects signal muxa_sel and muxb_sel to do one relatively through comparer (CMP) 550 by time clock, if the input value (real time clock pulse selecting signal muxb_sel) of A end is identical with the input value (real time clock pulse selecting signal muxa_sel) of B end, then be output as 0, if difference then exports 1.
Please refer to Fig. 6, the operating clock pulse diagram that is converted to time clock x1_clk about the time clock switched system 500 of Fig. 5 from time clock x0_clk is described.When time t1, time clock selects signal muxb_sel to change, so drive multiplexer 540 output time clock x1_clk, at the same time, switching enable signal switch_H through comparer 550 outputs is converted to high level, so in next sampling clock pulse sample_clk rising edge, time t2 just, detect time clock x0_clk and be output as low level, and the previous value of time clock x0_clk also is a low level, the time of representing this level is enough long, can carry out blocked operation.Selection signal (the S1 of control switching circuit 520 outputs, S0) value is converted to (1 at this moment, 0),, and all can time clock x1_clk be detected in the sampling clock pulse sample_clk rising edge of following so output signal out_clk promptly transfers high level to, when time t3, time clock x1_clk transfers high level to, and the selection signal that control switching circuit 520 is exported (S1, S0) value promptly is converted to (1,1), output signal out_clk promptly switches to time clock x1_clk synchronous.
Please refer to Fig. 7, also is explanation is converted to time clock x1_clk from time clock x0_clk about the time clock switched system 500 of Fig. 5 operating clock pulse diagram.When time t1, time clock selects signal muxb_sel to change, so drive multiplexer 540 output time clock x1_clk, at the same time, switching enable signal switch_H through comparer 550 outputs is converted to high level, so in next sampling clock pulse sample_clk rising edge, time t2 just, with Fig. 6 difference, be to detect time clock x0_clk and be output as high level, and the previous value of time clock x0_clk also is a high level, represents that the time of this level is enough long, can carry out blocked operation.Selection signal (the S1 of control switching circuit 520 outputs, S0) value is converted to (0 at this moment, 1), so output signal out_clk promptly transfers low level to, and the sampling clock pulse sample_clk rising edge of following, just during time t3, detecting time clock x1_clk is high level, and the selection signal that control switching circuit 520 is exported (S1, S0) value promptly is converted to (1,1), output signal out_clk promptly switches to time clock x1_clk synchronous.
Please refer to Fig. 8, the operating clock pulse diagram that is converted to time clock x0_clk about the time clock switched system 500 of Fig. 5 from time clock x1_clk is described.When time t1, time clock selects signal muxa_sel to change, so drive multiplexer 530 output time clock x0_clk, at the same time, switching enable signal switch_H through comparer 550 outputs is converted to high level, so in next sampling clock pulse sample_clk rising edge, time t2 just, detect time clock x1_clk and be output as high level, and the previous value of time clock x1_clk also is a high level, the time of representing this level is enough long, can carry out blocked operation.Selection signal (the S1 of control switching circuit 520 outputs, S0) value is converted to (0 at this moment, 1),, and all can time clock x0_clk be detected in the sampling clock pulse sample_clk rising edge of following so output signal out_clk promptly transfers low level to, when time t3, time clock x0_clk transfers low level to, and the selection signal that control switching circuit 520 is exported (S1, S0) value promptly is converted to (0,0), output signal out_clk promptly switches to time clock x0_clk synchronous.
Please refer to Fig. 9, the operating clock pulse diagram that is converted to time clock x0_clk about the time clock switched system 500 of Fig. 5 from time clock x1_clk is described.When time t1, time clock selects signal muxa_sel to change, so drive multiplexer 530 output time clock x0_clk, at the same time, switching enable signal switch_H through comparer 550 outputs is converted to high level, so in next sampling clock pulse sample_clk rising edge, time t2 just, with Fig. 8 difference, be to detect time clock x1_clk and be output as low level, and the previous value of time clock x1_clk also is a low level, represents that the time of this level is enough long, can carry out blocked operation.Selection signal (the S1 of control switching circuit 520 outputs, S0) value is converted to (1 at this moment, 0), so output signal out_clk promptly transfers high level to, and the sampling clock pulse sample_clk rising edge of following, just during time t3, detecting time clock x0_clk is high level, and the selection signal that control switching circuit 520 is exported (S1, S0) value promptly is converted to (0,0), output signal out_clk promptly switches to time clock x0_clk synchronous.
About the operating process of the time clock switched system 500 of Fig. 5, as shown in figure 10, in step 1000, the time clock of judging present multiplexer MUX 510 selected outputs is x0_clk or x1_clk.If the x1_clk time clock, then impact damper REG B 544 does not write new clk_sel value, and impact damper REG A 534 then writes new clk_sel value.Follow step 1020, multiplexer 510 is selected suitable fixed values (being so-called high level or low level) output, follows step 1030, and multiplexer 510 selects time clock x0_clk to export.
In step 1000, if judge the time clock x1_clk of present multiplexer MUX 510 selected outputs, then follow step 1040, impact damper REG A 534 does not write new clk_sel value, and impact damper REG B 544 then writes new clk_sel value.Follow step 1050, multiplexer 510 is selected suitable fixed values (being so-called high level or low level) output, follows step 1060, and multiplexer 510 selects time clock x1_clk to export.
Time clock switched system according to the invention described above preferred embodiment, the multiplexer of application buffer and low order, select signal to do one for time clock and latch effect, to control the clock pulse signal of being exported, its hardware complexity system on multiplexer and control switching circuit is directly proportional with the clock pulse signal number that will switch, can simplify the complexity of circuit in large quantities, reduce manufacturing cost.
Second embodiment
Please refer to Figure 11, a time clock switched system 1100 of another preferred embodiment of the present invention is described, this time clock switched system 1100 comprises that mainly a multiplexer 1110 and switches control device 1120.And switching control 1120 is in order to receive clock pulse x0_clk, time clock x1_clk, sampling clock pulse sample_clk and switching enable signal switch_H, and signal (S1 is selected in output, S0), wherein sampling clock pulse sample_clk adopts institute's desire to switch time clock x0_clk or the highest time clock of both frequencies of x1_clk, the frequency that is higher than time clock x1_clk in the frequency of this hypothesis time clock x0_clk, therefore, sampling clock pulse sample_clk promptly equals time clock x0_clk.
And the figure of 1100 time sequential routines of time clock switched system among Figure 11, then as shown in figure 12, for the time clock switching switches to time clock x1_clk from time clock x0_clk.When time t1, switch enable signal switch_H and become high level, promptly begin to switch time clock, at this moment, in next sampling clock pulse sample_clk rising edge, just during time t2, select signal (S1, S0) can be directly by original (0,0) transfer (1,0) to, just output signal out_clk temporarily transfers high level to, and need not judge that the previous time clock of x0_clk is high or low level, need not judge just whether this level time is enough long.The next sampling clock pulse sample_clk rising edge of following again, just during time t3, detecting time clock x1_clk is high level, so, output signal out_clk directly can be transferred to time clock x1_clk synchronously, realize the operation that time clock is switched.
And Figure 13 shows that the time clock switched system 1100 in the present embodiment switches to the time sequential routine figure of time clock x0_clk from time clock x1_clk.When time t1, switch enable signal switch_H and become high level, promptly begin to switch time clock, at this moment, in next sampling clock pulse sample_clk rising edge, just during time t2, detecting the x1_clk time clock is low level, and judge that the previous time clock of x1_clk also is a low level, and judge just whether this level time is enough long, select signal (S1, S0) can be directly by original (1,1) transfer (1,0) to, just output signal out_clk temporarily transfers high level to.The next sampling clock pulse sample_clk rising edge of following again, just during time t3, sampling clock pulse sample_clk is identical with time clock x0_clk, because of this time clock x0_clk also is in the rising edge, and the output signal out_clk of this moment is positioned at high level, then can't synchronously rise.Therefore, for the energy synchronous clock pulse, so must transfer output signal out_clk to low level earlier, (S1 S2) transfers (0,1) to just to select signal.And, just during time t4, output signal out_clk directly can be transferred to time clock x0_clk synchronously in next sampling clock pulse sample_clk rising edge, realize the operation that time clock is switched.
And Figure 14 shows that the time clock switched system 1100 in the present embodiment switches to the time sequential routine figure of time clock x0_clk from time clock x1_clk.When time t1, switch enable signal switch_H and become high level, promptly begin to switch time clock, at this moment, in next sampling clock pulse sample_clk rising edge, just during time t2, to detect the x1_clk time clock be high level and judge that the previous time clock of x1_clk also is a high level, judge just whether this level time enough long, select signal (S1, S0) can be directly by original (1,1) transfers (0 to, 1), just output signal out_clk temporarily transfers low level to, so the time is enough long.The next sampling clock pulse sample_clk rising edge of following again, just during time t3, sampling clock pulse sample_clk is identical with time clock x0_clk, because of this time clock x0_clk also is in the rising edge, and the output signal out_clk of this moment is positioned at low level, therefore output signal out_clk directly can be transferred to time clock x0_clk synchronously, realize the operation that time clock is switched.
About the sequential chart among the 13rd and 14 figure, utilize the rising edge of sampling clock pulse sample_clk (time clock x0_clk just) as the foundation of judging because be, therefore, when time clock x1_clk switches to time clock x0_clk, (just select signal S1 if temporarily transfer output signal out_clk to high level, S0=1,0), it is afterwards synchronous more then to need to transfer to low level again.Because adopt in the time clock that will switch at this embodiment, the time clock of highest frequency is as sampling clock pulse.Therefore, when forwarding the time clock of this highest frequency to,, then must transfer output signal out_clk to low level earlier as if being benchmark with the rising edge by low frequency.Certainly, the sampling clock pulse benchmark of present embodiment is not limited to the rising edge.If with the drop edge is benchmark, if then similarly output signal out_clk signal be positioned at low level, then must be converted into earlier after the high level, could do synchronous switching.
The operational flowchart of present embodiment serves as the time clock switching flow that switches foundation for the rising edge with the sampling clock pulse benchmark as shown in figure 15.When step 1510, judge it is which time clock is selected earlier.If switch to the time clock of high frequency, then carry out step 1512, if will switch to other time clock, then carry out step 1542 by highest frequency.
Please be earlier with reference to the step 1512 that will switch to high-frequency clock pulse, if when beginning to switch, then then carry out step 1514, judge whether present time clock level is enough long, whether the value that discloses a kind of former time clock value when utilizing sampling clock pulse to rise and previous sampling clock pulse pulse wave rising in the present embodiment is identical judges, does not so only limit and finishes with the method.Follow step 1516, the value of judgement time clock level, if 0, then carry out step 1518, make multiplexer select fixed value 1 output, and then step 1520 allow multiplexer change selection 0 output; And if 1, then carry out step 1522, allow multiplexer select 0 output.In step 1518 to 1520, multiplexer is had more once switching, be because when the sampling clock pulse rising edge, will switch the output time clock, and sampling clock pulse is the time clock of highest frequency, therefore, output must be switched to 0 earlier, could finish switching in the sampling clock pulse rising edge.Follow step 1524, multiplexer then can be selected the time clock output of highest frequency at this moment, and promptly follow step 1550 and finish blocked operation this moment, and without any defective (Glitch) generation of switching.
Please follow with reference to the step 1542 that will switch to other time clock, after decision is switched, then allow multiplexer select fixed value 1 output earlier by highest frequency.Then step 1546 judges whether the time clock level that institute's desire is switched is 1, if, then carry out step 1548, allow multiplexer directly export " selected time clock ".At this moment, promptly finish the operation of switching time clock.
In the present embodiment, provide a kind of switching clock system, its sampling clock pulse is the time clock that adopts highest frequency in the clock pulse signal that institute's desire is selected.Its advantage no matter be the time clock that other frequency clock pulse switches to highest frequency, or switches to the time clock of other frequency by the time clock of highest frequency as mentioned above, can simplify and faster flow process finish time clock and switch.Therefore, can avoid the sampling clock pulse frequency to select the problem that time clock produced less than institute's desire.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, under the premise without departing from the spirit and scope of the present invention; can do various changes and retouching, so protection scope of the present invention is looked accompanying Claim and is defined.
Claims (17)
1. time clock switched system, select signal in order to receive a time clock bus signals and a time clock, wherein this clock pulse bus signal has at least the first clock pulse signal and second clock pulse signal, this time clock switched system is in order to optionally to export in this first clock pulse signal and this second clock pulse signal in this clock pulse bus signal, and wherein this time clock switched system comprises:
One switches control device, in order to receive this first clock pulse signal, this second clock pulse signal, switches an enable signal and a sampling clock pulse signal, and, export one first and select the signal and the second selection signal according to this driving of switching enable signal;
One first multiplexer first selects signal and this second to select signal in order to receive this, and selects the value of signal according to this first and second and optionally export this first clock pulse signal, the second clock pulse signal that couples with it;
One first logical calculation device is selected signal in order to receive this first selection signal and second, and selects the combined value of signal to carry out exporting one first time clock write signal after one first logical operation to this first and second;
One second logical calculation device is selected signal in order to receive this first selection signal and second, and selects the combined value of signal to carry out exporting a second clock pulse write signal after one second logical operation to this first and second;
One first latch means, select signal, this first time clock write signal and this sampling clock pulse signal in order to receive this time clock, and, select conversion of signals to export one first time clock to this time clock and select signal according to this first time clock write signal and this sampling clock pulse signal;
One second latch means, select signal, this second clock pulse write signal and this sampling clock pulse signal in order to receive this time clock, and, select conversion of signals to export a second clock pulse selecting signal to this time clock according to this second clock pulse write signal and this sampling clock pulse signal;
One second multiplexer, be couple to this first multiplexer, select signal in order to receive this clock pulse bus signal and this first time clock, and select signal to export this first clock pulse signal to this first multiplexer according to this first time clock; And
One the 3rd multiplexer, be couple to this first multiplexer, in order to receive this clock pulse bus signal and this second clock pulse selecting signal, and export this second clock pulse signal to this first multiplexer according to this second clock pulse selecting signal, so that this first multiplexer is optionally exported one in this first clock pulse signal and this second clock pulse signal.
2. time clock switched system as claimed in claim 1, wherein this time clock switched system also comprises a comparer, in order to receive and relatively this first selects clock pulse signal and this second selection clock pulse signal, and export this switching enable signal, wherein, when selecting clock pulse signal identical when this first and second, then this switching enable signal is one first level, and select clock pulse signal not simultaneously when this first and second, then this switching enable signal is one second level of one and first level inversion, and the operation of switching according to this first and second level drive clock pulse.
3. time clock switched system as claimed in claim 1, wherein this first latch means comprises:
One first second order multiplexer is selected signal and this first time clock write signal in order to receive this time clock, and is exported this time clock according to the driving of this first time clock write signal and select signal; And
One first impact damper, select signal in order to receive this sampling clock pulse signal with this time clock of being exported via this first second order multiplexer, and according to this time clock selection signal of this sampling clock pulse signal latch, and export this first time clock and select signal.
4. time clock switched system as claimed in claim 1, wherein this second latch means comprises:
One second second order multiplexer is selected signal and this second clock pulse write signal in order to receive this time clock, and is exported this time clock according to the driving of this second clock pulse write signal and select signal; And
One second impact damper, select signal in order to receive this sampling clock pulse signal with this time clock of being exported via this second second order multiplexer, and according to this time clock selection signal of this sampling clock pulse signal latch, and export this second clock pulse selecting signal.
5. time clock switched system as claimed in claim 1, wherein this first logical calculation device is one or door, and this first logical operation is one or logical operation.
6. time clock switched system as claimed in claim 1, wherein this second logical calculation device is a Sheffer stroke gate, and this second logical operation is a NAND Logic computing.
7. time clock switched system, select signal in order to receive a time clock bus signals and a time clock, wherein this clock pulse bus signal has at least the first clock pulse signal and second clock pulse signal, this time clock switched system is in order to optionally to export in this first clock pulse signal and this second clock pulse signal in this clock pulse bus signal, and wherein this time clock switched system comprises:
One switches control device, in order to receive this first clock pulse signal, this second clock pulse signal, switches an enable signal and a sampling clock pulse signal, and, export one first and select the signal and the second selection signal according to this driving of switching enable signal;
One first multiplexer first selects signal and this second to select signal in order to receive this, and selects the value of signal according to this first and second and optionally export this first clock pulse signal, the second clock pulse signal that couples with it;
One first latch means, select signal, this first clock pulse signal, second clock pulse signal and this sampling clock pulse signal in order to receive this time clock, and, select conversion of signals to export one first time clock to this time clock and select signal according to this first clock pulse signal, this second clock pulse signal and this sampling clock pulse signal;
One second latch means, select signal, this first clock pulse signal, second clock pulse signal and this sampling clock pulse signal in order to receive this time clock, and, select conversion of signals to export a second clock pulse selecting signal to this time clock according to this first clock pulse signal, second clock pulse signal and this sampling clock pulse signal;
One second multiplexer, be couple to this first multiplexer, select signal in order to receive this clock pulse bus signal and this first time clock, and select signal to export this first clock pulse signal to this first multiplexer according to this first time clock; And
One the 3rd multiplexer, be couple to this first multiplexer, in order to receive this clock pulse bus signal and this second clock pulse selecting signal, and export this second clock pulse signal to this first multiplexer according to this second clock pulse selecting signal, so that this first multiplexer is optionally exported one in this first clock pulse signal and this second clock pulse signal.
8. time clock switched system as claimed in claim 7, wherein this time clock switched system also comprises a comparer, in order to receive and relatively this first time clock select signal and this second clock pulse selecting signal, and export this switching enable signal, wherein, when this first and second time clock selects signal identical, then this switching enable signal is one first level, select signal not simultaneously and work as this first and second time clock, then this switching enable signal be one with second level of this first level inversion, and according to the blocked operation of this first and second level drive clock pulse.
9. time clock switched system as claimed in claim 7, wherein this time clock switching device shifter also comprises:
One first logical calculation device first selects signal to select signal with second in order to receive this, and exports one first time clock write signal to this first latch means after selecting signal to do one first logical operation to this first and second; And
One second logical calculation device first selects signal to select signal with second in order to receive this, and exports a second clock pulse write signal to this second latch means after selecting signal to do one second logical operation to this first and second.
10. time clock switched system as claimed in claim 9, wherein this first logical calculation device is one or door, and this first logical operation is one or logical operation.
11. time clock switched system as claimed in claim 9, wherein this second logical calculation device is a Sheffer stroke gate, and this second logical operation is a NAND Logic computing.
12. time clock switched system, in order to receive one first clock pulse signal and a second clock pulse signal, wherein the frequency of this first clock pulse signal is higher than this second clock pulse signal, this time clock switched system is in order to optionally to export in this first clock pulse signal and this second clock pulse signal, and wherein this time clock switched system comprises:
One switches control device, this switching control is in order to receive this first clock pulse signal, this second clock pulse signal, a switching enable signal and a sampling clock pulse signal, wherein this sampling clock pulse signal is couple to this first clock pulse signal, and wherein this switching control is exported one first selection signal and one second selection signal according to this switching enable signal and this sampling clock pulse signal; And
One first multiplexer, be couple to this switching control, in order to receive this first clock pulse signal, this second clock pulse signal, this first selection signal and this second selection signal, and this first multiplexer according to received this first and second select the value of signal, optionally export in this first clock pulse signal and this second clock pulse signal.
13. time clock switched system, in order to receive a plurality of clock pulse signals, wherein the highest frequency clock pulse signal in those clock pulse signals is one first clock pulse signal, this time clock switched system is in order to optionally to export one of those clock pulse signals, and this time clock switched system comprises:
One switches control device, this switching control switches an enable signal and a sampling clock pulse signal in order to receive those clock pulse signals,, wherein this sampling clock pulse signal is couple to this first clock pulse signal, and wherein this switching control is exported a plurality of selection signals according to this switching enable signal and this sampling clock pulse signal; And
One first multiplexer is couple to this switching control, in order to receive those clock pulse signals, those select signal, and this first multiplexer is selected the value of signals according to those that are received, and optionally exports one of those clock pulse signals.
14. clock pulse switchover method, be applicable to according to a sampling clock pulse signal, one output clock pulse signal is switched to a second clock pulse signal from one first original clock pulse signal, wherein the frequency of this first clock pulse signal is higher than this second clock pulse signal, and this clock pulse switchover method comprises the following steps:
Select this sampling clock pulse signal to equal this first clock pulse signal;
When this sampling clock pulse signal rising edge, temporarily transfer this output clock pulse signal to high level; And
When this sampling clock pulse signal rising edge of the next one of following, detect the level of this second clock pulse signal, when being high level, this output clock pulse signal can be switched to this second clock pulse signal output as if this second clock pulse signal.
15. clock pulse switchover method, be applicable to according to a sampling clock pulse signal, one output clock pulse signal is switched to one first clock pulse signal from an original second clock pulse signal, wherein the frequency of this first clock pulse signal is higher than this second clock pulse signal, and this clock pulse switchover method comprises the following steps:
Select this sampling clock pulse signal to equal this first clock pulse signal;
In the very first time, this second clock pulse signal value during according to this sampling clock pulse signal rising edge, and whether this second clock pulse signal value when previous this sampling clock pulse pulse wave is identical, whether the level of judging this second clock pulse signal according to this can switch, wherein if two level are all identical, then expression can begin to switch; And
Judgement this second clock pulse signal value when this very first time, if low level, then temporarily with the fixing output of this output signal high level, and when the sampling clock pulse signal of next cycle rises, directly transfer this output signal to low level, and when the sampling clock pulse signal of next cycle rises, with this first clock pulse signal output
And if this second clock pulse signal value when this very first time is a high level, then temporarily with the fixing output low level of this output signal, then when next sampling clock pulse signal rises, directly this output clock pulse signal is selected to switch to this first clock pulse signal output.
16. clock pulse switchover method, be applicable to according to a sampling clock pulse signal, one output clock pulse signal is switched to one first clock pulse signal from an original second clock pulse signal, wherein the frequency of this first clock pulse signal is higher than this second clock pulse signal, and this clock pulse switchover method comprises the following steps:
Select this sampling clock pulse signal to equal this first clock pulse signal;
When the very first time, this second clock pulse signal value during according to this sampling clock pulse signal drop edge, and whether this second clock pulse signal value when previous this sampling clock pulse pulse wave is identical, whether the level of judging this second clock pulse signal according to this can switch, wherein if two level are all identical, then expression can begin to switch; And
Judgement this second clock pulse signal value when this very first time, if low level then temporarily with the fixing output of this output signal high level, and switches to when the sampling clock pulse signal of next cycle descends with this first clock pulse signal output,
And if this second clock pulse signal value when this very first time is a high level, then temporarily with the fixing output low level of this output signal, and follow when the sampling clock pulse signal of next cycle descends temporarily with this output signal fixed conversion output high level, then when next sampling clock pulse signal descends, directly this output clock pulse signal is selected to switch to this first clock pulse signal output.
17. clock pulse switchover method, be applicable to according to a sampling clock pulse signal, one output clock pulse signal is switched to a second clock pulse signal from one first original clock pulse signal, wherein the frequency of this first clock pulse signal is higher than this second clock pulse signal frequency, and this clock pulse switchover method comprises the following steps:
Select this sampling clock pulse frequency to equal this first clock pulse signal;
When this sampling clock pulse signal drop edge, transfer this output clock pulse signal to high level; And
When this sampled signal drop edge of the next one of following, detect the level of this second clock pulse signal, when being low level, this output clock pulse signal can be selected switch to this second clock pulse signal as if this second clock pulse signal.
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| CN100381968C (en) * | 2004-11-01 | 2008-04-16 | 联发科技股份有限公司 | System clock pulse switching device and method for switching its frequency |
| CN100511089C (en) * | 2007-04-20 | 2009-07-08 | 威盛电子股份有限公司 | Clock switching circuit and method for switching clock signal |
| CN111398786B (en) * | 2020-04-02 | 2020-12-25 | 上海燧原科技有限公司 | Switching control circuit, system-on-chip, chip test system and method |
| CN111541451B (en) * | 2020-06-23 | 2021-10-29 | 深圳比特微电子科技有限公司 | Method and clock circuit for up-converting a clock signal |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1212391A (en) * | 1997-09-24 | 1999-03-31 | 三菱电机系统Lsi设计株式会社 | Built-in oscillating circuit for integrated circuit |
| CN1294328A (en) * | 1999-10-26 | 2001-05-09 | 华硕电脑股份有限公司 | Device and method for switching frequency of system clock pulses on computer masterboard |
| JP2001202155A (en) * | 2000-01-18 | 2001-07-27 | Hitachi Ltd | Low power consumption processor |
| JP2002062948A (en) * | 2000-08-23 | 2002-02-28 | Ricoh Co Ltd | Clock switching device |
-
2002
- 2002-08-15 CN CNB021298394A patent/CN1315018C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1212391A (en) * | 1997-09-24 | 1999-03-31 | 三菱电机系统Lsi设计株式会社 | Built-in oscillating circuit for integrated circuit |
| CN1294328A (en) * | 1999-10-26 | 2001-05-09 | 华硕电脑股份有限公司 | Device and method for switching frequency of system clock pulses on computer masterboard |
| JP2001202155A (en) * | 2000-01-18 | 2001-07-27 | Hitachi Ltd | Low power consumption processor |
| JP2002062948A (en) * | 2000-08-23 | 2002-02-28 | Ricoh Co Ltd | Clock switching device |
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