CN100351827C - Pin sharing system - Google Patents
Pin sharing system Download PDFInfo
- Publication number
- CN100351827C CN100351827C CNB2004100328830A CN200410032883A CN100351827C CN 100351827 C CN100351827 C CN 100351827C CN B2004100328830 A CNB2004100328830 A CN B2004100328830A CN 200410032883 A CN200410032883 A CN 200410032883A CN 100351827 C CN100351827 C CN 100351827C
- Authority
- CN
- China
- Prior art keywords
- pin
- connections
- group
- integrated circuit
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Multi Processors (AREA)
Abstract
The present invention relates to a pin sharing system. The pin sharing system comprises an integrated circuit, a first device, a second device, a memory, a first group of wirings, a second group of wirings and a third group of wirings, wherein the integrated circuit a first pin group and a second pin group; the first device comprises a first group of data pins, and the second device comprises a group of input and output data address pins; the memory comprises a group of low address pins, a group of high address pins and a group of memory data pins. The first group of wirings are connected with the first group of data pins, and the low address pin group to the first pin group; the second group of wirings is connected with the memory data pin group, and the input and output data address pin group to the second pin group; the second group of wiring also comprise a register which is connected between the input and output data address pin group, and the second pin group; the register is used for temporarily store one group of address information; subsequently, the stored address information is transmitted to the second device; the third group of wirings are connected with the high address pin group and the register to the second pin group.
Description
Technical field
The present invention is about a kind of pin shared system, is used for the circuit that is connected between shared peripheral and integrated circuit.
Background technology
Along with semiconductor fabrication is advanced by leaps and bounds, the function of general integrated circuit also becomes increasingly complex, even some integrated circuit can be controlled many devices.Yet when being connected with integrated circuit, multiple arrangement but produces a problem, that is exactly usually deposited use of restriction that the externally continuous number of pins of integrated circuit is subjected to the integrated circuit encapsulation technology, so some pin just must design can allow several devices shared.So pin shared system is a structure common in the computing machine.Pin shared system may comprise several peripherals, and an integrated circuit that is generally central processing unit.Each outer periphery enjoys integrated circuit control, thereby the pin that needs the pin of the wiring connection integrated circuit that number do not wait and peripherals is with transmission signals.Wherein the pin of integrated circuit is because shared by several peripherals institute, thereby just must avoid signal to produce in integrated circuit and several peripherals transmittance processs and conflict.
For example United States Patent (USP) the 6th, 044, No. 412 disclosed technology, pin shared system can be applicable to dynamically storing media (Dynamic Memory Device, for example: CD-ROM), with the static store medium (StaticMemory Device, for example: ROM) wait between the peripherals.Yet because shared same the wiring of pin of several peripherals, several devices of shared same wiring can't be communicated with integrated circuit simultaneously, so that a plurality of peripherals of this kind pin shared system often are subject to shared wiring and are in idle state.If can make part peripherals when sharing wiring or pin, also can be integrated circuit simultaneously and control, then the usefulness of computer system integral body will thereby improve.
Summary of the invention
The present invention is about a kind of pin shared system, is used for the circuit that is connected between shared peripheral and integrated circuit.
Pin shared system comprises an integrated circuit, first device, second device, storage arrangement, first set of connections, second set of connections and the 3rd set of connections.Integrated circuit comprises one first pin set and second pin set.First device comprises first group of data pin.Second device comprises one group and exports into the data address pin.Storage arrangement comprises one group of lower address pins, one group of high address pin and storage stack data pin.First set of connections connects first group of data pin and lower address pins group to the first pin set.The second set of connections connected storage data pin group is gone into data address pin set to the second pin set with output.Second set of connections also comprises and is connected in output and goes into register between data address pin and second pin set, and this register is sent to institute's address stored information second subsequently and installs in order to temporary transient storage one group address message.The 3rd set of connections connects high address pin set and register to the second pin set.
This pin shared system can make integrated circuit control an above peripherals simultaneously, and makes several pins of integrated circuit can be shared by several peripherals institute, with improve the efficient that peripherals uses and reduce integrated circuit the pin number of palpus.
Description of drawings
Fig. 1 is the synoptic diagram of pin shared system first embodiment of the present invention.
Fig. 2 is the synoptic diagram of Fig. 1 integrated circuit.
Fig. 3 is the synoptic diagram of pin shared system second embodiment of the present invention.
Fig. 4 is the synoptic diagram of pin shared system the 3rd embodiment of the present invention.
The drawing reference numeral explanation
10: pin shared system 12: integrated circuit
16: the second devices of 14: the first devices
18: 20: the first pin set of storage arrangement
26: the first groups of data pin of 22: the second pin set
28: data address pin 30 is gone in output: lower address pins
32: high address pin 34: the memory data pin
42: the second set of connections of 40: the first set of connections
Set of connections 46 in 44: the three: register
50: pin is selected module 52: control module
54: resolver 56: Memory Controller
60: the second Setup Controllers of 58: the first Setup Controllers
68: the first logic gates of 66: the four set of connections
74: write pin 76: storer control pin
Logic gate 82 in 80: the three: device control pin
221: integrated circuit address pin 222: the integrated circuit data pin
223: integrated circuit control pin
281: the second device data input pins
282: the second device data output pins
283: the second unit address pins
Embodiment
See also Fig. 1, Fig. 1 is the synoptic diagram of pin shared system 10 first embodiment of the present invention.Pin shared system 10 comprises integrated circuit 12, the first device 14, the second devices 16, and peripherals such as storage arrangement 18.Integrated circuit comprises first pin set 20 and second pin set 22.First device 14 has first group of data pin 26, the second device 16 and has one group and export into data address pin 28, and storage arrangement 18 comprises one group of lower address pins 30, one group of high address pin 32 and storage stack data pin 34.
Pin shared system 10 according to the present invention has first set of connections, 40, the second set of connections 42, and the 3rd set of connections 44, installs 14, the second devices 16 in order to connect integrated circuit 12 and first, and storage arrangement 18.First set of connections 40 connects first group of data pin 26 and lower address pins group 30 to first pin set 20.Second set of connections 42 is gone into data address pin set 28 this second pin set 22 to this integrated circuit 12 in order to connected storage data pin group 34 and output.Second set of connections 42 also comprises a register 46, is connected in output and goes between the data address pin set 28 and second pin set 22, can temporarily store data, subsequently with data latching.Wherein the output of this group is gone into data address pin 28 and is comprised one group of second device data input pin 281, one group of second device data output pin 282, and one group of second unit address pin 283, this register 46 then is connected in this and organizes between the second unit address pin 283 and this second group of pin 22.The 3rd set of connections 44 is in order to connect register 46 to second pin set 22 of this group high address pin 32 and second set of connections 42.Wherein, second pin set 22 of integrated circuit 12 can comprise one group of integrated circuit address pin 221 and one group of integrated circuit data pin 222, these group integrated circuit data pin 222, the three set of connections 44 that make this second set of connections 42 be connected to second pin set 22 then can be connected to this group integrated circuit address pin 221 of second pin set 22.
Table one is each set of connections and first device, 14, the second devices 16, and storage arrangement 18 is shared the connecting line table:
Table one
See also table one, first set of connections, 40, the second set of connections 42, and the 3rd set of connections 44 as shown in Table 1 are by first device, 14, the second devices 16, and the degree of share of storage arrangement 18.In this pin shared system, first device 14 is with second device, 16 not shared any set of connections.First set of connections 40 is shared to transfer data to first pin set 20 of integrated circuit 12 with the data pin 26 of first device 14 by the lower address pins 30 of storage arrangement 18.Second set of connections 42 is gone into data address pin 28 by the memory data pin 34 of storage arrangement 18 with the output of second device 16 and is shared to transfer data to this group integrated circuit data pin 222 of second pin set 22.This first group of integrated circuit address pin 221 of the high address pin 32 of 44 connected storage devices 18 of the 3rd set of connections and breech lock activation to the second pin set 22 of the register 46 on second set of connections 42.At this moment, first pin set of integrated circuit 12 is shared with storage arrangement 18 by first device 14, and the integrated circuit address pin 221 of integrated circuit 12 and integrated circuit data pin 222 are shared with storage arrangement 18 by second device 16.
Table two uses and the signal table of comparisons for pin shared system 10 devices of the present invention.
Table two
According to the description of table two, transverse axis is the peripherals user mode of pin shared system 10, and the longitudinal axis is then represented the signal that transmitted in three set of connections.When storage arrangement 18 was used, first set of connections 40 was in order to transmission low address signal, and second set of connections 42 is in order to the transmission memory data-signal, and the 3rd set of connections 44 is in order to transmit the high address signal to storage arrangement 18.When first device 14 was used, first set of connections 40 was in order to transmission of data signals.
Desire to write this second device 16 o'clock as data, (AddressLatch Enable is ALE) to register 46 in order to the instruction of transport address breech lock in order to 44 of timesharing ground transmission data or address signal to the second device 16, the three set of connections for second set of connections 42.At this moment, second set of connections 42 transfers to register 46 in the very first time with address signal and deposits, and wait address latch instruction, and the 3rd set of connections 44 transport address breech locks instruct to register 46 so that address date be transferred to second device 16 this organize the second unit address pin 283.When second time, second set of connections 42 is with this group second device data input pin 281 of another data information transfer to the second device 16.Because first device, 14 and second device, 16 no shared wiring or pins, so first device, 14 and second device 16 of pin shared system 10 can operate simultaneously.
See also Fig. 2, Fig. 2 is the synoptic diagram of Fig. 1 integrated circuit 12.Integrated circuit 12 is in order to decision storage arrangement (not shown), the first device (not shown) and second device (not shown) use order separately.Integrated circuit 12 comprises pin and selects module 50 (Pin Mux Selection Module) and control module 52 (Control Module).Control module 52 comprises resolver 54, and Memory Controller 56, the first Setup Controllers 58, and second Setup Controller 60 are with decision peripherals use order separately.Pin selects 50 of modules be connected with first pin set 20 and second pin set 22 by resolver 54 controls, in order to transmit Memory Controller 56, first Setup Controller 58, and first pin set 20 that controls signal to of second Setup Controller 60 communicates with a plurality of signals to peripherals with second pin set 22 and via the first set of connections (not shown), the second set of connections (not shown) and the 3rd set of connections (not shown).
When storage arrangement is used, resolver 54 (Arbitrator) in the control module 52 will decide that (Arbitrate) selects module 50 by Memory Controller 56 accesses (Access) pin, pin selects module 50 further with first set of connections 40, second set of connections 42, and the 3rd set of connections 44 distribute and give Memory Controller 56, with transmission signals and control store apparatus 18.
When storage arrangement 18 is not used, the resolver 54 (Arbitrator) in the control module 52 will be decided (Arbitrate) first Setup Controller 58 and the state of second Setup Controller 60 for being used.At this moment, but first Setup Controller, 58 accesses, first device 14, but second device 16 of 60 accesses of second Setup Controller simultaneously.Pin selects module 50 further the 3rd set of connections 44 and 42 distribution of second set of connections to be given second Setup Controller 60 and second device 16, and first Setup Controller 58 and first is given in the distribution of first set of connections, 40 lines install 14, so that integrated circuit 12 is transmitted signals to first device, 14 and second device 16 simultaneously.
See also Fig. 3, Fig. 3 is the synoptic diagram of second embodiment of pin shared system 10 of the present invention.Compare with last embodiment, further increase by the 4th set of connections 66 in the present embodiment, and first logic gate 68, second logic gate 70.The 4th set of connections 66 connects reading pin 72, writing the integrated circuit control pin 223 of pin 74 and storer control pin 76 to second pin set 22 of storage arrangement 18 of second device 16.First logic gate 68 and second logic gate 70 are positioned on the 4th set of connections 66, respectively with read pin 72 and write pin 74 and be connected.In addition, originally, further more was connected, installed 16 read pin 72, write pin 74 with control transmission to the second with first logic gate 68, second logic gate 70 in order to connect the 3rd set of connections 44 of high address pin 32 and register 46 to second pin set 22.
See also table three, table three is each set of connections of second embodiment of the invention and first device, 14, the second devices 16, and storage arrangement 18 is shared the connecting line table:
Table three
Compare with first embodiment, second embodiment further with the 4th set of connections 66 by read pin 72, write pin 74, storer control pin 76 is shared, make the integrated circuit control pin 223 of second pin set 22 be able to share with storage arrangement 18, and this 4th set of connections 66 is not connected to first and install 14 by second device 16.First pin set 40 of integrated circuit 12 is shared with storage arrangement 18 by first device 14, the integrated circuit address pin 221 of integrated circuit 12 and integrated circuit data pin 222 are shared with storage arrangement 18 by second device 16, and the integrated circuit memory control pin 223 of integrated circuit 12 is shared with storage arrangement 18 by second device 16.
See also table four, table four uses and the signal table of comparisons for second embodiment of the present invention device.
Table four
The transverse axis of table four is the peripherals user mode of pin shared system 10, and the longitudinal axis is then represented the signal that transmitted in three set of connections.When storage arrangement 18 was used, first set of connections 40, second set of connections 42 and the 3rd set of connections 44 were used to control store apparatus 18 as aforementioned.The 4th set of connections 66 controls signal to storer control pin 76 in order to transmission memory under this state.When first device 14 was used, first set of connections 40 was in order to transmission of data signals to the first device 14.When second device 16 was used, the signal transfer mechanisms in first embodiment, the 3rd set of connections 44 further transmitted output and goes into read-write to the first logic gate 68 and second logic gate 70.66 of the 4th set of connections transmit memory idle (MI) signal to the first logic gate 68 and second logic gate 70.68,70 of two groups of logic gates judge that output goes into the value of read-write and storer control signal, the result of logical operation is sent to respectively reads pin 72 and write pin 74.This moment, integrated circuit 12 was still transmitted signals to first device, 14 and second device 16 simultaneously.
See also Fig. 4, Fig. 4 is the synoptic diagram of the third embodiment of the present invention.Compare with first embodiment, further increase the 4th set of connections 66 and the 3rd logic gate 80 in the present embodiment.The device control pin 82 that the 4th set of connections 66 connects second device 16 and storer control pin 76 to second pin set 22 of storage arrangement 18 integrated circuit control pin 223.The 3rd set of connections 44 further is connected with the 3rd logic gate 80, and the 3rd logic gate 80 further is connected with the device control pin 82 of second device 16 again.The 3rd set of connections 44 further with second device 16 read pin 72, and write pin 74 and be connected.
First device according to pin shared system of the present invention can be the integrated type electrical drive unit (Integrated Device Electronic Device) of integrated type electrical interface, second device then can be a microcontroller device (Micro Controller Device) that comprises microcontroller, and this storage arrangement then can be flash memory (Flash Memory).
Compare with known pin shared system, this pin shared system can make integrated circuit control an above peripherals simultaneously, and the pin of integrated circuit can be shared by peripherals, to promote the efficient that peripherals uses.
Via the above detailed description of preferred embodiments,, and be not to come category of the present invention is limited with above-mentioned disclosed preferred embodiment for hope can be known description feature of the present invention and spirit more.On the contrary, its objective is that hope can contain various changes and have in the category of claim of being arranged in of equivalence institute of the present invention desire application.
Claims (11)
1. pin shared system, this pin shared system comprises:
One integrated circuit, this integrated circuit comprise one first pin set and one second pin set;
One first device, this first device comprises one first group of data pin;
One second device, this second device comprises one group and exports into the data address pin;
One storage arrangement, this storage arrangement comprise one group of lower address pins, one group of high address pin and storage stack data pin;
One first set of connections connects this first group of data pin and this group lower address pins this first pin set to this integrated circuit;
One second set of connections, connect the output of this group memory data pin and this group and go into data address pin this second pin set to this integrated circuit, wherein this second set of connections comprises a register, being connected in this group output goes between data address pin and this second pin set, in order to temporary transient storage one group address message, and when receiving address latch instruction, this group address message of being stored is sent to this second device; And
One the 3rd set of connections, the breech lock instruction of register that connects the high address pin of this storage arrangement and this second set of connections be to this second pin set of this integrated circuit,
Wherein, this integrated circuit is controlled this first set of connections, this second set of connections and the 3rd set of connections and is communicated a plurality of signals to this storage arrangement, this first device and this second order of installing, so that this integrated circuit is able to communicate with this first device and this second device simultaneously.
2. pin shared system as claimed in claim 1, wherein this integrated circuit comprises:
One control module comprises a Memory Controller, and one first Setup Controller, and one second Setup Controller are to determine this storage arrangement, this first device and this second use order of installing; And
One pin is selected module, is connected to this control module, selecting this first set of connections, and this second set of connections, or the 3rd set of connections is to transmit these a plurality of signals.
3. pin shared system as claimed in claim 1, wherein this second pin set comprises one group of integrated circuit address pin and one group of integrated circuit data pin, this second set of connections is connected to this group integrated circuit data pin, and the 3rd set of connections is connected to this group integrated circuit address pin.
4. pin shared system as claimed in claim 1, wherein this group output of this second device is gone into the data address pin and is comprised one group second and install the data input pin, one group of second device data output pin, and one group of second unit address pin, this register is connected in this and organizes between the second unit address pin and this second pin set.
5. pin shared system as claimed in claim 1, also comprise one the 4th set of connections and one group of logic gate, with connect one of this second device read pin, write pin, with the integrated circuit control pin of a storer of this storage arrangement control pin to this second pin set of this integrated circuit, this group logic gate also links to each other with the 3rd set of connections.
6. pin shared system as claimed in claim 1, also comprise one the 4th set of connections and a logic gate, with storer control pin of the device control pin that connects this second device and this storage arrangement integrated circuit control pin to this second pin set of this integrated circuit, this logic gate with this second install one read pin and and write pin and link to each other with the 3rd set of connections.
7. as claim 5 or the 6th described pin shared system, this integrated circuit is controlled this first set of connections, this second set of connections, the 3rd set of connections and is communicated a plurality of signals with the 4th set of connections to this storage arrangement, this first device and this second order of installing, so that this integrated circuit is able to communicate with this first device and this second device simultaneously.
8. pin shared system as claimed in claim 7, wherein this integrated circuit comprises:
One control module comprises a Memory Controller, and one first Setup Controller, and one second Setup Controller are to determine this storage arrangement, this first device and this second use order of installing; And
One pin is selected module, selecting this first set of connections, and this second set of connections, the 3rd set of connections, or the 4th set of connections is to transmit these a plurality of signals.
9. pin shared system as claimed in claim 1, wherein this first device comprises an integrated electronic formula drive unit.
10. pin shared system as claimed in claim 1, wherein this second device comprises a microcontroller device.
11. pin shared system as claimed in claim 1, wherein this storage arrangement comprises a flash memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100328830A CN100351827C (en) | 2004-04-13 | 2004-04-13 | Pin sharing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100328830A CN100351827C (en) | 2004-04-13 | 2004-04-13 | Pin sharing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1684056A CN1684056A (en) | 2005-10-19 |
| CN100351827C true CN100351827C (en) | 2007-11-28 |
Family
ID=35263406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100328830A Expired - Fee Related CN100351827C (en) | 2004-04-13 | 2004-04-13 | Pin sharing system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100351827C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9129072B2 (en) * | 2012-10-15 | 2015-09-08 | Qualcomm Incorporated | Virtual GPIO |
| US10002102B2 (en) * | 2015-03-13 | 2018-06-19 | Microchip Technology Incorporated | Low-pin microcontroller device with multiple independent microcontrollers |
| CN113987991B (en) * | 2021-09-29 | 2022-09-27 | 展讯半导体(南京)有限公司 | Signal transmission device and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6044412A (en) * | 1997-10-21 | 2000-03-28 | Vlsi Technology, Inc. | Integrated circuit pin sharing method and apparatus for diverse memory devices by multiplexing subsets of pins in accordance with operation modes |
| CN1361458A (en) * | 2000-12-27 | 2002-07-31 | 扬智科技股份有限公司 | Computer system backing up different type of DRAMs |
| US20030074510A1 (en) * | 2001-10-11 | 2003-04-17 | International Business Machines Corporation | Method and apparatus for sharing signal pins on an interface between a system controller and peripheral integrated circuits |
| TW546567B (en) * | 2002-02-25 | 2003-08-11 | Sunplus Technology Co Ltd | The Simplification and making of reliable one-to-multiple access system |
-
2004
- 2004-04-13 CN CNB2004100328830A patent/CN100351827C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6044412A (en) * | 1997-10-21 | 2000-03-28 | Vlsi Technology, Inc. | Integrated circuit pin sharing method and apparatus for diverse memory devices by multiplexing subsets of pins in accordance with operation modes |
| CN1361458A (en) * | 2000-12-27 | 2002-07-31 | 扬智科技股份有限公司 | Computer system backing up different type of DRAMs |
| US20030074510A1 (en) * | 2001-10-11 | 2003-04-17 | International Business Machines Corporation | Method and apparatus for sharing signal pins on an interface between a system controller and peripheral integrated circuits |
| TW546567B (en) * | 2002-02-25 | 2003-08-11 | Sunplus Technology Co Ltd | The Simplification and making of reliable one-to-multiple access system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1684056A (en) | 2005-10-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1188948C (en) | Reconfigurable computing system | |
| US6230223B1 (en) | Dual purpose apparatus method and system for accelerated graphics or second memory interface | |
| CN1270250C (en) | Method and device for raising serial storage equipment reliability and elasticity | |
| CN101036125A (en) | Masking within a data processing system having applicability for a development interface | |
| CN1881478A (en) | Memory device | |
| CN101231879A (en) | Data access and multi-chip controller | |
| TWI727236B (en) | Data bit width converter and system on chip thereof | |
| CN1797381A (en) | On-chip data transmission control apparatus and method | |
| CN1180430A (en) | Memory controller which executes read and write commands out of order | |
| CN1650276A (en) | ATA/SATA combined controller | |
| CN1653435A (en) | Mapping data masks in hardware by controller programming | |
| CN1707454A (en) | Hub, memory module, memory system and methods for reading and writing to the same | |
| CN100351827C (en) | Pin sharing system | |
| CN1181438C (en) | Method for controlling access of asynchronous clock devices to shared storage device | |
| CN102237867B (en) | Semiconductor module including module control circuit and method for controlling the same | |
| US20090138633A1 (en) | Computer, external storage and method for processing data information in external storage | |
| CN101034373A (en) | Controller of external storing device and address change method based on same | |
| US11693798B2 (en) | Layered ready status reporting structure | |
| CN1924833A (en) | Processing modules with multilevel cache architecture | |
| CN1725205A (en) | Combined access device and method of controller and multiple programmable logical device | |
| CN1279451C (en) | Drive capacity setting method and program and its driver circuit | |
| CN1967420A (en) | Series PLC host computer and fast parallel communication interface of expanding machine | |
| CN1655277A (en) | Multifunctional data storage device and method thereof | |
| US7890687B2 (en) | Motherboard and interface control method of memory slot thereof | |
| CN114747143A (en) | Programmable device configuration memory system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071128 Termination date: 20190413 |