JPH07168750A - Information processor - Google Patents

Abstract

PURPOSE:To cope with plural kinds of architecture by one device without increasing a cost and complicating a design. CONSTITUTION:A storage element 3 is connected to a field programmable gate array 1 via a socket 2, and the internal logic circuit of the field programmable gate array 1 can be defined according to program data stored in the storage element 3. Memory 6 connected corresponding to desired address space based on an inputted signal, a combination circuit which generates a control signal to perform selection for the memory 6 and a peripheral LSI 7, etc., and a logic circuit which generates a control signal to perform the optimum quick access in accordance with the memory 6 and the peripheral LSI 7, etc., connected based on the inputted signal are included in the internal logic circuit of the field programmable gate array 1 defined by the program data in the storage element 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus that can support a plurality of architectures.

[0002]

2. Description of the Related Art Conventionally, in an information processing apparatus such as a personal computer, when a memory group 34 and a peripheral LSI group 35 are connected to a central processing unit 32 as shown in FIG. A control circuit 33 is provided in order to realize an access in consideration of the arrangement of the peripheral LSI group 35 in the address space and their access time, that is, their own architecture.

In the control circuit 33, the clock signal 131 from the oscillator 31 to the central processing unit 32, the control signal 132 from the central processing unit 32, the central processing unit 32 to the memory group 34 and the peripheral LSI group 35. Control signal 135 in consideration of the address space arrangement, access time, etc. described above.

A control signal 135 generated by the control circuit 33
Is input to the memory group 34 and the peripheral LSI group 35,
In the memory group 34 and the peripheral LSI group 35, the control signal 1
According to 35, data is exchanged with the central processing unit 32 via the data bus 134 based on the address signal 133 from the central processing unit 32.

When a plurality of architectures are realized in the information processing apparatus having the above-mentioned configuration, as shown in FIG.
A control circuit 36 for realizing each architecture,
37 is provided, and control signals 136 and 137 from the control circuits 36 and 37 corresponding to the architecture to be realized are output to the memory group 34 and the peripheral LSI group 35 via the selection circuit 38.

In this case, a selection signal 138 for instructing to select the control circuit 36, 37 corresponding to the architecture to be realized is given to the selection circuit 38, so that the control signal 136, 36 from the corresponding control circuit 36, 37 is supplied. 137
Is selected by the selection circuit 38 and output as a control signal 139 to the memory group 34 and the peripheral LSI group 35 via the selection circuit 38.

[0007]

In the above-mentioned conventional information processing apparatus, when a plurality of architectures are realized by one apparatus, it is necessary to provide a logic circuit for realizing each required architecture. There is a problem that the scale is increased, the cost for realizing a plurality of architectures is increased, and the design is complicated.

Further, since it is possible to deal only with the architecture assumed at the time of designing the device, there is a problem that it is not possible to deal with the case where a new architecture is realized or when the user freely constructs the architecture. is there.

Therefore, an object of the present invention is to solve the above problems and provide an information processing apparatus capable of supporting a plurality of architectures with a single apparatus without increasing cost and complicating design. Especially.

[0010]

An information processing apparatus according to the present invention is an information processing apparatus including a memory device, a peripheral device, and a central processing unit for controlling the memory device and the peripheral device. A programmable gate array that converts a control signal from a central processing unit into a signal corresponding to the memory device and the peripheral device and that can change an internal logic circuit by external program data, and is attachable to and detachable from the programmable gate array. A storage element that is connected and stores the program data.

[0011]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a storage element 3 is connected to a field programmable gate array (hereinafter referred to as FPGA) 1 via a socket 2, and an internal logic circuit of the FPGA 1 is defined according to program data stored in the storage element 3. It has become so. The storage element 3 is detachably connected to the FPGA 1 via the socket 2.

The FPGA 1 has a status signal 102 and an address signal 103 input from the central processing unit 4,
The control signal 110 is generated based on the clock signal 101 input from the oscillator 5 and output to the memory 6 and the peripheral LSI 7 in the predetermined area 8.

Based on the input signal, the internal logic circuit of the FPGA 1 defined by the program data of the storage element 3 selects the memory 6 and the peripheral LSI 7 connected according to the desired address space. Included is a combinatorial circuit that generates a control signal 110 for performing.

In addition, a logic circuit for generating a control signal 110 for realizing an optimum access speed according to the connected memory 6 and peripheral LSI 7 is also included in the internal logic circuit based on the input signal. Is included.

The central processing unit 4 receives the status signal 10
By outputting 2 to FPGA1, the address signal 103
And the memory 6 and peripheral LSI via the data bus 104
Data is written to and read from 7.

FIG. 2 is a block diagram showing a configuration example of the FPGA 1 of FIG. In the figure, a control signal generation block 1
0 is the read / write signal (W / R) 102a of the status signal 102 from the central processing unit 4 and the memory /
Peripheral LSI access instruction signal (M / IO) 102b,
The data / code access instruction signal (D / C) 102c is input.

The control signal generation block 10 decodes each of the above-mentioned input signals, and a memory read signal (MRD) of the control signals 110 to the memory 6 and the peripheral LSI 7.
111, a memory write signal (MWR) 112, a peripheral LSI read signal (IORD) 113, and a peripheral LSI write signal (IOWR) 114 are generated and output.

Here, if the write / read signal 102a is at a high level, it indicates a read operation, and if it is at a low level, it indicates a write operation. When the memory / peripheral LSI access instruction signal 102b is at high level, it indicates access to the memory 6, and when it is at low level, it indicates access to the peripheral LSI 7. Further, the data / code access instruction signal 102c indicates a data access when it is at a high level, and indicates a program code access when it is at a low level.

Upon receiving the address signal 103 from the central processing unit 4, the selection signal generation block 11 decodes the address signal 103 to decode the address signal 103 and the memory 6 and the peripheral LSI.
Memory control signal (MC
S) 115 and peripheral LSI selection signal (IOCS) 116
And generate and output.

Here, when the address of the area allocated to itself is input, the selection signal generation block 11 activates the memory selection signal 115 or the peripheral LSI selection signal 116 corresponding to the area.

Ready signal generation block 1
2 receives the address strobe signal (ADS) 102d of the status signal 102 from the central processing unit 4, inputs the clock signal 101 from the oscillator 5, and selects the memory selection signal 115 from the selection signal generation circuit 11 and the peripheral LSI.
The selection signal 116 is input.

When the ready signal generating block 12 receives the above signals, it generates and outputs a ready signal (READY) 117 of the control signals 110 to the memory 6 and the peripheral LSI 7.

The ready signal generating block 12 is a memory selection signal 115 generated by the selection signal generating block 11.
Alternatively, the execution target device is recognized by the peripheral LSI selection signal 116, and the ready signal 117 is enabled at a timing corresponding to the access speed of each execution target device. The address strobe signal 102d goes low to indicate the start of an access cycle.

Here, for example, when it is desired to make the arrangement positions of the memory 6 or the peripheral LSI in the entire address space different, the combination circuit portion for address decoding formed in the selection signal generation block 11 is a desired circuit. It can be realized by replacing with.

FIG. 3 shows the ready signal generation block 12 of FIG.
3 is a block diagram showing an example of the circuit of FIG. 3A shows the circuit of the ready signal generation block 12 before the change, and FIG.
(B) shows the circuit of the ready signal generation block 12 after the change.

The counter 12a is a 4-bit counter and counts up at the rising edge of the clock signal (CLK) 101. Further, the counter 12a is configured such that the counter value is initialized when the address strobe signal 102d becomes low level.

Before the circuit of the ready signal generation block 12 is changed, if the counter value of the counter 12a becomes "3" when the peripheral LSI selection signal 116 becomes active (low level), the logical sum circuits 12b and 12c are logically connected. The ready signal 117 becomes active (low level) via the product circuit 12d [see FIG. 3 (a)].

After the circuit of the ready signal generation block 12 is changed, when the counter value of the counter 12a becomes "5" when the peripheral LSI selection signal 116 becomes active (low level), the logical sum circuits 12b and 12c are logically connected. The ready signal 117 becomes active (low level) via the product circuit 12d [see FIG. 3 (b)].

As described above, the program data for the FPGA 1 of the memory element 3 is changed to change the ready signal generation block 1
By changing the circuit of No. 2, the memory 6 and the peripheral LSI 7
It is possible to secure the access time according to.

FIG. 4 is a time chart showing the operation of the FPGA 1 of FIG. FPGA using these FIG. 2 to FIG.
The operation of No. 1 will be described. The operation of writing the data “AA55” into the address “0F0F” of the memory 6 will be described below.

In this case, from the central processing unit 4 to the FPG
The write / read signal 102a to A1 is at a low level indicating a write operation, the memory / peripheral LSI access instruction signal 102b is at a high level indicating access to the memory 6, and the data / code access instruction signal 102c is at a high level indicating data access. Becomes

The control signal generation block 10 decodes each of the above input signals and activates the memory write signal 112 (low level).

Further, the selection signal generation block 11 outputs' 0F0 as the address signal 103 from the central processing unit 4.
When F'is input, since the address '0F0F' indicates the area of the memory 6, the memory selection signal 115 is activated (low level).

As a result, at the timing when the ready signal 117 from the ready signal generating block 12 becomes active (low level), the address' 0F is stored in the memory 6.
Data'AA55 'is written in 0F'.

FIG. 5 is a diagram showing a connection example of a replaceable memory and a peripheral LSI in one embodiment of the present invention. Figure 5
FIG. 5A shows a connection example of the replaceable memory 22, and FIG.
(B) shows an example of connection of the replaceable peripheral LSI 24.

In FIG. 5A, the memory 22 has an address signal 103 and a data bus 104 from the central processing unit 4 via a connector (connector) 21 commonly used with other memories (not shown). And the control signal 110 from the FPGA 1.

Further, in FIG. 5B, the peripheral LSI 2
Reference numeral 4 denotes an address signal 103 from the central processing unit 4, a data bus 104, and an FPGA via a connector (connector) 23 that is commonly used with other peripheral LSIs (not shown).
1 and the control signal 110 from 1.

The operation of one embodiment of the present invention will be described with reference to FIGS. At the time of initialization immediately after the power is turned on, the FPGA 1 automatically receives the program data from the storage element 3, and the internal logic circuit is defined according to the contents of the program data.

The program data sent from the storage element 3 is designed in advance so as to realize a logic circuit having a desired function with a dedicated programming device, and is written in the storage element 3 in advance.

As a result, the internal logic circuit of the FPGA 1 is defined by the program data written in the memory element 3, so that the information processing apparatus according to the embodiment of the present invention determines the address space and access speed according to the program data. It works as a device you have.

If it is desired to use this device in an address space different from the address space realized by the above-mentioned program data, the address decoding circuit in the FPGA 1 is designed separately, and the program data for realizing the logic circuit is designed. It can be realized by creating and writing in the storage element 3.

In this case, by turning on the power again with the storage element 3 inserted in the socket 2 and re-initializing,
The FPGA 1 can form a new and separate desired address space.

On the other hand, in the same way as the above-mentioned processing, the FPG
The access time of the memory 6 and the peripheral LSI 7 can be freely set by changing the internal logic circuit of A1.

Therefore, as shown in FIG.
The peripheral LSI 24 and the like are configured to be electrically connectable by the connectors 21 and 23, so that data reading and writing are performed at an access speed according to various connected memories and peripheral LSIs. be able to. Therefore, it is possible to flexibly construct an efficient system.

In this case, for example, two access speeds are different.
Assuming that there is a board having a common connector for various kinds of memories, a memory having a slow access speed or a memory having a fast access speed can be connected through the connector.

At this time, if the program data is defined in the ready signal generation block 12 so that the ready signal 117 is generated at a timing in time for a memory having a slow access speed, the memory having a slow access speed is defined. Can be accessed without problems in.

When a board equipped with a memory having a high access speed is connected instead of the board equipped with a memory having a slow access speed, which has just been connected, the ready signal generation block 12 defined previously operates without any problem. Since the system performance is improved by performing faster memory access, the program data may be defined so that the ready signal generation block 12 described above becomes a circuit that generates a ready signal at a faster timing.

As described above, even when the memories having various access speeds are connected via the connector, the FPG
Optimal access can be performed by changing the definition of the program data for A1.

Similarly, even when there are various boards having different memory capacities, the combination circuit by the address signal 103 of the selection signal generation block 11 of the FPGA 1 becomes a circuit corresponding to the respective memory capacities. By defining the program data, it is possible to respond more flexibly.

Further, the functions of peripheral LSIs such as an image display control LSI and a data transmission / reception control LSI can be made into a logic circuit configuration desired by the user by the same means as described above.

In this case, an FPGA having a sufficient number of gates for accommodating the above peripheral LSI is adopted.
A storage element in which program data for forming a logic circuit having a desired peripheral LSI function is written is connected therein.

Furthermore, by connecting the electrical signal that needs to be connected to the outside of the system from the terminal of the FPGA to the outside, the function of the peripheral LSI can be realized in the logic circuit configuration desired by the user.

As the above-mentioned FPGA, those already developed and marketed can be used. The number of gates aggregated in development and commercialization is currently increasing from tens of thousands of gates every year, and products with shorter internal delay time have been commercialized.

As described above, the storage element 3 that stores the control circuit portion of the information processing device in the FPGA 1 and also stores the program data for defining the circuit configuration of the FPGA 1.
By connecting the FPGA 1 and the FPGA 1 via the socket 2 so that they can be easily exchanged, it becomes possible to exchange the program data written in the storage element 3 and realize a plurality of architectures by one device.

Therefore, one device can support a plurality of architectures without increasing costs and complicating the design.

[0057]

As described above, according to the present invention, the control signal from the central processing unit is converted into a signal corresponding to the memory device and the peripheral device, and the internal logic circuit can be freely changed by the program data from the outside. A programmable gate array and a storage element that is detachably connected to the programmable gate array and stores program data, so that a single device can be used for a plurality of architectures without increasing cost or complicating the design. It has the effect of being able to respond.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of the field programmable gate array in FIG.

FIG. 3A is a diagram showing a circuit of a ready signal generation block before change, and FIG. 3B is a diagram showing a circuit of a ready signal generation block after change.

FIG. 4 is a time chart showing the operation of the field programmable gate array of FIG.

FIG. 5A is a diagram showing a connection example of a replaceable memory,
(B) is a diagram showing a connection example of a replaceable peripheral LSI.

FIG. 6 is a block diagram showing a configuration of a conventional example.

FIG. 7 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 Field Programmable Gate Array 2 Socket 3 Storage Element 4 Central Processing Unit 6,22 Memory 7,24 Peripheral LSI 10 Control Signal Generation Block 12 Selection Signal Generation Block 13 Ready Signal Generation Block 21,23 Connector

Claims (3)

[Claims] 1. An information processing apparatus including a memory device, a peripheral device, and a central processing unit for controlling the memory device and the peripheral device, wherein the control signal from the central processing unit is the memory device. And a programmable gate array which is converted into a signal according to the peripheral device and which can change the internal logic circuit by external program data, and a storage element which is detachably connected to the programmable gate array and stores the program data. An information processing device comprising: 2. In the programmable gate array, the internal logic circuit converts the control signal into a signal according to an arrangement of the memory device and the peripheral device in an address space composed of the memory device and the peripheral device. The information processing apparatus according to claim 1, wherein the information processing apparatus is configured to perform. 3. The programmable gate array according to claim 1, wherein the internal logic circuit is configured to convert the control signal into a signal according to an access time of each of the memory device and the peripheral device. Alternatively, the information processing apparatus according to claim 2.