JPH01121965A - Microprocessor - Google Patents

Abstract

PURPOSE:To perform bus wait control without a bus wait signal generating circuit by providing a wait register and an OR circuit which generate an internal wait signal during a period indicated by the number of wait cycles. CONSTITUTION:A wait register 48 sets 5 as the initial value of the number of wait cycles at the time of system initialization, and an internal wait indicating signal 62 is outputted from a microprogram control circuit 500 when an arithmetic part 47 reads data from a first memory 43. The register 48 outputs an internal wait signal 63 in accordance with the number of wait cycles when receiving the signal 62, and an OR circuit 49 operates OR between the signal 63 and an external wait signal 64 from a PIO 46 and outputs the result as a wait signal 61. When a circuit 50 accesses the memory 43, the circuit 50 determines a required wait cycle period and outputs a data enable signal 54 to open a data register 51, and data is read out of the memory 43, thus performing the bus wait control without the bus wait signal generating circuit.

Description

[Detailed Description of the Invention] This Industrial Application Field] The present invention relates to a microprocessor, and in particular, it receives the number of wait cycles required when transmitting data with peripherals as a specific program command, and based on this, the present invention relates to a microprocessor. This relates to something that performs bus weight control.

[Conventional technology]

The CPU (CENTRAL) is the central part of information processing equipment such as computers and word processors.
PROCESSING [INIT] equipment such as microprocessor, semiconductor memory and other dedicated LSI (LA)
RGEscAu riEeRATEo c+Rcu+r
) Niyo”) These circuit elements are generally designed to operate in synchronization with a basic clock (this is called a system clock) provided within the system. In dedicated LSIs for processors and human output control, the basic number of clocks required to execute one basic process is called the basic bus cycle number, and this is used as a measure of the information processing ability of the circuit element.In the case of semiconductor memory, The required basic number of bus cycles can be determined from the access time, which represents the operating speed.

Generally, in a CPU device, the access time or basic number of bus cycles differs between the microprocessor and the semiconductor memory or peripheral LSI connected thereto, so a wait signal is used to synchronize human output. Such synchronization control between circuit elements is particularly called bus wait control. As a typical example of this, when a high-speed 32-bit microprocessor accesses the main memory semiconductor memory, it reads the wait signal issued by the memory side from the wait signal input terminal during a memory read cycle or memory write cycle, and then outputs the read weight. For example, necessary wait cycles are inserted depending on the length of the signal. That is, when performing this bus wait control conventionally, a microprocessor takes in a wait signal issued from an external circuit through a wait signal input terminal, and performs bus wait only for a necessary period according to the length of this wait signal. This will be explained using a diagram.

FIG. 3 shows a microprocessor connected to three memories with different access times and a parallel input/output port. First, each part of the figure will be briefly explained. The microprocessor 11 writes information to and reads information from the memories 13 to 15 and the parallel input/output port 16 through the external data bus 12, and includes an arithmetic unit 17 and a microprogram control circuit 1.
8, a data register 19 and an address register 20.

Of these, the arithmetic unit 17 is a microprogram control circuit 18
It also performs arithmetic processing in accordance with program instructions and data taken out from the memory IJ 13 to the memory 15 and the parallel input/output port 16. The data register 19 is a tree-state buffer circuit that connects the internal data bus 21 of the microprocessor 11 and the external data bus 12,
Connect these by bus. address register 29
is a tree-state buffer circuit that connects the internal address bus 23 and external address bus 24 of the microprocessor 11, and connects them by an address enable signal 25. The microprogram control circuit 18 receives write instructions or read instructions issued by the arithmetic unit 17 through an internal data bus 21, and also manually inputs a wait signal 26, based on which the memory 13
The system generates signals for input/output control while appropriately inserting wait cycles to the memory 15 and the parallel output capo 16 according to their access times. The clock generation circuit 31 is a circuit that supplies a system clock signal 32 to the microprocessor 11. The first memory 13 is a high-speed semiconductor memory element and does not require a wait cycle when accessed by the microprocessor 11. The second memory 14 is a medium-speed semiconductor storage element, and requires a wait cycle of one system clock period when accessed by the microprocessor 11. The third memory 15 is a low-speed semiconductor 1α device, and requires a wait cycle of two system clock periods when accessed by the microprocessor 11. The parallel input/output port 16 is a low-speed human output device and issues a wait request signal 33 of four system clock periods in response to access from the microprocessor 11. Wait signal generation circuit 3
4 inputs an external address bus 24 and a wait request signal 33, and from this, a wait signal 26 of the length required when accessing the first memory 13 to third memory 15 and the parallel output capo-j 16 is generated. This is a circuit that outputs .

Next, the operation of bus wait control by the conventional microprocessor 11 will be explained based on this figure. First, when the power is turned on and the system starts up, the arithmetic unit 17
Assume that the third memory 15 performs a memory read by sending an address signal to the internal address bus 23. At this time, the microprogram control circuit 11 outputs the read signal 35 following the address enable signal 25. This brings me to the third memo IJ 15! starts reading operation. The wait signal generation circuit 34 receives this address signal and the memo IJ-de signal 35 and outputs a wait signal 26 for two system clock periods required when reading the third memory 15 to the microprocessor 11. do. Microprogram control circuit 18
When receiving the wait signal 26, the arithmetic unit 17 extends the instructed bus cycle by the period during which the wait signal 26 is active, outputs the data enable signal 22, opens the data register I9, and reads data from the third memory 15. The received data is sent to the internal data bus 21. That is, in this case, a wait cycle corresponding to 2/stem clock is inserted into the normal read cycle, so that the data in the third memory 15 can be read without any problem at this time.

Next, the microprocessor 11 runs in parallel
The case of accessing 6 will be explained.

Performance 3f Suppose that B l 7 sends an address signal and output data to the internal address bus 23 and writes r10 to the parallel output port 16. At this time, the microprogram control circuit 18 outputs an address enable signal 25.
and data enable signal 22 followed by write signal 3
Outputs 6. This allows parallel person output port 16
enters output operation.

At this time, the parallel person output port 16 outputs the wait request signal 33 for four system clock periods. The wait signal generation circuit 34 receives this wait request signal 3.
3, a wait signal 26 for four system clock periods, which is required when writing data to the parallel output port 16, is output to the microprocessor 11.

The microprogram control circuit 18 receives a wait signal 26.
When received, the arithmetic unit 17 extends the instructed bus cycle by the period during which the wait signal 26 is active. That is, in this case, a wait cycle for four system clocks is inserted into the normal read cycle to extend the bus cycle, so that the output to the parallel output port 16 is executed without any problem.

Similarly, the microprocessor 11 connects the second memory 14 to the second memory 14.
When accessing the first memory 13, the wait signal generation circuit 34 generates a wait signal 26 for the I system clock period, and when accessing the first memory 13, it does not generate the wait signal 26, so the microprocessor 11 also generates a wait signal 26 for these memories. Read dry according to the access time)・
It can be performed.

[Problem that the invention seeks to solve]

By the way, in the above-described conventional bus wait control method in a system using a microprocessor, a bus wait signal generation circuit 34 is required to generate the wait signal 26 to be supplied to the microprocessor. Particularly when memories with different access times are used in combination as in the example shown above, the main part becomes complicated and the manufacturing cost becomes high.

Therefore, an object of the present invention is to provide a microprocessor that can perform bus wait control without using such a complicated bus wait signal generation circuit 26.

Means for Solving Two Problems] The microprocessor of the present invention takes in wait cycle information sent from memories and peripheral LSIs through a data bus, and based on this wait cycle information, these memories and peripherals 1=
The period of the wait cycle to be executed when accessing SI is determined. For example, by storing information about its own access time in peripheral memory as wait cycle information, and giving this wait cycle information to the microprocessor before accessing the memory, a complex wait signal generation circuit can be created. Bus weight control can be performed without using.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 1 is a block diagram showing the configuration of this embodiment in which a microprocessor is connected to three memories having different access times and a parallel input/output port. In this embodiment, a wait cycle for the memory is generated by an internal wait signal, and a wait cycle for the parallel input/output port is generated by an external wait signal.

First, each part of the figure will be briefly explained. The microprocessor 41 writes information to and reads information from the memories 43 to 45 and the parallel input/output port 46 through the external data bus 42, and includes an arithmetic unit 47, an eight register 48, an OR circuit 49,
Microprogram control circuit 50, data register 51
and an address register 52. Among these, the arithmetic unit 47: controls the microprogram control circuit 50 and the wait register 48, and performs arithmetic processing according to program instructions and data taken out from the first memory 43 to third memory 45 and the parallel input/output port 46. It is something to do. These program instructions also include unit cycle setting instructions, which will be described later. The data register 511 is a tree-state buffer circuit that connects and disconnects the internal data bus 53 of the microprocessor 41 and the external data bus 42, and connects the data bus by receiving the data enable signal 54. The address register 52 is the microprocessor 41
This is a tree-state buffer circuit that connects and disconnects an internal address bus 55 and an external address bus 56, and connects them by receiving an address enable signal 57. The microprogram control circuit 50 receives a write instruction or a read instruction issued by the arithmetic unit 47 through an internal data bus 53, and also manually inputs a wait signal 61 to control the memory 4 based on this.
3 to the memory 45 and the parallel input/output port 46, the human output control signal and the internal wait instruction signal 62 are generated while appropriately inserting wait cycles corresponding to these access times j. The wait register 48 receives from the internal data bus 53 a wait cycle setting command representing the access time of peripheral devices such as the memories 43 to 45 and the parallel input/output port 46, so that when accessing these memories and I/○ devices, This circuit stores the required number of wait cycles and outputs the internal wait signal 63 during the period indicated by this number of wait cycles. The OR circuit 49 manually inputs the wait request signal 64 (external wait signal) output from the parallel input/output port 46 and the internal wait signal 63 output from the wait register 48.
This is a circuit that generates a wait signal 61 by calculating the logical sum of these. Clock generation circuit 65 is a circuit that supplies system clock signal 66 to microprocessor 41. The first memory 43 is a high-speed semiconductor memory element and does not require a wait cycle when accessed by the microprocessor 41. The second memory 44 is a medium-speed semiconductor memory element, and requires a wait cycle of one system clock period when accessed by the microprocessor 41. Further, the third memory 45 is a low-speed semiconductor storage element, and requires a wait cycle of two system clock periods when accessed by the microprocessor 41. Parallel input/output port 46
is a low-speed human output device and the microprocessor 41
A wait request signal 64 for four system clock periods is issued in response to an access from.

Next, the operation of the microprocessor 41 will be explained based on this figure. First, when the power is turned on and the system starts up, the wait register 48 sets "5'° as the initial value of the number of wait cycles.

At this time, it is assumed that the arithmetic unit 47 sends an address signal to the internal address bus 55 to read the memory of the first memory 43. At this time, the microprogrammed i11 circuit 50 outputs an address enable signal 57j, followed by a read signal 71 and an internal wait instruction signal 62. This causes the first memory 43 to enter a read operation. At this time, the wait register 48 receives the internal wait instruction signal 62.
When receiving the signal, it outputs an internal wait signal 63 for 5 system clock periods according to the number of wait cycles stored therein. The OR circuit 49 manually inputs the internal weight signal 63 and outputs it as it is as the weight signal 61.

Upon receiving the wait signal 61, the microprogram control circuit 50 extends the bus cycle instructed by the arithmetic unit 47 by the period during which the wait signal 61 is active, and then outputs the data enable signal 54 to open the data register and read the data from the first memory. The data read from 43 is sent to internal data bus 53. That is, in this case, eight cycles corresponding to five system clocks are inserted into the normal read cycle. Since the device with the slowest access time in the system of this embodiment is the parallel input/output port 46 which requires a wait cycle of four system clock periods, data in the first memory 43 can be read at this time without any problem.

Next, assume that operation @547 reads a wait cycle setting command indicating its own wait number of zero from the first memory 43. When the arithmetic unit 47 decodes this wait cycle setting instruction, it sends information about the number of waits to the wait register 48 .

FIG. 2 is a conceptual diagram showing the structure of this wait cycle setting command. In the figure, an operation code 81 is an identification code for notifying the calculation unit 47 that this instruction is a wait cycle setting instruction. Wait count 82 represents the number of wait cycles to be executed in subsequent bus cycles.

When the wait register 48 receives this wait count 82 from the arithmetic unit 47, it sets it in an internal register as the number of wait cycles. In this case, the number of wait cycles set is zero, so the wait register 4
8 does not generate the internal wait signal 63 even if it receives the internal wait instruction signal 62. That is, the bus cycles after this time are executed in a no-wait manner without adding any wait cycles. When the wait count 82 of the wait cycle setting command is 1 wait, 2 waits, or 3 waits, the same operation as above is performed, and the subsequent bus cycles have waits of 1 wait cycle, 2 wait cycles, and 3 wait cycles, respectively. A cycle is inserted and executed.

Next, the microprocessor 41 connects to the parallel input/output port 4.
The case of accessing 6 will be explained.

The performance section 47 sends an address signal and output data to the internal address bus 55 and outputs an I/O signal to the parallel input/output port 46.
Assume that 10 writes are performed. At this time, microprogram control circuit 50 outputs write signal 83 and internal wait instruction signal 62 following address enable signal 57 and data enable signal 54. This causes the parallel input/output port 46 to enter output operation. At this time, the parallel input/output port 46 outputs a wait request signal 64 for four system clock periods. The OR circuit 49 receives the wait request signal 64 manually and outputs it as it is as the wait signal 61.

Upon receiving the wait signal 61, the microprogram control circuit 50 extends the bus cycle instructed by the arithmetic unit 47 by the period during which the wait signal 61 is active. That is, in this case, the bus cycle is extended by inserting a wait cycle corresponding to four system clocks into two normal read cycles j, so that output to the parallel input/output port 46 is executed without any problem.

〔Effect of the invention〕

As explained above, the microprocessor of the present invention determines the wait cycle period required when accessing the memory and peripheral LSI based on the wait cycle information sent via the data bus. This allows the peripheral side to have information regarding its own access time and to give this wait cycle information to the microprocessor before accessing these memories or peripheral LSIs, thereby reducing the need for complex wait signal generation circuits. This has the effect of providing a microprocessor that can perform bus wait control without using it.

[Brief explanation of the drawing]

Figures 1 and 2 are for explaining one embodiment of the present invention. Figure 1 shows the configuration of a system in which a microprocessor is connected to three memories with different access times and a parallel input/output board. Figure 2 is a conceptual diagram showing the configuration of a wait cycle setting command, and Figure 3 is a diagram for explaining bus wait control by a conventional microprocessor. 1 is a block diagram showing the configuration of a system in which a parallel input/output board is connected to a parallel input/output board. 42...External data bus, 48...Wait register, 49...OR circuit, 50...Microprogram control circuit, 51...
... Data register, 52 ... Address register, 53 ... Internal data bus, 54 ... Timer enable 1 word, 55 ...
...Internal address bus, 56...External address bus, 57...Address enable signal, 61...
...Wait signal, 62...Internal wait instruction signal, 63...
...Internal wait signal, 64...External wait signal, 71...Read signal, 83...Write signal. Applicant: NEC Corporation

Claims (1)

[Claims] A memory or peripheral LSI decodes a wait number setting command sent through an external data bus, stores the number of wait cycles to be used in the following bus cycle, and receives an internal wait instruction signal to determine the wait number setting command. A wait register that generates an internal wait signal for a period indicated by the number of cycles, an external wait signal output from the memory or peripheral LSI, etc., and the internal wait signal are inputted, and a wait signal is output by calculating the logical sum of these. The OR circuit outputs an internal wait instruction signal, a data enable signal, and an address enable signal together with a write signal or a read signal, respectively, by receiving a write instruction or a read instruction from an internal data bus, and by receiving the wait signal, outputs an internal wait instruction signal, a data enable signal, and an address enable signal. a microprogram control circuit that adjusts the signal widths of the write signal, the read signal, the data enable signal, and the address enable signal according to the length of the wait signal; A microprocessor comprising: a data register for bus-coupling an external data bus; and an address register for receiving the address enable signal and coupling the internal address bus and the external address bus.